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-------------------------------------------------------------------
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-- System Generator version 13.2 VHDL source file.
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--
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-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
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-- text/file contains proprietary, confidential information of Xilinx,
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-- Inc., is distributed under license from Xilinx, Inc., and may be used,
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-- copied and/or disclosed only pursuant to the terms of a valid license
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-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
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-- this text/file solely for design, simulation, implementation and
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-- creation of design files limited to Xilinx devices or technologies.
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-- Use with non-Xilinx devices or technologies is expressly prohibited
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-- and immediately terminates your license unless covered by a separate
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-- agreement.
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--
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-- Xilinx is providing this design, code, or information "as is" solely
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-- for use in developing programs and solutions for Xilinx devices. By
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-- providing this design, code, or information as one possible
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-- implementation of this feature, application or standard, Xilinx is
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-- making no representation that this implementation is free from any
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-- claims of infringement. You are responsible for obtaining any rights
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-- you may require for your implementation. Xilinx expressly disclaims
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-- any warranty whatsoever with respect to the adequacy of the
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-- implementation, including but not limited to warranties of
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-- merchantability or fitness for a particular purpose.
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--
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-- Xilinx products are not intended for use in life support appliances,
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-- devices, or systems. Use in such applications is expressly prohibited.
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--
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-- Any modifications that are made to the source code are done at the user's
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-- sole risk and will be unsupported.
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--
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-- This copyright and support notice must be retained as part of this
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-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
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-- reserved.
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-------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package conv_pkg is
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constant simulating : boolean := false
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-- synopsys translate_off
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or true
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-- synopsys translate_on
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;
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constant xlUnsigned : integer := 1;
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constant xlSigned : integer := 2;
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constant xlFloat : integer := 3;
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constant xlWrap : integer := 1;
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constant xlSaturate : integer := 2;
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constant xlTruncate : integer := 1;
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constant xlRound : integer := 2;
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constant xlRoundBanker : integer := 3;
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constant xlAddMode : integer := 1;
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constant xlSubMode : integer := 2;
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attribute black_box : boolean;
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attribute syn_black_box : boolean;
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attribute fpga_dont_touch: string;
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attribute box_type : string;
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attribute keep : string;
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attribute syn_keep : boolean;
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function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
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function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
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function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
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function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
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function unsigned_to_signed(inp : unsigned) return signed;
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function signed_to_unsigned(inp : signed) return unsigned;
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function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
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function all_same(inp: std_logic_vector) return boolean;
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function all_zeros(inp: std_logic_vector) return boolean;
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function is_point_five(inp: std_logic_vector) return boolean;
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function all_ones(inp: std_logic_vector) return boolean;
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function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
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old_arith, new_width, new_bin_pt, new_arith,
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quantization, overflow : INTEGER)
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return std_logic_vector;
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function cast (inp : std_logic_vector; old_bin_pt,
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new_width, new_bin_pt, new_arith : INTEGER)
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return std_logic_vector;
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function shift_division_result(quotient, fraction: std_logic_vector;
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fraction_width, shift_value, shift_dir: INTEGER)
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return std_logic_vector;
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function shift_op (inp: std_logic_vector;
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result_width, shift_value, shift_dir: INTEGER)
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return std_logic_vector;
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function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
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return std_logic_vector;
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function s2u_slice (inp : signed; upper, lower : INTEGER)
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return unsigned;
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function u2u_slice (inp : unsigned; upper, lower : INTEGER)
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return unsigned;
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function s2s_cast (inp : signed; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return signed;
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function u2s_cast (inp : unsigned; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return signed;
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function s2u_cast (inp : signed; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return unsigned;
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function u2u_cast (inp : unsigned; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return unsigned;
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function u2v_cast (inp : unsigned; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return std_logic_vector;
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function s2v_cast (inp : signed; old_bin_pt,
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new_width, new_bin_pt : INTEGER)
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return std_logic_vector;
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function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
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new_width, new_bin_pt, new_arith : INTEGER)
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return std_logic_vector;
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function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
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old_arith, new_width, new_bin_pt,
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new_arith : INTEGER) return std_logic_vector;
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function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
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old_arith, new_width, new_bin_pt,
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new_arith : INTEGER) return std_logic_vector;
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function max_signed(width : INTEGER) return std_logic_vector;
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function min_signed(width : INTEGER) return std_logic_vector;
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function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
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old_arith, new_width, new_bin_pt, new_arith
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: INTEGER) return std_logic_vector;
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function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
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old_arith, new_width, new_bin_pt, new_arith : INTEGER)
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return std_logic_vector;
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function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
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function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
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return INTEGER;
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function sign_ext(inp : std_logic_vector; new_width : INTEGER)
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return std_logic_vector;
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function zero_ext(inp : std_logic_vector; new_width : INTEGER)
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return std_logic_vector;
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function zero_ext(inp : std_logic; new_width : INTEGER)
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return std_logic_vector;
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function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
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return std_logic_vector;
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function align_input(inp : std_logic_vector; old_width, delta, new_arith,
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new_width: INTEGER)
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return std_logic_vector;
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function pad_LSB(inp : std_logic_vector; new_width: integer)
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return std_logic_vector;
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function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
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return std_logic_vector;
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function max(L, R: INTEGER) return INTEGER;
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function min(L, R: INTEGER) return INTEGER;
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function "="(left,right: STRING) return boolean;
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function boolean_to_signed (inp : boolean; width: integer)
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return signed;
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function boolean_to_unsigned (inp : boolean; width: integer)
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return unsigned;
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function boolean_to_vector (inp : boolean)
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return std_logic_vector;
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function std_logic_to_vector (inp : std_logic)
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return std_logic_vector;
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function integer_to_std_logic_vector (inp : integer; width, arith : integer)
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return std_logic_vector;
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function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
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return integer;
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function std_logic_to_integer(constant inp : std_logic := '0')
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return integer;
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function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
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return std_logic_vector;
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function bin_string_to_std_logic_vector (inp : string)
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return std_logic_vector;
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function hex_string_to_std_logic_vector (inp : string; width : integer)
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return std_logic_vector;
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function makeZeroBinStr (width : integer) return STRING;
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function and_reduce(inp: std_logic_vector) return std_logic;
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-- synopsys translate_off
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function is_binary_string_invalid (inp : string)
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return boolean;
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function is_binary_string_undefined (inp : string)
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return boolean;
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function is_XorU(inp : std_logic_vector)
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return boolean;
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function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
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return real;
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function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
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return real;
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function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
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return std_logic_vector;
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function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
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return std_logic_vector;
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constant display_precision : integer := 20;
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function real_to_string (inp : real) return string;
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function valid_bin_string(inp : string) return boolean;
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function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
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function std_logic_to_bin_string(inp : std_logic) return string;
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function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
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return string;
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function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
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return string;
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type stdlogic_to_char_t is array(std_logic) of character;
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constant to_char : stdlogic_to_char_t := (
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'U' => 'U',
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'X' => 'X',
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'0' => '0',
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'1' => '1',
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'Z' => 'Z',
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'W' => 'W',
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'L' => 'L',
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'H' => 'H',
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'-' => '-');
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-- synopsys translate_on
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end conv_pkg;
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package body conv_pkg is
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function std_logic_vector_to_unsigned(inp : std_logic_vector)
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return unsigned
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is
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begin
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return unsigned (inp);
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end;
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function unsigned_to_std_logic_vector(inp : unsigned)
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return std_logic_vector
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is
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begin
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return std_logic_vector(inp);
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end;
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function std_logic_vector_to_signed(inp : std_logic_vector)
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return signed
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is
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begin
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return signed (inp);
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end;
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function signed_to_std_logic_vector(inp : signed)
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return std_logic_vector
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is
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begin
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return std_logic_vector(inp);
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end;
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function unsigned_to_signed (inp : unsigned)
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return signed
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is
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begin
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return signed(std_logic_vector(inp));
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end;
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function signed_to_unsigned (inp : signed)
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return unsigned
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is
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begin
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return unsigned(std_logic_vector(inp));
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end;
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function pos(inp : std_logic_vector; arith : INTEGER)
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return boolean
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is
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constant width : integer := inp'length;
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variable vec : std_logic_vector(width-1 downto 0);
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begin
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vec := inp;
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if arith = xlUnsigned then
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return true;
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else
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if vec(width-1) = '0' then
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return true;
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else
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return false;
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end if;
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end if;
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return true;
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end;
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function max_signed(width : INTEGER)
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return std_logic_vector
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is
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variable ones : std_logic_vector(width-2 downto 0);
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variable result : std_logic_vector(width-1 downto 0);
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begin
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ones := (others => '1');
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result(width-1) := '0';
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result(width-2 downto 0) := ones;
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return result;
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end;
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function min_signed(width : INTEGER)
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return std_logic_vector
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is
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variable zeros : std_logic_vector(width-2 downto 0);
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variable result : std_logic_vector(width-1 downto 0);
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begin
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zeros := (others => '0');
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result(width-1) := '1';
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result(width-2 downto 0) := zeros;
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return result;
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end;
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function and_reduce(inp: std_logic_vector) return std_logic
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is
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variable result: std_logic;
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constant width : integer := inp'length;
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variable vec : std_logic_vector(width-1 downto 0);
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begin
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vec := inp;
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result := vec(0);
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if width > 1 then
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for i in 1 to width-1 loop
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result := result and vec(i);
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end loop;
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end if;
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return result;
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end;
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function all_same(inp: std_logic_vector) return boolean
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is
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variable result: boolean;
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constant width : integer := inp'length;
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variable vec : std_logic_vector(width-1 downto 0);
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begin
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vec := inp;
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result := true;
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if width > 0 then
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for i in 1 to width-1 loop
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if vec(i) /= vec(0) then
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result := false;
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end if;
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end loop;
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end if;
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return result;
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end;
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function all_zeros(inp: std_logic_vector)
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return boolean
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is
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constant width : integer := inp'length;
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variable vec : std_logic_vector(width-1 downto 0);
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variable zero : std_logic_vector(width-1 downto 0);
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variable result : boolean;
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begin
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324 |
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zero := (others => '0');
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vec := inp;
|
326 |
|
|
-- synopsys translate_off
|
327 |
|
|
if (is_XorU(vec)) then
|
328 |
|
|
return false;
|
329 |
|
|
end if;
|
330 |
|
|
-- synopsys translate_on
|
331 |
|
|
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
|
332 |
|
|
result := true;
|
333 |
|
|
else
|
334 |
|
|
result := false;
|
335 |
|
|
end if;
|
336 |
|
|
return result;
|
337 |
|
|
end;
|
338 |
|
|
function is_point_five(inp: std_logic_vector)
|
339 |
|
|
return boolean
|
340 |
|
|
is
|
341 |
|
|
constant width : integer := inp'length;
|
342 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
343 |
|
|
variable result : boolean;
|
344 |
|
|
begin
|
345 |
|
|
vec := inp;
|
346 |
|
|
-- synopsys translate_off
|
347 |
|
|
if (is_XorU(vec)) then
|
348 |
|
|
return false;
|
349 |
|
|
end if;
|
350 |
|
|
-- synopsys translate_on
|
351 |
|
|
if (width > 1) then
|
352 |
|
|
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
|
353 |
|
|
result := true;
|
354 |
|
|
else
|
355 |
|
|
result := false;
|
356 |
|
|
end if;
|
357 |
|
|
else
|
358 |
|
|
if (vec(width-1) = '1') then
|
359 |
|
|
result := true;
|
360 |
|
|
else
|
361 |
|
|
result := false;
|
362 |
|
|
end if;
|
363 |
|
|
end if;
|
364 |
|
|
return result;
|
365 |
|
|
end;
|
366 |
|
|
function all_ones(inp: std_logic_vector)
|
367 |
|
|
return boolean
|
368 |
|
|
is
|
369 |
|
|
constant width : integer := inp'length;
|
370 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
371 |
|
|
variable one : std_logic_vector(width-1 downto 0);
|
372 |
|
|
variable result : boolean;
|
373 |
|
|
begin
|
374 |
|
|
one := (others => '1');
|
375 |
|
|
vec := inp;
|
376 |
|
|
-- synopsys translate_off
|
377 |
|
|
if (is_XorU(vec)) then
|
378 |
|
|
return false;
|
379 |
|
|
end if;
|
380 |
|
|
-- synopsys translate_on
|
381 |
|
|
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
|
382 |
|
|
result := true;
|
383 |
|
|
else
|
384 |
|
|
result := false;
|
385 |
|
|
end if;
|
386 |
|
|
return result;
|
387 |
|
|
end;
|
388 |
|
|
function full_precision_num_width(quantization, overflow, old_width,
|
389 |
|
|
old_bin_pt, old_arith,
|
390 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
391 |
|
|
return integer
|
392 |
|
|
is
|
393 |
|
|
variable result : integer;
|
394 |
|
|
begin
|
395 |
|
|
result := old_width + 2;
|
396 |
|
|
return result;
|
397 |
|
|
end;
|
398 |
|
|
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
|
399 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
400 |
|
|
: INTEGER)
|
401 |
|
|
return integer
|
402 |
|
|
is
|
403 |
|
|
variable right_of_dp, left_of_dp, result : integer;
|
404 |
|
|
begin
|
405 |
|
|
right_of_dp := max(new_bin_pt, old_bin_pt);
|
406 |
|
|
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
|
407 |
|
|
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
|
408 |
|
|
return result;
|
409 |
|
|
end;
|
410 |
|
|
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
|
411 |
|
|
old_arith, new_width, new_bin_pt, new_arith,
|
412 |
|
|
quantization, overflow : INTEGER)
|
413 |
|
|
return std_logic_vector
|
414 |
|
|
is
|
415 |
|
|
constant fp_width : integer :=
|
416 |
|
|
full_precision_num_width(quantization, overflow, old_width,
|
417 |
|
|
old_bin_pt, old_arith, new_width,
|
418 |
|
|
new_bin_pt, new_arith);
|
419 |
|
|
constant fp_bin_pt : integer := old_bin_pt;
|
420 |
|
|
constant fp_arith : integer := old_arith;
|
421 |
|
|
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
|
422 |
|
|
constant q_width : integer :=
|
423 |
|
|
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
|
424 |
|
|
old_arith, new_width, new_bin_pt, new_arith);
|
425 |
|
|
constant q_bin_pt : integer := new_bin_pt;
|
426 |
|
|
constant q_arith : integer := old_arith;
|
427 |
|
|
variable quantized_result : std_logic_vector(q_width-1 downto 0);
|
428 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
429 |
|
|
begin
|
430 |
|
|
result := (others => '0');
|
431 |
|
|
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
|
432 |
|
|
fp_arith);
|
433 |
|
|
if (quantization = xlRound) then
|
434 |
|
|
quantized_result := round_towards_inf(full_precision_result,
|
435 |
|
|
fp_width, fp_bin_pt,
|
436 |
|
|
fp_arith, q_width, q_bin_pt,
|
437 |
|
|
q_arith);
|
438 |
|
|
elsif (quantization = xlRoundBanker) then
|
439 |
|
|
quantized_result := round_towards_even(full_precision_result,
|
440 |
|
|
fp_width, fp_bin_pt,
|
441 |
|
|
fp_arith, q_width, q_bin_pt,
|
442 |
|
|
q_arith);
|
443 |
|
|
else
|
444 |
|
|
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
|
445 |
|
|
fp_arith, q_width, q_bin_pt, q_arith);
|
446 |
|
|
end if;
|
447 |
|
|
if (overflow = xlSaturate) then
|
448 |
|
|
result := saturation_arith(quantized_result, q_width, q_bin_pt,
|
449 |
|
|
q_arith, new_width, new_bin_pt, new_arith);
|
450 |
|
|
else
|
451 |
|
|
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
|
452 |
|
|
new_width, new_bin_pt, new_arith);
|
453 |
|
|
end if;
|
454 |
|
|
return result;
|
455 |
|
|
end;
|
456 |
|
|
function cast (inp : std_logic_vector; old_bin_pt, new_width,
|
457 |
|
|
new_bin_pt, new_arith : INTEGER)
|
458 |
|
|
return std_logic_vector
|
459 |
|
|
is
|
460 |
|
|
constant old_width : integer := inp'length;
|
461 |
|
|
constant left_of_dp : integer := (new_width - new_bin_pt)
|
462 |
|
|
- (old_width - old_bin_pt);
|
463 |
|
|
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
|
464 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
465 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
466 |
|
|
variable j : integer;
|
467 |
|
|
begin
|
468 |
|
|
vec := inp;
|
469 |
|
|
for i in new_width-1 downto 0 loop
|
470 |
|
|
j := i - right_of_dp;
|
471 |
|
|
if ( j > old_width-1) then
|
472 |
|
|
if (new_arith = xlUnsigned) then
|
473 |
|
|
result(i) := '0';
|
474 |
|
|
else
|
475 |
|
|
result(i) := vec(old_width-1);
|
476 |
|
|
end if;
|
477 |
|
|
elsif ( j >= 0) then
|
478 |
|
|
result(i) := vec(j);
|
479 |
|
|
else
|
480 |
|
|
result(i) := '0';
|
481 |
|
|
end if;
|
482 |
|
|
end loop;
|
483 |
|
|
return result;
|
484 |
|
|
end;
|
485 |
|
|
function shift_division_result(quotient, fraction: std_logic_vector;
|
486 |
|
|
fraction_width, shift_value, shift_dir: INTEGER)
|
487 |
|
|
return std_logic_vector
|
488 |
|
|
is
|
489 |
|
|
constant q_width : integer := quotient'length;
|
490 |
|
|
constant f_width : integer := fraction'length;
|
491 |
|
|
constant vec_MSB : integer := q_width+f_width-1;
|
492 |
|
|
constant result_MSB : integer := q_width+fraction_width-1;
|
493 |
|
|
constant result_LSB : integer := vec_MSB-result_MSB;
|
494 |
|
|
variable vec : std_logic_vector(vec_MSB downto 0);
|
495 |
|
|
variable result : std_logic_vector(result_MSB downto 0);
|
496 |
|
|
begin
|
497 |
|
|
vec := ( quotient & fraction );
|
498 |
|
|
if shift_dir = 1 then
|
499 |
|
|
for i in vec_MSB downto 0 loop
|
500 |
|
|
if (i < shift_value) then
|
501 |
|
|
vec(i) := '0';
|
502 |
|
|
else
|
503 |
|
|
vec(i) := vec(i-shift_value);
|
504 |
|
|
end if;
|
505 |
|
|
end loop;
|
506 |
|
|
else
|
507 |
|
|
for i in 0 to vec_MSB loop
|
508 |
|
|
if (i > vec_MSB-shift_value) then
|
509 |
|
|
vec(i) := vec(vec_MSB);
|
510 |
|
|
else
|
511 |
|
|
vec(i) := vec(i+shift_value);
|
512 |
|
|
end if;
|
513 |
|
|
end loop;
|
514 |
|
|
end if;
|
515 |
|
|
result := vec(vec_MSB downto result_LSB);
|
516 |
|
|
return result;
|
517 |
|
|
end;
|
518 |
|
|
function shift_op (inp: std_logic_vector;
|
519 |
|
|
result_width, shift_value, shift_dir: INTEGER)
|
520 |
|
|
return std_logic_vector
|
521 |
|
|
is
|
522 |
|
|
constant inp_width : integer := inp'length;
|
523 |
|
|
constant vec_MSB : integer := inp_width-1;
|
524 |
|
|
constant result_MSB : integer := result_width-1;
|
525 |
|
|
constant result_LSB : integer := vec_MSB-result_MSB;
|
526 |
|
|
variable vec : std_logic_vector(vec_MSB downto 0);
|
527 |
|
|
variable result : std_logic_vector(result_MSB downto 0);
|
528 |
|
|
begin
|
529 |
|
|
vec := inp;
|
530 |
|
|
if shift_dir = 1 then
|
531 |
|
|
for i in vec_MSB downto 0 loop
|
532 |
|
|
if (i < shift_value) then
|
533 |
|
|
vec(i) := '0';
|
534 |
|
|
else
|
535 |
|
|
vec(i) := vec(i-shift_value);
|
536 |
|
|
end if;
|
537 |
|
|
end loop;
|
538 |
|
|
else
|
539 |
|
|
for i in 0 to vec_MSB loop
|
540 |
|
|
if (i > vec_MSB-shift_value) then
|
541 |
|
|
vec(i) := vec(vec_MSB);
|
542 |
|
|
else
|
543 |
|
|
vec(i) := vec(i+shift_value);
|
544 |
|
|
end if;
|
545 |
|
|
end loop;
|
546 |
|
|
end if;
|
547 |
|
|
result := vec(vec_MSB downto result_LSB);
|
548 |
|
|
return result;
|
549 |
|
|
end;
|
550 |
|
|
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
|
551 |
|
|
return std_logic_vector
|
552 |
|
|
is
|
553 |
|
|
begin
|
554 |
|
|
return inp(upper downto lower);
|
555 |
|
|
end;
|
556 |
|
|
function s2u_slice (inp : signed; upper, lower : INTEGER)
|
557 |
|
|
return unsigned
|
558 |
|
|
is
|
559 |
|
|
begin
|
560 |
|
|
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
|
561 |
|
|
end;
|
562 |
|
|
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
|
563 |
|
|
return unsigned
|
564 |
|
|
is
|
565 |
|
|
begin
|
566 |
|
|
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
|
567 |
|
|
end;
|
568 |
|
|
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
|
569 |
|
|
return signed
|
570 |
|
|
is
|
571 |
|
|
begin
|
572 |
|
|
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
|
573 |
|
|
end;
|
574 |
|
|
function s2u_cast (inp : signed; old_bin_pt, new_width,
|
575 |
|
|
new_bin_pt : INTEGER)
|
576 |
|
|
return unsigned
|
577 |
|
|
is
|
578 |
|
|
begin
|
579 |
|
|
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
|
580 |
|
|
end;
|
581 |
|
|
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
|
582 |
|
|
new_bin_pt : INTEGER)
|
583 |
|
|
return signed
|
584 |
|
|
is
|
585 |
|
|
begin
|
586 |
|
|
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
|
587 |
|
|
end;
|
588 |
|
|
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
|
589 |
|
|
new_bin_pt : INTEGER)
|
590 |
|
|
return unsigned
|
591 |
|
|
is
|
592 |
|
|
begin
|
593 |
|
|
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
|
594 |
|
|
end;
|
595 |
|
|
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
|
596 |
|
|
new_bin_pt : INTEGER)
|
597 |
|
|
return std_logic_vector
|
598 |
|
|
is
|
599 |
|
|
begin
|
600 |
|
|
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
|
601 |
|
|
end;
|
602 |
|
|
function s2v_cast (inp : signed; old_bin_pt, new_width,
|
603 |
|
|
new_bin_pt : INTEGER)
|
604 |
|
|
return std_logic_vector
|
605 |
|
|
is
|
606 |
|
|
begin
|
607 |
|
|
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
|
608 |
|
|
end;
|
609 |
|
|
function boolean_to_signed (inp : boolean; width : integer)
|
610 |
|
|
return signed
|
611 |
|
|
is
|
612 |
|
|
variable result : signed(width - 1 downto 0);
|
613 |
|
|
begin
|
614 |
|
|
result := (others => '0');
|
615 |
|
|
if inp then
|
616 |
|
|
result(0) := '1';
|
617 |
|
|
else
|
618 |
|
|
result(0) := '0';
|
619 |
|
|
end if;
|
620 |
|
|
return result;
|
621 |
|
|
end;
|
622 |
|
|
function boolean_to_unsigned (inp : boolean; width : integer)
|
623 |
|
|
return unsigned
|
624 |
|
|
is
|
625 |
|
|
variable result : unsigned(width - 1 downto 0);
|
626 |
|
|
begin
|
627 |
|
|
result := (others => '0');
|
628 |
|
|
if inp then
|
629 |
|
|
result(0) := '1';
|
630 |
|
|
else
|
631 |
|
|
result(0) := '0';
|
632 |
|
|
end if;
|
633 |
|
|
return result;
|
634 |
|
|
end;
|
635 |
|
|
function boolean_to_vector (inp : boolean)
|
636 |
|
|
return std_logic_vector
|
637 |
|
|
is
|
638 |
|
|
variable result : std_logic_vector(1 - 1 downto 0);
|
639 |
|
|
begin
|
640 |
|
|
result := (others => '0');
|
641 |
|
|
if inp then
|
642 |
|
|
result(0) := '1';
|
643 |
|
|
else
|
644 |
|
|
result(0) := '0';
|
645 |
|
|
end if;
|
646 |
|
|
return result;
|
647 |
|
|
end;
|
648 |
|
|
function std_logic_to_vector (inp : std_logic)
|
649 |
|
|
return std_logic_vector
|
650 |
|
|
is
|
651 |
|
|
variable result : std_logic_vector(1 - 1 downto 0);
|
652 |
|
|
begin
|
653 |
|
|
result(0) := inp;
|
654 |
|
|
return result;
|
655 |
|
|
end;
|
656 |
|
|
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
|
657 |
|
|
new_width, new_bin_pt, new_arith : INTEGER)
|
658 |
|
|
return std_logic_vector
|
659 |
|
|
is
|
660 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
661 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
662 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
663 |
|
|
begin
|
664 |
|
|
vec := inp;
|
665 |
|
|
if right_of_dp >= 0 then
|
666 |
|
|
if new_arith = xlUnsigned then
|
667 |
|
|
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
|
668 |
|
|
else
|
669 |
|
|
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
|
670 |
|
|
end if;
|
671 |
|
|
else
|
672 |
|
|
if new_arith = xlUnsigned then
|
673 |
|
|
result := zero_ext(pad_LSB(vec, old_width +
|
674 |
|
|
abs(right_of_dp)), new_width);
|
675 |
|
|
else
|
676 |
|
|
result := sign_ext(pad_LSB(vec, old_width +
|
677 |
|
|
abs(right_of_dp)), new_width);
|
678 |
|
|
end if;
|
679 |
|
|
end if;
|
680 |
|
|
return result;
|
681 |
|
|
end;
|
682 |
|
|
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
|
683 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
684 |
|
|
: INTEGER)
|
685 |
|
|
return std_logic_vector
|
686 |
|
|
is
|
687 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
688 |
|
|
constant expected_new_width : integer := old_width - right_of_dp + 1;
|
689 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
690 |
|
|
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
|
691 |
|
|
variable truncated_val : std_logic_vector(new_width-1 downto 0);
|
692 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
693 |
|
|
begin
|
694 |
|
|
vec := inp;
|
695 |
|
|
if right_of_dp >= 0 then
|
696 |
|
|
if new_arith = xlUnsigned then
|
697 |
|
|
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
|
698 |
|
|
new_width);
|
699 |
|
|
else
|
700 |
|
|
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
|
701 |
|
|
new_width);
|
702 |
|
|
end if;
|
703 |
|
|
else
|
704 |
|
|
if new_arith = xlUnsigned then
|
705 |
|
|
truncated_val := zero_ext(pad_LSB(vec, old_width +
|
706 |
|
|
abs(right_of_dp)), new_width);
|
707 |
|
|
else
|
708 |
|
|
truncated_val := sign_ext(pad_LSB(vec, old_width +
|
709 |
|
|
abs(right_of_dp)), new_width);
|
710 |
|
|
end if;
|
711 |
|
|
end if;
|
712 |
|
|
one_or_zero := (others => '0');
|
713 |
|
|
if (new_arith = xlSigned) then
|
714 |
|
|
if (vec(old_width-1) = '0') then
|
715 |
|
|
one_or_zero(0) := '1';
|
716 |
|
|
end if;
|
717 |
|
|
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
|
718 |
|
|
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
|
719 |
|
|
one_or_zero(0) := '1';
|
720 |
|
|
end if;
|
721 |
|
|
end if;
|
722 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
723 |
|
|
if vec(right_of_dp-1) = '0' then
|
724 |
|
|
one_or_zero(0) := '0';
|
725 |
|
|
end if;
|
726 |
|
|
else
|
727 |
|
|
one_or_zero(0) := '0';
|
728 |
|
|
end if;
|
729 |
|
|
else
|
730 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
731 |
|
|
one_or_zero(0) := vec(right_of_dp-1);
|
732 |
|
|
end if;
|
733 |
|
|
end if;
|
734 |
|
|
if new_arith = xlSigned then
|
735 |
|
|
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
|
736 |
|
|
std_logic_vector_to_signed(one_or_zero));
|
737 |
|
|
else
|
738 |
|
|
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
|
739 |
|
|
std_logic_vector_to_unsigned(one_or_zero));
|
740 |
|
|
end if;
|
741 |
|
|
return result;
|
742 |
|
|
end;
|
743 |
|
|
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
|
744 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
745 |
|
|
: INTEGER)
|
746 |
|
|
return std_logic_vector
|
747 |
|
|
is
|
748 |
|
|
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
|
749 |
|
|
constant expected_new_width : integer := old_width - right_of_dp + 1;
|
750 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
751 |
|
|
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
|
752 |
|
|
variable truncated_val : std_logic_vector(new_width-1 downto 0);
|
753 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
754 |
|
|
begin
|
755 |
|
|
vec := inp;
|
756 |
|
|
if right_of_dp >= 0 then
|
757 |
|
|
if new_arith = xlUnsigned then
|
758 |
|
|
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
|
759 |
|
|
new_width);
|
760 |
|
|
else
|
761 |
|
|
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
|
762 |
|
|
new_width);
|
763 |
|
|
end if;
|
764 |
|
|
else
|
765 |
|
|
if new_arith = xlUnsigned then
|
766 |
|
|
truncated_val := zero_ext(pad_LSB(vec, old_width +
|
767 |
|
|
abs(right_of_dp)), new_width);
|
768 |
|
|
else
|
769 |
|
|
truncated_val := sign_ext(pad_LSB(vec, old_width +
|
770 |
|
|
abs(right_of_dp)), new_width);
|
771 |
|
|
end if;
|
772 |
|
|
end if;
|
773 |
|
|
one_or_zero := (others => '0');
|
774 |
|
|
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
|
775 |
|
|
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
|
776 |
|
|
one_or_zero(0) := vec(right_of_dp-1);
|
777 |
|
|
else
|
778 |
|
|
one_or_zero(0) := vec(right_of_dp);
|
779 |
|
|
end if;
|
780 |
|
|
end if;
|
781 |
|
|
if new_arith = xlSigned then
|
782 |
|
|
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
|
783 |
|
|
std_logic_vector_to_signed(one_or_zero));
|
784 |
|
|
else
|
785 |
|
|
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
|
786 |
|
|
std_logic_vector_to_unsigned(one_or_zero));
|
787 |
|
|
end if;
|
788 |
|
|
return result;
|
789 |
|
|
end;
|
790 |
|
|
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
791 |
|
|
old_arith, new_width, new_bin_pt, new_arith
|
792 |
|
|
: INTEGER)
|
793 |
|
|
return std_logic_vector
|
794 |
|
|
is
|
795 |
|
|
constant left_of_dp : integer := (old_width - old_bin_pt) -
|
796 |
|
|
(new_width - new_bin_pt);
|
797 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
798 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
799 |
|
|
variable overflow : boolean;
|
800 |
|
|
begin
|
801 |
|
|
vec := inp;
|
802 |
|
|
overflow := true;
|
803 |
|
|
result := (others => '0');
|
804 |
|
|
if (new_width >= old_width) then
|
805 |
|
|
overflow := false;
|
806 |
|
|
end if;
|
807 |
|
|
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
|
808 |
|
|
if all_same(vec(old_width-1 downto new_width-1)) then
|
809 |
|
|
overflow := false;
|
810 |
|
|
end if;
|
811 |
|
|
end if;
|
812 |
|
|
if (old_arith = xlSigned and new_arith = xlUnsigned) then
|
813 |
|
|
if (old_width > new_width) then
|
814 |
|
|
if all_zeros(vec(old_width-1 downto new_width)) then
|
815 |
|
|
overflow := false;
|
816 |
|
|
end if;
|
817 |
|
|
else
|
818 |
|
|
if (old_width = new_width) then
|
819 |
|
|
if (vec(new_width-1) = '0') then
|
820 |
|
|
overflow := false;
|
821 |
|
|
end if;
|
822 |
|
|
end if;
|
823 |
|
|
end if;
|
824 |
|
|
end if;
|
825 |
|
|
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
|
826 |
|
|
if (old_width > new_width) then
|
827 |
|
|
if all_zeros(vec(old_width-1 downto new_width)) then
|
828 |
|
|
overflow := false;
|
829 |
|
|
end if;
|
830 |
|
|
else
|
831 |
|
|
if (old_width = new_width) then
|
832 |
|
|
overflow := false;
|
833 |
|
|
end if;
|
834 |
|
|
end if;
|
835 |
|
|
end if;
|
836 |
|
|
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
|
837 |
|
|
if all_same(vec(old_width-1 downto new_width-1)) then
|
838 |
|
|
overflow := false;
|
839 |
|
|
end if;
|
840 |
|
|
end if;
|
841 |
|
|
if overflow then
|
842 |
|
|
if new_arith = xlSigned then
|
843 |
|
|
if vec(old_width-1) = '0' then
|
844 |
|
|
result := max_signed(new_width);
|
845 |
|
|
else
|
846 |
|
|
result := min_signed(new_width);
|
847 |
|
|
end if;
|
848 |
|
|
else
|
849 |
|
|
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
|
850 |
|
|
result := (others => '0');
|
851 |
|
|
else
|
852 |
|
|
result := (others => '1');
|
853 |
|
|
end if;
|
854 |
|
|
end if;
|
855 |
|
|
else
|
856 |
|
|
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
|
857 |
|
|
if (vec(old_width-1) = '1') then
|
858 |
|
|
vec := (others => '0');
|
859 |
|
|
end if;
|
860 |
|
|
end if;
|
861 |
|
|
if new_width <= old_width then
|
862 |
|
|
result := vec(new_width-1 downto 0);
|
863 |
|
|
else
|
864 |
|
|
if new_arith = xlUnsigned then
|
865 |
|
|
result := zero_ext(vec, new_width);
|
866 |
|
|
else
|
867 |
|
|
result := sign_ext(vec, new_width);
|
868 |
|
|
end if;
|
869 |
|
|
end if;
|
870 |
|
|
end if;
|
871 |
|
|
return result;
|
872 |
|
|
end;
|
873 |
|
|
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
|
874 |
|
|
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
|
875 |
|
|
return std_logic_vector
|
876 |
|
|
is
|
877 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
878 |
|
|
variable result_arith : integer;
|
879 |
|
|
begin
|
880 |
|
|
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
|
881 |
|
|
result_arith := xlSigned;
|
882 |
|
|
end if;
|
883 |
|
|
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
|
884 |
|
|
return result;
|
885 |
|
|
end;
|
886 |
|
|
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
|
887 |
|
|
begin
|
888 |
|
|
return max(a_bin_pt, b_bin_pt);
|
889 |
|
|
end;
|
890 |
|
|
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
|
891 |
|
|
return INTEGER is
|
892 |
|
|
begin
|
893 |
|
|
return max(a_width - a_bin_pt, b_width - b_bin_pt);
|
894 |
|
|
end;
|
895 |
|
|
function pad_LSB(inp : std_logic_vector; new_width: integer)
|
896 |
|
|
return STD_LOGIC_VECTOR
|
897 |
|
|
is
|
898 |
|
|
constant orig_width : integer := inp'length;
|
899 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
900 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
901 |
|
|
variable pos : integer;
|
902 |
|
|
constant pad_pos : integer := new_width - orig_width - 1;
|
903 |
|
|
begin
|
904 |
|
|
vec := inp;
|
905 |
|
|
pos := new_width-1;
|
906 |
|
|
if (new_width >= orig_width) then
|
907 |
|
|
for i in orig_width-1 downto 0 loop
|
908 |
|
|
result(pos) := vec(i);
|
909 |
|
|
pos := pos - 1;
|
910 |
|
|
end loop;
|
911 |
|
|
if pad_pos >= 0 then
|
912 |
|
|
for i in pad_pos downto 0 loop
|
913 |
|
|
result(i) := '0';
|
914 |
|
|
end loop;
|
915 |
|
|
end if;
|
916 |
|
|
end if;
|
917 |
|
|
return result;
|
918 |
|
|
end;
|
919 |
|
|
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
|
920 |
|
|
return std_logic_vector
|
921 |
|
|
is
|
922 |
|
|
constant old_width : integer := inp'length;
|
923 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
924 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
925 |
|
|
begin
|
926 |
|
|
vec := inp;
|
927 |
|
|
if new_width >= old_width then
|
928 |
|
|
result(old_width-1 downto 0) := vec;
|
929 |
|
|
if new_width-1 >= old_width then
|
930 |
|
|
for i in new_width-1 downto old_width loop
|
931 |
|
|
result(i) := vec(old_width-1);
|
932 |
|
|
end loop;
|
933 |
|
|
end if;
|
934 |
|
|
else
|
935 |
|
|
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
|
936 |
|
|
end if;
|
937 |
|
|
return result;
|
938 |
|
|
end;
|
939 |
|
|
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
|
940 |
|
|
return std_logic_vector
|
941 |
|
|
is
|
942 |
|
|
constant old_width : integer := inp'length;
|
943 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
944 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
945 |
|
|
begin
|
946 |
|
|
vec := inp;
|
947 |
|
|
if new_width >= old_width then
|
948 |
|
|
result(old_width-1 downto 0) := vec;
|
949 |
|
|
if new_width-1 >= old_width then
|
950 |
|
|
for i in new_width-1 downto old_width loop
|
951 |
|
|
result(i) := '0';
|
952 |
|
|
end loop;
|
953 |
|
|
end if;
|
954 |
|
|
else
|
955 |
|
|
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
|
956 |
|
|
end if;
|
957 |
|
|
return result;
|
958 |
|
|
end;
|
959 |
|
|
function zero_ext(inp : std_logic; new_width : INTEGER)
|
960 |
|
|
return std_logic_vector
|
961 |
|
|
is
|
962 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
963 |
|
|
begin
|
964 |
|
|
result(0) := inp;
|
965 |
|
|
for i in new_width-1 downto 1 loop
|
966 |
|
|
result(i) := '0';
|
967 |
|
|
end loop;
|
968 |
|
|
return result;
|
969 |
|
|
end;
|
970 |
|
|
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
|
971 |
|
|
return std_logic_vector
|
972 |
|
|
is
|
973 |
|
|
constant orig_width : integer := inp'length;
|
974 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
975 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
976 |
|
|
begin
|
977 |
|
|
vec := inp;
|
978 |
|
|
if arith = xlUnsigned then
|
979 |
|
|
result := zero_ext(vec, new_width);
|
980 |
|
|
else
|
981 |
|
|
result := sign_ext(vec, new_width);
|
982 |
|
|
end if;
|
983 |
|
|
return result;
|
984 |
|
|
end;
|
985 |
|
|
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
|
986 |
|
|
return STD_LOGIC_VECTOR
|
987 |
|
|
is
|
988 |
|
|
constant orig_width : integer := inp'length;
|
989 |
|
|
variable vec : std_logic_vector(orig_width-1 downto 0);
|
990 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
991 |
|
|
variable pos : integer;
|
992 |
|
|
begin
|
993 |
|
|
vec := inp;
|
994 |
|
|
pos := new_width-1;
|
995 |
|
|
if (arith = xlUnsigned) then
|
996 |
|
|
result(pos) := '0';
|
997 |
|
|
pos := pos - 1;
|
998 |
|
|
else
|
999 |
|
|
result(pos) := vec(orig_width-1);
|
1000 |
|
|
pos := pos - 1;
|
1001 |
|
|
end if;
|
1002 |
|
|
if (new_width >= orig_width) then
|
1003 |
|
|
for i in orig_width-1 downto 0 loop
|
1004 |
|
|
result(pos) := vec(i);
|
1005 |
|
|
pos := pos - 1;
|
1006 |
|
|
end loop;
|
1007 |
|
|
if pos >= 0 then
|
1008 |
|
|
for i in pos downto 0 loop
|
1009 |
|
|
result(i) := '0';
|
1010 |
|
|
end loop;
|
1011 |
|
|
end if;
|
1012 |
|
|
end if;
|
1013 |
|
|
return result;
|
1014 |
|
|
end;
|
1015 |
|
|
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
|
1016 |
|
|
new_width: INTEGER)
|
1017 |
|
|
return std_logic_vector
|
1018 |
|
|
is
|
1019 |
|
|
variable vec : std_logic_vector(old_width-1 downto 0);
|
1020 |
|
|
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
|
1021 |
|
|
variable result : std_logic_vector(new_width-1 downto 0);
|
1022 |
|
|
begin
|
1023 |
|
|
vec := inp;
|
1024 |
|
|
if delta > 0 then
|
1025 |
|
|
padded_inp := pad_LSB(vec, old_width+delta);
|
1026 |
|
|
result := extend_MSB(padded_inp, new_width, new_arith);
|
1027 |
|
|
else
|
1028 |
|
|
result := extend_MSB(vec, new_width, new_arith);
|
1029 |
|
|
end if;
|
1030 |
|
|
return result;
|
1031 |
|
|
end;
|
1032 |
|
|
function max(L, R: INTEGER) return INTEGER is
|
1033 |
|
|
begin
|
1034 |
|
|
if L > R then
|
1035 |
|
|
return L;
|
1036 |
|
|
else
|
1037 |
|
|
return R;
|
1038 |
|
|
end if;
|
1039 |
|
|
end;
|
1040 |
|
|
function min(L, R: INTEGER) return INTEGER is
|
1041 |
|
|
begin
|
1042 |
|
|
if L < R then
|
1043 |
|
|
return L;
|
1044 |
|
|
else
|
1045 |
|
|
return R;
|
1046 |
|
|
end if;
|
1047 |
|
|
end;
|
1048 |
|
|
function "="(left,right: STRING) return boolean is
|
1049 |
|
|
begin
|
1050 |
|
|
if (left'length /= right'length) then
|
1051 |
|
|
return false;
|
1052 |
|
|
else
|
1053 |
|
|
test : for i in 1 to left'length loop
|
1054 |
|
|
if left(i) /= right(i) then
|
1055 |
|
|
return false;
|
1056 |
|
|
end if;
|
1057 |
|
|
end loop test;
|
1058 |
|
|
return true;
|
1059 |
|
|
end if;
|
1060 |
|
|
end;
|
1061 |
|
|
-- synopsys translate_off
|
1062 |
|
|
function is_binary_string_invalid (inp : string)
|
1063 |
|
|
return boolean
|
1064 |
|
|
is
|
1065 |
|
|
variable vec : string(1 to inp'length);
|
1066 |
|
|
variable result : boolean;
|
1067 |
|
|
begin
|
1068 |
|
|
vec := inp;
|
1069 |
|
|
result := false;
|
1070 |
|
|
for i in 1 to vec'length loop
|
1071 |
|
|
if ( vec(i) = 'X' ) then
|
1072 |
|
|
result := true;
|
1073 |
|
|
end if;
|
1074 |
|
|
end loop;
|
1075 |
|
|
return result;
|
1076 |
|
|
end;
|
1077 |
|
|
function is_binary_string_undefined (inp : string)
|
1078 |
|
|
return boolean
|
1079 |
|
|
is
|
1080 |
|
|
variable vec : string(1 to inp'length);
|
1081 |
|
|
variable result : boolean;
|
1082 |
|
|
begin
|
1083 |
|
|
vec := inp;
|
1084 |
|
|
result := false;
|
1085 |
|
|
for i in 1 to vec'length loop
|
1086 |
|
|
if ( vec(i) = 'U' ) then
|
1087 |
|
|
result := true;
|
1088 |
|
|
end if;
|
1089 |
|
|
end loop;
|
1090 |
|
|
return result;
|
1091 |
|
|
end;
|
1092 |
|
|
function is_XorU(inp : std_logic_vector)
|
1093 |
|
|
return boolean
|
1094 |
|
|
is
|
1095 |
|
|
constant width : integer := inp'length;
|
1096 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1097 |
|
|
variable result : boolean;
|
1098 |
|
|
begin
|
1099 |
|
|
vec := inp;
|
1100 |
|
|
result := false;
|
1101 |
|
|
for i in 0 to width-1 loop
|
1102 |
|
|
if (vec(i) = 'U') or (vec(i) = 'X') then
|
1103 |
|
|
result := true;
|
1104 |
|
|
end if;
|
1105 |
|
|
end loop;
|
1106 |
|
|
return result;
|
1107 |
|
|
end;
|
1108 |
|
|
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
|
1109 |
|
|
return real
|
1110 |
|
|
is
|
1111 |
|
|
variable vec : std_logic_vector(inp'length-1 downto 0);
|
1112 |
|
|
variable result, shift_val, undefined_real : real;
|
1113 |
|
|
variable neg_num : boolean;
|
1114 |
|
|
begin
|
1115 |
|
|
vec := inp;
|
1116 |
|
|
result := 0.0;
|
1117 |
|
|
neg_num := false;
|
1118 |
|
|
if vec(inp'length-1) = '1' then
|
1119 |
|
|
neg_num := true;
|
1120 |
|
|
end if;
|
1121 |
|
|
for i in 0 to inp'length-1 loop
|
1122 |
|
|
if vec(i) = 'U' or vec(i) = 'X' then
|
1123 |
|
|
return undefined_real;
|
1124 |
|
|
end if;
|
1125 |
|
|
if arith = xlSigned then
|
1126 |
|
|
if neg_num then
|
1127 |
|
|
if vec(i) = '0' then
|
1128 |
|
|
result := result + 2.0**i;
|
1129 |
|
|
end if;
|
1130 |
|
|
else
|
1131 |
|
|
if vec(i) = '1' then
|
1132 |
|
|
result := result + 2.0**i;
|
1133 |
|
|
end if;
|
1134 |
|
|
end if;
|
1135 |
|
|
else
|
1136 |
|
|
if vec(i) = '1' then
|
1137 |
|
|
result := result + 2.0**i;
|
1138 |
|
|
end if;
|
1139 |
|
|
end if;
|
1140 |
|
|
end loop;
|
1141 |
|
|
if arith = xlSigned then
|
1142 |
|
|
if neg_num then
|
1143 |
|
|
result := result + 1.0;
|
1144 |
|
|
result := result * (-1.0);
|
1145 |
|
|
end if;
|
1146 |
|
|
end if;
|
1147 |
|
|
shift_val := 2.0**(-1*bin_pt);
|
1148 |
|
|
result := result * shift_val;
|
1149 |
|
|
return result;
|
1150 |
|
|
end;
|
1151 |
|
|
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
|
1152 |
|
|
return real
|
1153 |
|
|
is
|
1154 |
|
|
variable result : real := 0.0;
|
1155 |
|
|
begin
|
1156 |
|
|
if inp = '1' then
|
1157 |
|
|
result := 1.0;
|
1158 |
|
|
end if;
|
1159 |
|
|
if arith = xlSigned then
|
1160 |
|
|
assert false
|
1161 |
|
|
report "It doesn't make sense to convert a 1 bit number to a signed real.";
|
1162 |
|
|
end if;
|
1163 |
|
|
return result;
|
1164 |
|
|
end;
|
1165 |
|
|
-- synopsys translate_on
|
1166 |
|
|
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
|
1167 |
|
|
return std_logic_vector
|
1168 |
|
|
is
|
1169 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1170 |
|
|
variable unsigned_val : unsigned(width-1 downto 0);
|
1171 |
|
|
variable signed_val : signed(width-1 downto 0);
|
1172 |
|
|
begin
|
1173 |
|
|
if (arith = xlSigned) then
|
1174 |
|
|
signed_val := to_signed(inp, width);
|
1175 |
|
|
result := signed_to_std_logic_vector(signed_val);
|
1176 |
|
|
else
|
1177 |
|
|
unsigned_val := to_unsigned(inp, width);
|
1178 |
|
|
result := unsigned_to_std_logic_vector(unsigned_val);
|
1179 |
|
|
end if;
|
1180 |
|
|
return result;
|
1181 |
|
|
end;
|
1182 |
|
|
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
|
1183 |
|
|
return integer
|
1184 |
|
|
is
|
1185 |
|
|
constant width : integer := inp'length;
|
1186 |
|
|
variable unsigned_val : unsigned(width-1 downto 0);
|
1187 |
|
|
variable signed_val : signed(width-1 downto 0);
|
1188 |
|
|
variable result : integer;
|
1189 |
|
|
begin
|
1190 |
|
|
if (arith = xlSigned) then
|
1191 |
|
|
signed_val := std_logic_vector_to_signed(inp);
|
1192 |
|
|
result := to_integer(signed_val);
|
1193 |
|
|
else
|
1194 |
|
|
unsigned_val := std_logic_vector_to_unsigned(inp);
|
1195 |
|
|
result := to_integer(unsigned_val);
|
1196 |
|
|
end if;
|
1197 |
|
|
return result;
|
1198 |
|
|
end;
|
1199 |
|
|
function std_logic_to_integer(constant inp : std_logic := '0')
|
1200 |
|
|
return integer
|
1201 |
|
|
is
|
1202 |
|
|
begin
|
1203 |
|
|
if inp = '1' then
|
1204 |
|
|
return 1;
|
1205 |
|
|
else
|
1206 |
|
|
return 0;
|
1207 |
|
|
end if;
|
1208 |
|
|
end;
|
1209 |
|
|
function makeZeroBinStr (width : integer) return STRING is
|
1210 |
|
|
variable result : string(1 to width+3);
|
1211 |
|
|
begin
|
1212 |
|
|
result(1) := '0';
|
1213 |
|
|
result(2) := 'b';
|
1214 |
|
|
for i in 3 to width+2 loop
|
1215 |
|
|
result(i) := '0';
|
1216 |
|
|
end loop;
|
1217 |
|
|
result(width+3) := '.';
|
1218 |
|
|
return result;
|
1219 |
|
|
end;
|
1220 |
|
|
-- synopsys translate_off
|
1221 |
|
|
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
|
1222 |
|
|
return std_logic_vector
|
1223 |
|
|
is
|
1224 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1225 |
|
|
begin
|
1226 |
|
|
result := (others => '0');
|
1227 |
|
|
return result;
|
1228 |
|
|
end;
|
1229 |
|
|
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
|
1230 |
|
|
return std_logic_vector
|
1231 |
|
|
is
|
1232 |
|
|
variable real_val : real;
|
1233 |
|
|
variable int_val : integer;
|
1234 |
|
|
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
|
1235 |
|
|
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
|
1236 |
|
|
variable signed_val : signed(width-1 downto 0) := (others => '0');
|
1237 |
|
|
begin
|
1238 |
|
|
real_val := inp;
|
1239 |
|
|
int_val := integer(real_val * 2.0**(bin_pt));
|
1240 |
|
|
if (arith = xlSigned) then
|
1241 |
|
|
signed_val := to_signed(int_val, width);
|
1242 |
|
|
result := signed_to_std_logic_vector(signed_val);
|
1243 |
|
|
else
|
1244 |
|
|
unsigned_val := to_unsigned(int_val, width);
|
1245 |
|
|
result := unsigned_to_std_logic_vector(unsigned_val);
|
1246 |
|
|
end if;
|
1247 |
|
|
return result;
|
1248 |
|
|
end;
|
1249 |
|
|
-- synopsys translate_on
|
1250 |
|
|
function valid_bin_string (inp : string)
|
1251 |
|
|
return boolean
|
1252 |
|
|
is
|
1253 |
|
|
variable vec : string(1 to inp'length);
|
1254 |
|
|
begin
|
1255 |
|
|
vec := inp;
|
1256 |
|
|
if (vec(1) = '0' and vec(2) = 'b') then
|
1257 |
|
|
return true;
|
1258 |
|
|
else
|
1259 |
|
|
return false;
|
1260 |
|
|
end if;
|
1261 |
|
|
end;
|
1262 |
|
|
function hex_string_to_std_logic_vector(inp: string; width : integer)
|
1263 |
|
|
return std_logic_vector is
|
1264 |
|
|
constant strlen : integer := inp'LENGTH;
|
1265 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1266 |
|
|
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
|
1267 |
|
|
variable posn : integer;
|
1268 |
|
|
variable ch : character;
|
1269 |
|
|
variable vec : string(1 to strlen);
|
1270 |
|
|
begin
|
1271 |
|
|
vec := inp;
|
1272 |
|
|
result := (others => '0');
|
1273 |
|
|
posn := (strlen*4)-1;
|
1274 |
|
|
for i in 1 to strlen loop
|
1275 |
|
|
ch := vec(i);
|
1276 |
|
|
case ch is
|
1277 |
|
|
when '0' => bitval(posn downto posn-3) := "0000";
|
1278 |
|
|
when '1' => bitval(posn downto posn-3) := "0001";
|
1279 |
|
|
when '2' => bitval(posn downto posn-3) := "0010";
|
1280 |
|
|
when '3' => bitval(posn downto posn-3) := "0011";
|
1281 |
|
|
when '4' => bitval(posn downto posn-3) := "0100";
|
1282 |
|
|
when '5' => bitval(posn downto posn-3) := "0101";
|
1283 |
|
|
when '6' => bitval(posn downto posn-3) := "0110";
|
1284 |
|
|
when '7' => bitval(posn downto posn-3) := "0111";
|
1285 |
|
|
when '8' => bitval(posn downto posn-3) := "1000";
|
1286 |
|
|
when '9' => bitval(posn downto posn-3) := "1001";
|
1287 |
|
|
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
|
1288 |
|
|
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
|
1289 |
|
|
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
|
1290 |
|
|
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
|
1291 |
|
|
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
|
1292 |
|
|
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
|
1293 |
|
|
when others => bitval(posn downto posn-3) := "XXXX";
|
1294 |
|
|
-- synopsys translate_off
|
1295 |
|
|
ASSERT false
|
1296 |
|
|
REPORT "Invalid hex value" SEVERITY ERROR;
|
1297 |
|
|
-- synopsys translate_on
|
1298 |
|
|
end case;
|
1299 |
|
|
posn := posn - 4;
|
1300 |
|
|
end loop;
|
1301 |
|
|
if (width <= strlen*4) then
|
1302 |
|
|
result := bitval(width-1 downto 0);
|
1303 |
|
|
else
|
1304 |
|
|
result((strlen*4)-1 downto 0) := bitval;
|
1305 |
|
|
end if;
|
1306 |
|
|
return result;
|
1307 |
|
|
end;
|
1308 |
|
|
function bin_string_to_std_logic_vector (inp : string)
|
1309 |
|
|
return std_logic_vector
|
1310 |
|
|
is
|
1311 |
|
|
variable pos : integer;
|
1312 |
|
|
variable vec : string(1 to inp'length);
|
1313 |
|
|
variable result : std_logic_vector(inp'length-1 downto 0);
|
1314 |
|
|
begin
|
1315 |
|
|
vec := inp;
|
1316 |
|
|
pos := inp'length-1;
|
1317 |
|
|
result := (others => '0');
|
1318 |
|
|
for i in 1 to vec'length loop
|
1319 |
|
|
-- synopsys translate_off
|
1320 |
|
|
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
|
1321 |
|
|
assert false
|
1322 |
|
|
report "Input string is larger than output std_logic_vector. Truncating output.";
|
1323 |
|
|
return result;
|
1324 |
|
|
end if;
|
1325 |
|
|
-- synopsys translate_on
|
1326 |
|
|
if vec(i) = '0' then
|
1327 |
|
|
result(pos) := '0';
|
1328 |
|
|
pos := pos - 1;
|
1329 |
|
|
end if;
|
1330 |
|
|
if vec(i) = '1' then
|
1331 |
|
|
result(pos) := '1';
|
1332 |
|
|
pos := pos - 1;
|
1333 |
|
|
end if;
|
1334 |
|
|
-- synopsys translate_off
|
1335 |
|
|
if (vec(i) = 'X' or vec(i) = 'U') then
|
1336 |
|
|
result(pos) := 'U';
|
1337 |
|
|
pos := pos - 1;
|
1338 |
|
|
end if;
|
1339 |
|
|
-- synopsys translate_on
|
1340 |
|
|
end loop;
|
1341 |
|
|
return result;
|
1342 |
|
|
end;
|
1343 |
|
|
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
|
1344 |
|
|
return std_logic_vector
|
1345 |
|
|
is
|
1346 |
|
|
constant str_width : integer := width + 4;
|
1347 |
|
|
constant inp_len : integer := inp'length;
|
1348 |
|
|
constant num_elements : integer := (inp_len + 1)/str_width;
|
1349 |
|
|
constant reverse_index : integer := (num_elements-1) - index;
|
1350 |
|
|
variable left_pos : integer;
|
1351 |
|
|
variable right_pos : integer;
|
1352 |
|
|
variable vec : string(1 to inp'length);
|
1353 |
|
|
variable result : std_logic_vector(width-1 downto 0);
|
1354 |
|
|
begin
|
1355 |
|
|
vec := inp;
|
1356 |
|
|
result := (others => '0');
|
1357 |
|
|
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
|
1358 |
|
|
left_pos := 1;
|
1359 |
|
|
right_pos := width + 3;
|
1360 |
|
|
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
|
1361 |
|
|
end if;
|
1362 |
|
|
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
|
1363 |
|
|
left_pos := (reverse_index * str_width) + 1;
|
1364 |
|
|
right_pos := left_pos + width + 2;
|
1365 |
|
|
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
|
1366 |
|
|
end if;
|
1367 |
|
|
return result;
|
1368 |
|
|
end;
|
1369 |
|
|
-- synopsys translate_off
|
1370 |
|
|
function std_logic_vector_to_bin_string(inp : std_logic_vector)
|
1371 |
|
|
return string
|
1372 |
|
|
is
|
1373 |
|
|
variable vec : std_logic_vector(1 to inp'length);
|
1374 |
|
|
variable result : string(vec'range);
|
1375 |
|
|
begin
|
1376 |
|
|
vec := inp;
|
1377 |
|
|
for i in vec'range loop
|
1378 |
|
|
result(i) := to_char(vec(i));
|
1379 |
|
|
end loop;
|
1380 |
|
|
return result;
|
1381 |
|
|
end;
|
1382 |
|
|
function std_logic_to_bin_string(inp : std_logic)
|
1383 |
|
|
return string
|
1384 |
|
|
is
|
1385 |
|
|
variable result : string(1 to 3);
|
1386 |
|
|
begin
|
1387 |
|
|
result(1) := '0';
|
1388 |
|
|
result(2) := 'b';
|
1389 |
|
|
result(3) := to_char(inp);
|
1390 |
|
|
return result;
|
1391 |
|
|
end;
|
1392 |
|
|
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
|
1393 |
|
|
return string
|
1394 |
|
|
is
|
1395 |
|
|
variable width : integer := inp'length;
|
1396 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1397 |
|
|
variable str_pos : integer;
|
1398 |
|
|
variable result : string(1 to width+3);
|
1399 |
|
|
begin
|
1400 |
|
|
vec := inp;
|
1401 |
|
|
str_pos := 1;
|
1402 |
|
|
result(str_pos) := '0';
|
1403 |
|
|
str_pos := 2;
|
1404 |
|
|
result(str_pos) := 'b';
|
1405 |
|
|
str_pos := 3;
|
1406 |
|
|
for i in width-1 downto 0 loop
|
1407 |
|
|
if (((width+3) - bin_pt) = str_pos) then
|
1408 |
|
|
result(str_pos) := '.';
|
1409 |
|
|
str_pos := str_pos + 1;
|
1410 |
|
|
end if;
|
1411 |
|
|
result(str_pos) := to_char(vec(i));
|
1412 |
|
|
str_pos := str_pos + 1;
|
1413 |
|
|
end loop;
|
1414 |
|
|
if (bin_pt = 0) then
|
1415 |
|
|
result(str_pos) := '.';
|
1416 |
|
|
end if;
|
1417 |
|
|
return result;
|
1418 |
|
|
end;
|
1419 |
|
|
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
|
1420 |
|
|
return string
|
1421 |
|
|
is
|
1422 |
|
|
variable result : string(1 to width);
|
1423 |
|
|
variable vec : std_logic_vector(width-1 downto 0);
|
1424 |
|
|
begin
|
1425 |
|
|
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
|
1426 |
|
|
result := std_logic_vector_to_bin_string(vec);
|
1427 |
|
|
return result;
|
1428 |
|
|
end;
|
1429 |
|
|
function real_to_string (inp : real) return string
|
1430 |
|
|
is
|
1431 |
|
|
variable result : string(1 to display_precision) := (others => ' ');
|
1432 |
|
|
begin
|
1433 |
|
|
result(real'image(inp)'range) := real'image(inp);
|
1434 |
|
|
return result;
|
1435 |
|
|
end;
|
1436 |
|
|
-- synopsys translate_on
|
1437 |
|
|
end conv_pkg;
|
1438 |
|
|
|
1439 |
|
|
-------------------------------------------------------------------
|
1440 |
|
|
-- System Generator version 13.2 VHDL source file.
|
1441 |
|
|
--
|
1442 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
1443 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
1444 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
1445 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
1446 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
1447 |
|
|
-- this text/file solely for design, simulation, implementation and
|
1448 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
1449 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
1450 |
|
|
-- and immediately terminates your license unless covered by a separate
|
1451 |
|
|
-- agreement.
|
1452 |
|
|
--
|
1453 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
1454 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
1455 |
|
|
-- providing this design, code, or information as one possible
|
1456 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
1457 |
|
|
-- making no representation that this implementation is free from any
|
1458 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
1459 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
1460 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
1461 |
|
|
-- implementation, including but not limited to warranties of
|
1462 |
|
|
-- merchantability or fitness for a particular purpose.
|
1463 |
|
|
--
|
1464 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
1465 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
1466 |
|
|
--
|
1467 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
1468 |
|
|
-- sole risk and will be unsupported.
|
1469 |
|
|
--
|
1470 |
|
|
-- This copyright and support notice must be retained as part of this
|
1471 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
1472 |
|
|
-- reserved.
|
1473 |
|
|
-------------------------------------------------------------------
|
1474 |
|
|
-- synopsys translate_off
|
1475 |
|
|
library unisim;
|
1476 |
|
|
use unisim.vcomponents.all;
|
1477 |
|
|
-- synopsys translate_on
|
1478 |
|
|
library IEEE;
|
1479 |
|
|
use IEEE.std_logic_1164.all;
|
1480 |
|
|
use work.conv_pkg.all;
|
1481 |
|
|
entity srl17e is
|
1482 |
|
|
generic (width : integer:=16;
|
1483 |
|
|
latency : integer :=8);
|
1484 |
|
|
port (clk : in std_logic;
|
1485 |
|
|
ce : in std_logic;
|
1486 |
|
|
d : in std_logic_vector(width-1 downto 0);
|
1487 |
|
|
q : out std_logic_vector(width-1 downto 0));
|
1488 |
|
|
end srl17e;
|
1489 |
|
|
architecture structural of srl17e is
|
1490 |
|
|
component SRL16E
|
1491 |
|
|
port (D : in STD_ULOGIC;
|
1492 |
|
|
CE : in STD_ULOGIC;
|
1493 |
|
|
CLK : in STD_ULOGIC;
|
1494 |
|
|
A0 : in STD_ULOGIC;
|
1495 |
|
|
A1 : in STD_ULOGIC;
|
1496 |
|
|
A2 : in STD_ULOGIC;
|
1497 |
|
|
A3 : in STD_ULOGIC;
|
1498 |
|
|
Q : out STD_ULOGIC);
|
1499 |
|
|
end component;
|
1500 |
|
|
attribute syn_black_box of SRL16E : component is true;
|
1501 |
|
|
attribute fpga_dont_touch of SRL16E : component is "true";
|
1502 |
|
|
component FDE
|
1503 |
|
|
port(
|
1504 |
|
|
Q : out STD_ULOGIC;
|
1505 |
|
|
D : in STD_ULOGIC;
|
1506 |
|
|
C : in STD_ULOGIC;
|
1507 |
|
|
CE : in STD_ULOGIC);
|
1508 |
|
|
end component;
|
1509 |
|
|
attribute syn_black_box of FDE : component is true;
|
1510 |
|
|
attribute fpga_dont_touch of FDE : component is "true";
|
1511 |
|
|
constant a : std_logic_vector(4 downto 0) :=
|
1512 |
|
|
integer_to_std_logic_vector(latency-2,5,xlSigned);
|
1513 |
|
|
signal d_delayed : std_logic_vector(width-1 downto 0);
|
1514 |
|
|
signal srl16_out : std_logic_vector(width-1 downto 0);
|
1515 |
|
|
begin
|
1516 |
|
|
d_delayed <= d after 200 ps;
|
1517 |
|
|
reg_array : for i in 0 to width-1 generate
|
1518 |
|
|
srl16_used: if latency > 1 generate
|
1519 |
|
|
u1 : srl16e port map(clk => clk,
|
1520 |
|
|
d => d_delayed(i),
|
1521 |
|
|
q => srl16_out(i),
|
1522 |
|
|
ce => ce,
|
1523 |
|
|
a0 => a(0),
|
1524 |
|
|
a1 => a(1),
|
1525 |
|
|
a2 => a(2),
|
1526 |
|
|
a3 => a(3));
|
1527 |
|
|
end generate;
|
1528 |
|
|
srl16_not_used: if latency <= 1 generate
|
1529 |
|
|
srl16_out(i) <= d_delayed(i);
|
1530 |
|
|
end generate;
|
1531 |
|
|
fde_used: if latency /= 0 generate
|
1532 |
|
|
u2 : fde port map(c => clk,
|
1533 |
|
|
d => srl16_out(i),
|
1534 |
|
|
q => q(i),
|
1535 |
|
|
ce => ce);
|
1536 |
|
|
end generate;
|
1537 |
|
|
fde_not_used: if latency = 0 generate
|
1538 |
|
|
q(i) <= srl16_out(i);
|
1539 |
|
|
end generate;
|
1540 |
|
|
end generate;
|
1541 |
|
|
end structural;
|
1542 |
|
|
library IEEE;
|
1543 |
|
|
use IEEE.std_logic_1164.all;
|
1544 |
|
|
use work.conv_pkg.all;
|
1545 |
|
|
entity synth_reg is
|
1546 |
|
|
generic (width : integer := 8;
|
1547 |
|
|
latency : integer := 1);
|
1548 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
1549 |
|
|
ce : in std_logic;
|
1550 |
|
|
clr : in std_logic;
|
1551 |
|
|
clk : in std_logic;
|
1552 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
1553 |
|
|
end synth_reg;
|
1554 |
|
|
architecture structural of synth_reg is
|
1555 |
|
|
component srl17e
|
1556 |
|
|
generic (width : integer:=16;
|
1557 |
|
|
latency : integer :=8);
|
1558 |
|
|
port (clk : in std_logic;
|
1559 |
|
|
ce : in std_logic;
|
1560 |
|
|
d : in std_logic_vector(width-1 downto 0);
|
1561 |
|
|
q : out std_logic_vector(width-1 downto 0));
|
1562 |
|
|
end component;
|
1563 |
|
|
function calc_num_srl17es (latency : integer)
|
1564 |
|
|
return integer
|
1565 |
|
|
is
|
1566 |
|
|
variable remaining_latency : integer;
|
1567 |
|
|
variable result : integer;
|
1568 |
|
|
begin
|
1569 |
|
|
result := latency / 17;
|
1570 |
|
|
remaining_latency := latency - (result * 17);
|
1571 |
|
|
if (remaining_latency /= 0) then
|
1572 |
|
|
result := result + 1;
|
1573 |
|
|
end if;
|
1574 |
|
|
return result;
|
1575 |
|
|
end;
|
1576 |
|
|
constant complete_num_srl17es : integer := latency / 17;
|
1577 |
|
|
constant num_srl17es : integer := calc_num_srl17es(latency);
|
1578 |
|
|
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
|
1579 |
|
|
type register_array is array (num_srl17es downto 0) of
|
1580 |
|
|
std_logic_vector(width-1 downto 0);
|
1581 |
|
|
signal z : register_array;
|
1582 |
|
|
begin
|
1583 |
|
|
z(0) <= i;
|
1584 |
|
|
complete_ones : if complete_num_srl17es > 0 generate
|
1585 |
|
|
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
|
1586 |
|
|
delay_comp : srl17e
|
1587 |
|
|
generic map (width => width,
|
1588 |
|
|
latency => 17)
|
1589 |
|
|
port map (clk => clk,
|
1590 |
|
|
ce => ce,
|
1591 |
|
|
d => z(i),
|
1592 |
|
|
q => z(i+1));
|
1593 |
|
|
end generate;
|
1594 |
|
|
end generate;
|
1595 |
|
|
partial_one : if remaining_latency > 0 generate
|
1596 |
|
|
last_srl17e : srl17e
|
1597 |
|
|
generic map (width => width,
|
1598 |
|
|
latency => remaining_latency)
|
1599 |
|
|
port map (clk => clk,
|
1600 |
|
|
ce => ce,
|
1601 |
|
|
d => z(num_srl17es-1),
|
1602 |
|
|
q => z(num_srl17es));
|
1603 |
|
|
end generate;
|
1604 |
|
|
o <= z(num_srl17es);
|
1605 |
|
|
end structural;
|
1606 |
|
|
library IEEE;
|
1607 |
|
|
use IEEE.std_logic_1164.all;
|
1608 |
|
|
use work.conv_pkg.all;
|
1609 |
|
|
entity synth_reg_reg is
|
1610 |
|
|
generic (width : integer := 8;
|
1611 |
|
|
latency : integer := 1);
|
1612 |
|
|
port (i : in std_logic_vector(width-1 downto 0);
|
1613 |
|
|
ce : in std_logic;
|
1614 |
|
|
clr : in std_logic;
|
1615 |
|
|
clk : in std_logic;
|
1616 |
|
|
o : out std_logic_vector(width-1 downto 0));
|
1617 |
|
|
end synth_reg_reg;
|
1618 |
|
|
architecture behav of synth_reg_reg is
|
1619 |
|
|
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
|
1620 |
|
|
signal reg_bank : reg_array_type := (others => (others => '0'));
|
1621 |
|
|
signal reg_bank_in : reg_array_type := (others => (others => '0'));
|
1622 |
|
|
attribute syn_allow_retiming : boolean;
|
1623 |
|
|
attribute syn_srlstyle : string;
|
1624 |
|
|
attribute syn_allow_retiming of reg_bank : signal is true;
|
1625 |
|
|
attribute syn_allow_retiming of reg_bank_in : signal is true;
|
1626 |
|
|
attribute syn_srlstyle of reg_bank : signal is "registers";
|
1627 |
|
|
attribute syn_srlstyle of reg_bank_in : signal is "registers";
|
1628 |
|
|
begin
|
1629 |
|
|
latency_eq_0: if latency = 0 generate
|
1630 |
|
|
o <= i;
|
1631 |
|
|
end generate latency_eq_0;
|
1632 |
|
|
latency_gt_0: if latency >= 1 generate
|
1633 |
|
|
o <= reg_bank(latency-1);
|
1634 |
|
|
reg_bank_in(0) <= i;
|
1635 |
|
|
loop_gen: for idx in latency-2 downto 0 generate
|
1636 |
|
|
reg_bank_in(idx+1) <= reg_bank(idx);
|
1637 |
|
|
end generate loop_gen;
|
1638 |
|
|
sync_loop: for sync_idx in latency-1 downto 0 generate
|
1639 |
|
|
sync_proc: process (clk)
|
1640 |
|
|
begin
|
1641 |
|
|
if clk'event and clk = '1' then
|
1642 |
|
|
if clr = '1' then
|
1643 |
|
|
reg_bank_in <= (others => (others => '0'));
|
1644 |
|
|
elsif ce = '1' then
|
1645 |
|
|
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
|
1646 |
|
|
end if;
|
1647 |
|
|
end if;
|
1648 |
|
|
end process sync_proc;
|
1649 |
|
|
end generate sync_loop;
|
1650 |
|
|
end generate latency_gt_0;
|
1651 |
|
|
end behav;
|
1652 |
|
|
|
1653 |
|
|
-------------------------------------------------------------------
|
1654 |
|
|
-- System Generator version 13.2 VHDL source file.
|
1655 |
|
|
--
|
1656 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
1657 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
1658 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
1659 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
1660 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
1661 |
|
|
-- this text/file solely for design, simulation, implementation and
|
1662 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
1663 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
1664 |
|
|
-- and immediately terminates your license unless covered by a separate
|
1665 |
|
|
-- agreement.
|
1666 |
|
|
--
|
1667 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
1668 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
1669 |
|
|
-- providing this design, code, or information as one possible
|
1670 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
1671 |
|
|
-- making no representation that this implementation is free from any
|
1672 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
1673 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
1674 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
1675 |
|
|
-- implementation, including but not limited to warranties of
|
1676 |
|
|
-- merchantability or fitness for a particular purpose.
|
1677 |
|
|
--
|
1678 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
1679 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
1680 |
|
|
--
|
1681 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
1682 |
|
|
-- sole risk and will be unsupported.
|
1683 |
|
|
--
|
1684 |
|
|
-- This copyright and support notice must be retained as part of this
|
1685 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
1686 |
|
|
-- reserved.
|
1687 |
|
|
-------------------------------------------------------------------
|
1688 |
|
|
-- synopsys translate_off
|
1689 |
|
|
library unisim;
|
1690 |
|
|
use unisim.vcomponents.all;
|
1691 |
|
|
-- synopsys translate_on
|
1692 |
|
|
library IEEE;
|
1693 |
|
|
use IEEE.std_logic_1164.all;
|
1694 |
|
|
use work.conv_pkg.all;
|
1695 |
|
|
entity single_reg_w_init is
|
1696 |
|
|
generic (
|
1697 |
|
|
width: integer := 8;
|
1698 |
|
|
init_index: integer := 0;
|
1699 |
|
|
init_value: bit_vector := b"0000"
|
1700 |
|
|
);
|
1701 |
|
|
port (
|
1702 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1703 |
|
|
ce: in std_logic;
|
1704 |
|
|
clr: in std_logic;
|
1705 |
|
|
clk: in std_logic;
|
1706 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1707 |
|
|
);
|
1708 |
|
|
end single_reg_w_init;
|
1709 |
|
|
architecture structural of single_reg_w_init is
|
1710 |
|
|
function build_init_const(width: integer;
|
1711 |
|
|
init_index: integer;
|
1712 |
|
|
init_value: bit_vector)
|
1713 |
|
|
return std_logic_vector
|
1714 |
|
|
is
|
1715 |
|
|
variable result: std_logic_vector(width - 1 downto 0);
|
1716 |
|
|
begin
|
1717 |
|
|
if init_index = 0 then
|
1718 |
|
|
result := (others => '0');
|
1719 |
|
|
elsif init_index = 1 then
|
1720 |
|
|
result := (others => '0');
|
1721 |
|
|
result(0) := '1';
|
1722 |
|
|
else
|
1723 |
|
|
result := to_stdlogicvector(init_value);
|
1724 |
|
|
end if;
|
1725 |
|
|
return result;
|
1726 |
|
|
end;
|
1727 |
|
|
component fdre
|
1728 |
|
|
port (
|
1729 |
|
|
q: out std_ulogic;
|
1730 |
|
|
d: in std_ulogic;
|
1731 |
|
|
c: in std_ulogic;
|
1732 |
|
|
ce: in std_ulogic;
|
1733 |
|
|
r: in std_ulogic
|
1734 |
|
|
);
|
1735 |
|
|
end component;
|
1736 |
|
|
attribute syn_black_box of fdre: component is true;
|
1737 |
|
|
attribute fpga_dont_touch of fdre: component is "true";
|
1738 |
|
|
component fdse
|
1739 |
|
|
port (
|
1740 |
|
|
q: out std_ulogic;
|
1741 |
|
|
d: in std_ulogic;
|
1742 |
|
|
c: in std_ulogic;
|
1743 |
|
|
ce: in std_ulogic;
|
1744 |
|
|
s: in std_ulogic
|
1745 |
|
|
);
|
1746 |
|
|
end component;
|
1747 |
|
|
attribute syn_black_box of fdse: component is true;
|
1748 |
|
|
attribute fpga_dont_touch of fdse: component is "true";
|
1749 |
|
|
constant init_const: std_logic_vector(width - 1 downto 0)
|
1750 |
|
|
:= build_init_const(width, init_index, init_value);
|
1751 |
|
|
begin
|
1752 |
|
|
fd_prim_array: for index in 0 to width - 1 generate
|
1753 |
|
|
bit_is_0: if (init_const(index) = '0') generate
|
1754 |
|
|
fdre_comp: fdre
|
1755 |
|
|
port map (
|
1756 |
|
|
c => clk,
|
1757 |
|
|
d => i(index),
|
1758 |
|
|
q => o(index),
|
1759 |
|
|
ce => ce,
|
1760 |
|
|
r => clr
|
1761 |
|
|
);
|
1762 |
|
|
end generate;
|
1763 |
|
|
bit_is_1: if (init_const(index) = '1') generate
|
1764 |
|
|
fdse_comp: fdse
|
1765 |
|
|
port map (
|
1766 |
|
|
c => clk,
|
1767 |
|
|
d => i(index),
|
1768 |
|
|
q => o(index),
|
1769 |
|
|
ce => ce,
|
1770 |
|
|
s => clr
|
1771 |
|
|
);
|
1772 |
|
|
end generate;
|
1773 |
|
|
end generate;
|
1774 |
|
|
end architecture structural;
|
1775 |
|
|
-- synopsys translate_off
|
1776 |
|
|
library unisim;
|
1777 |
|
|
use unisim.vcomponents.all;
|
1778 |
|
|
-- synopsys translate_on
|
1779 |
|
|
library IEEE;
|
1780 |
|
|
use IEEE.std_logic_1164.all;
|
1781 |
|
|
use work.conv_pkg.all;
|
1782 |
|
|
entity synth_reg_w_init is
|
1783 |
|
|
generic (
|
1784 |
|
|
width: integer := 8;
|
1785 |
|
|
init_index: integer := 0;
|
1786 |
|
|
init_value: bit_vector := b"0000";
|
1787 |
|
|
latency: integer := 1
|
1788 |
|
|
);
|
1789 |
|
|
port (
|
1790 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1791 |
|
|
ce: in std_logic;
|
1792 |
|
|
clr: in std_logic;
|
1793 |
|
|
clk: in std_logic;
|
1794 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1795 |
|
|
);
|
1796 |
|
|
end synth_reg_w_init;
|
1797 |
|
|
architecture structural of synth_reg_w_init is
|
1798 |
|
|
component single_reg_w_init
|
1799 |
|
|
generic (
|
1800 |
|
|
width: integer := 8;
|
1801 |
|
|
init_index: integer := 0;
|
1802 |
|
|
init_value: bit_vector := b"0000"
|
1803 |
|
|
);
|
1804 |
|
|
port (
|
1805 |
|
|
i: in std_logic_vector(width - 1 downto 0);
|
1806 |
|
|
ce: in std_logic;
|
1807 |
|
|
clr: in std_logic;
|
1808 |
|
|
clk: in std_logic;
|
1809 |
|
|
o: out std_logic_vector(width - 1 downto 0)
|
1810 |
|
|
);
|
1811 |
|
|
end component;
|
1812 |
|
|
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
|
1813 |
|
|
signal dly_clr: std_logic;
|
1814 |
|
|
begin
|
1815 |
|
|
latency_eq_0: if (latency = 0) generate
|
1816 |
|
|
o <= i;
|
1817 |
|
|
end generate;
|
1818 |
|
|
latency_gt_0: if (latency >= 1) generate
|
1819 |
|
|
dly_i((latency + 1) * width - 1 downto latency * width) <= i
|
1820 |
|
|
after 200 ps;
|
1821 |
|
|
dly_clr <= clr after 200 ps;
|
1822 |
|
|
fd_array: for index in latency downto 1 generate
|
1823 |
|
|
reg_comp: single_reg_w_init
|
1824 |
|
|
generic map (
|
1825 |
|
|
width => width,
|
1826 |
|
|
init_index => init_index,
|
1827 |
|
|
init_value => init_value
|
1828 |
|
|
)
|
1829 |
|
|
port map (
|
1830 |
|
|
clk => clk,
|
1831 |
|
|
i => dly_i((index + 1) * width - 1 downto index * width),
|
1832 |
|
|
o => dly_i(index * width - 1 downto (index - 1) * width),
|
1833 |
|
|
ce => ce,
|
1834 |
|
|
clr => dly_clr
|
1835 |
|
|
);
|
1836 |
|
|
end generate;
|
1837 |
|
|
o <= dly_i(width - 1 downto 0);
|
1838 |
|
|
end generate;
|
1839 |
|
|
end structural;
|
1840 |
|
|
library IEEE;
|
1841 |
|
|
use IEEE.std_logic_1164.all;
|
1842 |
|
|
use IEEE.numeric_std.all;
|
1843 |
|
|
use work.conv_pkg.all;
|
1844 |
|
|
|
1845 |
|
|
entity constant_6293007044 is
|
1846 |
|
|
port (
|
1847 |
|
|
op : out std_logic_vector((1 - 1) downto 0);
|
1848 |
|
|
clk : in std_logic;
|
1849 |
|
|
ce : in std_logic;
|
1850 |
|
|
clr : in std_logic);
|
1851 |
|
|
end constant_6293007044;
|
1852 |
|
|
|
1853 |
|
|
|
1854 |
|
|
architecture behavior of constant_6293007044 is
|
1855 |
|
|
begin
|
1856 |
|
|
op <= "1";
|
1857 |
|
|
end behavior;
|
1858 |
|
|
|
1859 |
|
|
library IEEE;
|
1860 |
|
|
use IEEE.std_logic_1164.all;
|
1861 |
|
|
use work.conv_pkg.all;
|
1862 |
|
|
|
1863 |
|
|
-- Generated from Simulink block "INOUT_LOGIC"
|
1864 |
|
|
|
1865 |
|
|
entity inout_logic is
|
1866 |
|
|
port (
|
1867 |
|
|
data_out: in std_logic;
|
1868 |
|
|
data_out_x0: in std_logic_vector(31 downto 0);
|
1869 |
|
|
data_out_x1: in std_logic_vector(31 downto 0);
|
1870 |
|
|
data_out_x10: in std_logic;
|
1871 |
|
|
data_out_x11: in std_logic;
|
1872 |
|
|
data_out_x12: in std_logic_vector(31 downto 0);
|
1873 |
|
|
data_out_x13: in std_logic;
|
1874 |
|
|
data_out_x14: in std_logic_vector(31 downto 0);
|
1875 |
|
|
data_out_x15: in std_logic;
|
1876 |
|
|
data_out_x16: in std_logic_vector(31 downto 0);
|
1877 |
|
|
data_out_x17: in std_logic;
|
1878 |
|
|
data_out_x18: in std_logic_vector(31 downto 0);
|
1879 |
|
|
data_out_x19: in std_logic;
|
1880 |
|
|
data_out_x2: in std_logic;
|
1881 |
|
|
data_out_x20: in std_logic_vector(31 downto 0);
|
1882 |
|
|
data_out_x21: in std_logic;
|
1883 |
|
|
data_out_x22: in std_logic_vector(31 downto 0);
|
1884 |
|
|
data_out_x23: in std_logic;
|
1885 |
|
|
data_out_x24: in std_logic_vector(31 downto 0);
|
1886 |
|
|
data_out_x25: in std_logic_vector(31 downto 0);
|
1887 |
|
|
data_out_x26: in std_logic;
|
1888 |
|
|
data_out_x3: in std_logic_vector(31 downto 0);
|
1889 |
|
|
data_out_x4: in std_logic;
|
1890 |
|
|
data_out_x5: in std_logic_vector(31 downto 0);
|
1891 |
|
|
data_out_x6: in std_logic;
|
1892 |
|
|
data_out_x7: in std_logic_vector(31 downto 0);
|
1893 |
|
|
data_out_x8: in std_logic;
|
1894 |
|
|
data_out_x9: in std_logic_vector(31 downto 0);
|
1895 |
|
|
debug_in_1i: in std_logic_vector(31 downto 0);
|
1896 |
|
|
debug_in_2i: in std_logic_vector(31 downto 0);
|
1897 |
|
|
debug_in_3i: in std_logic_vector(31 downto 0);
|
1898 |
|
|
debug_in_4i: in std_logic_vector(31 downto 0);
|
1899 |
|
|
dma_host2board_busy: in std_logic;
|
1900 |
|
|
dma_host2board_done: in std_logic;
|
1901 |
|
|
reg01_td: in std_logic_vector(31 downto 0);
|
1902 |
|
|
reg01_tv: in std_logic;
|
1903 |
|
|
reg02_td: in std_logic_vector(31 downto 0);
|
1904 |
|
|
reg02_tv: in std_logic;
|
1905 |
|
|
reg03_td: in std_logic_vector(31 downto 0);
|
1906 |
|
|
reg03_tv: in std_logic;
|
1907 |
|
|
reg04_td: in std_logic_vector(31 downto 0);
|
1908 |
|
|
reg04_tv: in std_logic;
|
1909 |
|
|
reg05_td: in std_logic_vector(31 downto 0);
|
1910 |
|
|
reg05_tv: in std_logic;
|
1911 |
|
|
reg06_td: in std_logic_vector(31 downto 0);
|
1912 |
|
|
reg06_tv: in std_logic;
|
1913 |
|
|
reg07_td: in std_logic_vector(31 downto 0);
|
1914 |
|
|
reg07_tv: in std_logic;
|
1915 |
|
|
reg08_td: in std_logic_vector(31 downto 0);
|
1916 |
|
|
reg08_tv: in std_logic;
|
1917 |
|
|
reg09_td: in std_logic_vector(31 downto 0);
|
1918 |
|
|
reg09_tv: in std_logic;
|
1919 |
|
|
reg10_td: in std_logic_vector(31 downto 0);
|
1920 |
|
|
reg10_tv: in std_logic;
|
1921 |
|
|
reg11_td: in std_logic_vector(31 downto 0);
|
1922 |
|
|
reg11_tv: in std_logic;
|
1923 |
|
|
reg12_td: in std_logic_vector(31 downto 0);
|
1924 |
|
|
reg12_tv: in std_logic;
|
1925 |
|
|
reg13_td: in std_logic_vector(31 downto 0);
|
1926 |
|
|
reg13_tv: in std_logic;
|
1927 |
|
|
reg14_td: in std_logic_vector(31 downto 0);
|
1928 |
|
|
reg14_tv: in std_logic;
|
1929 |
|
|
data_in: out std_logic_vector(31 downto 0);
|
1930 |
|
|
data_in_x0: out std_logic;
|
1931 |
|
|
data_in_x1: out std_logic_vector(31 downto 0);
|
1932 |
|
|
data_in_x10: out std_logic_vector(31 downto 0);
|
1933 |
|
|
data_in_x11: out std_logic_vector(31 downto 0);
|
1934 |
|
|
data_in_x12: out std_logic;
|
1935 |
|
|
data_in_x13: out std_logic_vector(31 downto 0);
|
1936 |
|
|
data_in_x14: out std_logic;
|
1937 |
|
|
data_in_x15: out std_logic_vector(31 downto 0);
|
1938 |
|
|
data_in_x16: out std_logic;
|
1939 |
|
|
data_in_x17: out std_logic_vector(31 downto 0);
|
1940 |
|
|
data_in_x18: out std_logic;
|
1941 |
|
|
data_in_x19: out std_logic_vector(31 downto 0);
|
1942 |
|
|
data_in_x2: out std_logic;
|
1943 |
|
|
data_in_x20: out std_logic;
|
1944 |
|
|
data_in_x21: out std_logic;
|
1945 |
|
|
data_in_x22: out std_logic_vector(31 downto 0);
|
1946 |
|
|
data_in_x23: out std_logic;
|
1947 |
|
|
data_in_x24: out std_logic_vector(31 downto 0);
|
1948 |
|
|
data_in_x25: out std_logic;
|
1949 |
|
|
data_in_x26: out std_logic_vector(31 downto 0);
|
1950 |
|
|
data_in_x27: out std_logic;
|
1951 |
|
|
data_in_x28: out std_logic_vector(31 downto 0);
|
1952 |
|
|
data_in_x29: out std_logic_vector(31 downto 0);
|
1953 |
|
|
data_in_x3: out std_logic_vector(31 downto 0);
|
1954 |
|
|
data_in_x30: out std_logic_vector(31 downto 0);
|
1955 |
|
|
data_in_x31: out std_logic;
|
1956 |
|
|
data_in_x32: out std_logic_vector(31 downto 0);
|
1957 |
|
|
data_in_x4: out std_logic;
|
1958 |
|
|
data_in_x5: out std_logic_vector(31 downto 0);
|
1959 |
|
|
data_in_x6: out std_logic;
|
1960 |
|
|
data_in_x7: out std_logic_vector(31 downto 0);
|
1961 |
|
|
data_in_x8: out std_logic;
|
1962 |
|
|
data_in_x9: out std_logic;
|
1963 |
|
|
en: out std_logic;
|
1964 |
|
|
en_x0: out std_logic;
|
1965 |
|
|
en_x1: out std_logic;
|
1966 |
|
|
en_x10: out std_logic;
|
1967 |
|
|
en_x11: out std_logic;
|
1968 |
|
|
en_x12: out std_logic;
|
1969 |
|
|
en_x13: out std_logic;
|
1970 |
|
|
en_x14: out std_logic;
|
1971 |
|
|
en_x15: out std_logic;
|
1972 |
|
|
en_x16: out std_logic;
|
1973 |
|
|
en_x17: out std_logic;
|
1974 |
|
|
en_x18: out std_logic;
|
1975 |
|
|
en_x19: out std_logic;
|
1976 |
|
|
en_x2: out std_logic;
|
1977 |
|
|
en_x20: out std_logic;
|
1978 |
|
|
en_x21: out std_logic;
|
1979 |
|
|
en_x22: out std_logic;
|
1980 |
|
|
en_x23: out std_logic;
|
1981 |
|
|
en_x24: out std_logic;
|
1982 |
|
|
en_x25: out std_logic;
|
1983 |
|
|
en_x26: out std_logic;
|
1984 |
|
|
en_x27: out std_logic;
|
1985 |
|
|
en_x28: out std_logic;
|
1986 |
|
|
en_x29: out std_logic;
|
1987 |
|
|
en_x3: out std_logic;
|
1988 |
|
|
en_x30: out std_logic;
|
1989 |
|
|
en_x31: out std_logic;
|
1990 |
|
|
en_x32: out std_logic;
|
1991 |
|
|
en_x4: out std_logic;
|
1992 |
|
|
en_x5: out std_logic;
|
1993 |
|
|
en_x6: out std_logic;
|
1994 |
|
|
en_x7: out std_logic;
|
1995 |
|
|
en_x8: out std_logic;
|
1996 |
|
|
en_x9: out std_logic;
|
1997 |
|
|
reg01_rd: out std_logic_vector(31 downto 0);
|
1998 |
|
|
reg01_rv: out std_logic;
|
1999 |
|
|
reg02_rd: out std_logic_vector(31 downto 0);
|
2000 |
|
|
reg02_rv: out std_logic;
|
2001 |
|
|
reg03_rd: out std_logic_vector(31 downto 0);
|
2002 |
|
|
reg03_rv: out std_logic;
|
2003 |
|
|
reg04_rd: out std_logic_vector(31 downto 0);
|
2004 |
|
|
reg04_rv: out std_logic;
|
2005 |
|
|
reg05_rd: out std_logic_vector(31 downto 0);
|
2006 |
|
|
reg05_rv: out std_logic;
|
2007 |
|
|
reg06_rd: out std_logic_vector(31 downto 0);
|
2008 |
|
|
reg06_rv: out std_logic;
|
2009 |
|
|
reg07_rd: out std_logic_vector(31 downto 0);
|
2010 |
|
|
reg07_rv: out std_logic;
|
2011 |
|
|
reg08_rd: out std_logic_vector(31 downto 0);
|
2012 |
|
|
reg08_rv: out std_logic;
|
2013 |
|
|
reg09_rd: out std_logic_vector(31 downto 0);
|
2014 |
|
|
reg09_rv: out std_logic;
|
2015 |
|
|
reg10_rd: out std_logic_vector(31 downto 0);
|
2016 |
|
|
reg10_rv: out std_logic;
|
2017 |
|
|
reg11_rd: out std_logic_vector(31 downto 0);
|
2018 |
|
|
reg11_rv: out std_logic;
|
2019 |
|
|
reg12_rd: out std_logic_vector(31 downto 0);
|
2020 |
|
|
reg12_rv: out std_logic;
|
2021 |
|
|
reg13_rd: out std_logic_vector(31 downto 0);
|
2022 |
|
|
reg13_rv: out std_logic;
|
2023 |
|
|
reg14_rd: out std_logic_vector(31 downto 0);
|
2024 |
|
|
reg14_rv: out std_logic
|
2025 |
|
|
);
|
2026 |
|
|
end inout_logic;
|
2027 |
|
|
|
2028 |
|
|
architecture structural of inout_logic is
|
2029 |
|
|
attribute core_generation_info: string;
|
2030 |
|
|
attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=351,xilinx_chipscope_block=1,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=89,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}";
|
2031 |
|
|
|
2032 |
|
|
signal constant1_op_net_x0: std_logic;
|
2033 |
|
|
signal constant5_op_net_x0: std_logic;
|
2034 |
|
|
signal debug_in_1i_net: std_logic_vector(31 downto 0);
|
2035 |
|
|
signal debug_in_2i_net: std_logic_vector(31 downto 0);
|
2036 |
|
|
signal debug_in_3i_net: std_logic_vector(31 downto 0);
|
2037 |
|
|
signal debug_in_4i_net: std_logic_vector(31 downto 0);
|
2038 |
|
|
signal dma_host2board_busy_net: std_logic;
|
2039 |
|
|
signal dma_host2board_done_net: std_logic;
|
2040 |
|
|
signal from_register10_data_out_net: std_logic_vector(31 downto 0);
|
2041 |
|
|
signal from_register11_data_out_net: std_logic_vector(31 downto 0);
|
2042 |
|
|
signal from_register12_data_out_net: std_logic;
|
2043 |
|
|
signal from_register13_data_out_net: std_logic_vector(31 downto 0);
|
2044 |
|
|
signal from_register14_data_out_net: std_logic;
|
2045 |
|
|
signal from_register15_data_out_net: std_logic_vector(31 downto 0);
|
2046 |
|
|
signal from_register16_data_out_net: std_logic;
|
2047 |
|
|
signal from_register17_data_out_net: std_logic_vector(31 downto 0);
|
2048 |
|
|
signal from_register18_data_out_net: std_logic;
|
2049 |
|
|
signal from_register19_data_out_net: std_logic_vector(31 downto 0);
|
2050 |
|
|
signal from_register1_data_out_net: std_logic;
|
2051 |
|
|
signal from_register20_data_out_net: std_logic;
|
2052 |
|
|
signal from_register21_data_out_net: std_logic_vector(31 downto 0);
|
2053 |
|
|
signal from_register22_data_out_net: std_logic;
|
2054 |
|
|
signal from_register23_data_out_net: std_logic_vector(31 downto 0);
|
2055 |
|
|
signal from_register24_data_out_net: std_logic;
|
2056 |
|
|
signal from_register25_data_out_net: std_logic_vector(31 downto 0);
|
2057 |
|
|
signal from_register26_data_out_net: std_logic;
|
2058 |
|
|
signal from_register27_data_out_net: std_logic_vector(31 downto 0);
|
2059 |
|
|
signal from_register28_data_out_net: std_logic;
|
2060 |
|
|
signal from_register2_data_out_net: std_logic;
|
2061 |
|
|
signal from_register3_data_out_net: std_logic_vector(31 downto 0);
|
2062 |
|
|
signal from_register4_data_out_net: std_logic;
|
2063 |
|
|
signal from_register5_data_out_net: std_logic_vector(31 downto 0);
|
2064 |
|
|
signal from_register6_data_out_net: std_logic;
|
2065 |
|
|
signal from_register7_data_out_net: std_logic_vector(31 downto 0);
|
2066 |
|
|
signal from_register8_data_out_net: std_logic_vector(31 downto 0);
|
2067 |
|
|
signal from_register9_data_out_net: std_logic;
|
2068 |
|
|
signal reg01_td_net: std_logic_vector(31 downto 0);
|
2069 |
|
|
signal reg01_tv_net: std_logic;
|
2070 |
|
|
signal reg02_td_net: std_logic_vector(31 downto 0);
|
2071 |
|
|
signal reg02_tv_net: std_logic;
|
2072 |
|
|
signal reg03_td_net: std_logic_vector(31 downto 0);
|
2073 |
|
|
signal reg03_tv_net: std_logic;
|
2074 |
|
|
signal reg04_td_net: std_logic_vector(31 downto 0);
|
2075 |
|
|
signal reg04_tv_net: std_logic;
|
2076 |
|
|
signal reg05_td_net: std_logic_vector(31 downto 0);
|
2077 |
|
|
signal reg05_tv_net: std_logic;
|
2078 |
|
|
signal reg06_td_net: std_logic_vector(31 downto 0);
|
2079 |
|
|
signal reg06_tv_net: std_logic;
|
2080 |
|
|
signal reg07_td_net: std_logic_vector(31 downto 0);
|
2081 |
|
|
signal reg07_tv_net: std_logic;
|
2082 |
|
|
signal reg08_td_net: std_logic_vector(31 downto 0);
|
2083 |
|
|
signal reg08_tv_net: std_logic;
|
2084 |
|
|
signal reg09_td_net: std_logic_vector(31 downto 0);
|
2085 |
|
|
signal reg09_tv_net: std_logic;
|
2086 |
|
|
signal reg10_td_net: std_logic_vector(31 downto 0);
|
2087 |
|
|
signal reg10_tv_net: std_logic;
|
2088 |
|
|
signal reg11_td_net: std_logic_vector(31 downto 0);
|
2089 |
|
|
signal reg11_tv_net: std_logic;
|
2090 |
|
|
signal reg12_td_net: std_logic_vector(31 downto 0);
|
2091 |
|
|
signal reg12_tv_net: std_logic;
|
2092 |
|
|
signal reg13_td_net: std_logic_vector(31 downto 0);
|
2093 |
|
|
signal reg13_tv_net: std_logic;
|
2094 |
|
|
signal reg14_td_net: std_logic_vector(31 downto 0);
|
2095 |
|
|
signal reg14_tv_net: std_logic;
|
2096 |
|
|
|
2097 |
|
|
begin
|
2098 |
|
|
from_register1_data_out_net <= data_out;
|
2099 |
|
|
from_register10_data_out_net <= data_out_x0;
|
2100 |
|
|
from_register11_data_out_net <= data_out_x1;
|
2101 |
|
|
from_register2_data_out_net <= data_out_x10;
|
2102 |
|
|
from_register20_data_out_net <= data_out_x11;
|
2103 |
|
|
from_register21_data_out_net <= data_out_x12;
|
2104 |
|
|
from_register22_data_out_net <= data_out_x13;
|
2105 |
|
|
from_register23_data_out_net <= data_out_x14;
|
2106 |
|
|
from_register24_data_out_net <= data_out_x15;
|
2107 |
|
|
from_register25_data_out_net <= data_out_x16;
|
2108 |
|
|
from_register26_data_out_net <= data_out_x17;
|
2109 |
|
|
from_register27_data_out_net <= data_out_x18;
|
2110 |
|
|
from_register28_data_out_net <= data_out_x19;
|
2111 |
|
|
from_register12_data_out_net <= data_out_x2;
|
2112 |
|
|
from_register3_data_out_net <= data_out_x20;
|
2113 |
|
|
from_register4_data_out_net <= data_out_x21;
|
2114 |
|
|
from_register5_data_out_net <= data_out_x22;
|
2115 |
|
|
from_register6_data_out_net <= data_out_x23;
|
2116 |
|
|
from_register7_data_out_net <= data_out_x24;
|
2117 |
|
|
from_register8_data_out_net <= data_out_x25;
|
2118 |
|
|
from_register9_data_out_net <= data_out_x26;
|
2119 |
|
|
from_register13_data_out_net <= data_out_x3;
|
2120 |
|
|
from_register14_data_out_net <= data_out_x4;
|
2121 |
|
|
from_register15_data_out_net <= data_out_x5;
|
2122 |
|
|
from_register16_data_out_net <= data_out_x6;
|
2123 |
|
|
from_register17_data_out_net <= data_out_x7;
|
2124 |
|
|
from_register18_data_out_net <= data_out_x8;
|
2125 |
|
|
from_register19_data_out_net <= data_out_x9;
|
2126 |
|
|
debug_in_1i_net <= debug_in_1i;
|
2127 |
|
|
debug_in_2i_net <= debug_in_2i;
|
2128 |
|
|
debug_in_3i_net <= debug_in_3i;
|
2129 |
|
|
debug_in_4i_net <= debug_in_4i;
|
2130 |
|
|
dma_host2board_busy_net <= dma_host2board_busy;
|
2131 |
|
|
dma_host2board_done_net <= dma_host2board_done;
|
2132 |
|
|
reg01_td_net <= reg01_td;
|
2133 |
|
|
reg01_tv_net <= reg01_tv;
|
2134 |
|
|
reg02_td_net <= reg02_td;
|
2135 |
|
|
reg02_tv_net <= reg02_tv;
|
2136 |
|
|
reg03_td_net <= reg03_td;
|
2137 |
|
|
reg03_tv_net <= reg03_tv;
|
2138 |
|
|
reg04_td_net <= reg04_td;
|
2139 |
|
|
reg04_tv_net <= reg04_tv;
|
2140 |
|
|
reg05_td_net <= reg05_td;
|
2141 |
|
|
reg05_tv_net <= reg05_tv;
|
2142 |
|
|
reg06_td_net <= reg06_td;
|
2143 |
|
|
reg06_tv_net <= reg06_tv;
|
2144 |
|
|
reg07_td_net <= reg07_td;
|
2145 |
|
|
reg07_tv_net <= reg07_tv;
|
2146 |
|
|
reg08_td_net <= reg08_td;
|
2147 |
|
|
reg08_tv_net <= reg08_tv;
|
2148 |
|
|
reg09_td_net <= reg09_td;
|
2149 |
|
|
reg09_tv_net <= reg09_tv;
|
2150 |
|
|
reg10_td_net <= reg10_td;
|
2151 |
|
|
reg10_tv_net <= reg10_tv;
|
2152 |
|
|
reg11_td_net <= reg11_td;
|
2153 |
|
|
reg11_tv_net <= reg11_tv;
|
2154 |
|
|
reg12_td_net <= reg12_td;
|
2155 |
|
|
reg12_tv_net <= reg12_tv;
|
2156 |
|
|
reg13_td_net <= reg13_td;
|
2157 |
|
|
reg13_tv_net <= reg13_tv;
|
2158 |
|
|
reg14_td_net <= reg14_td;
|
2159 |
|
|
reg14_tv_net <= reg14_tv;
|
2160 |
|
|
data_in <= debug_in_2i_net;
|
2161 |
|
|
data_in_x0 <= reg04_tv_net;
|
2162 |
|
|
data_in_x1 <= reg04_td_net;
|
2163 |
|
|
data_in_x10 <= debug_in_3i_net;
|
2164 |
|
|
data_in_x11 <= debug_in_4i_net;
|
2165 |
|
|
data_in_x12 <= reg09_tv_net;
|
2166 |
|
|
data_in_x13 <= reg09_td_net;
|
2167 |
|
|
data_in_x14 <= reg10_tv_net;
|
2168 |
|
|
data_in_x15 <= reg10_td_net;
|
2169 |
|
|
data_in_x16 <= reg08_tv_net;
|
2170 |
|
|
data_in_x17 <= reg08_td_net;
|
2171 |
|
|
data_in_x18 <= reg11_tv_net;
|
2172 |
|
|
data_in_x19 <= reg11_td_net;
|
2173 |
|
|
data_in_x2 <= reg05_tv_net;
|
2174 |
|
|
data_in_x20 <= reg12_tv_net;
|
2175 |
|
|
data_in_x21 <= reg01_tv_net;
|
2176 |
|
|
data_in_x22 <= reg12_td_net;
|
2177 |
|
|
data_in_x23 <= reg13_tv_net;
|
2178 |
|
|
data_in_x24 <= reg13_td_net;
|
2179 |
|
|
data_in_x25 <= reg14_tv_net;
|
2180 |
|
|
data_in_x26 <= reg14_td_net;
|
2181 |
|
|
data_in_x27 <= reg02_tv_net;
|
2182 |
|
|
data_in_x28 <= reg02_td_net;
|
2183 |
|
|
data_in_x29 <= debug_in_1i_net;
|
2184 |
|
|
data_in_x3 <= reg05_td_net;
|
2185 |
|
|
data_in_x30 <= reg01_td_net;
|
2186 |
|
|
data_in_x31 <= reg03_tv_net;
|
2187 |
|
|
data_in_x32 <= reg03_td_net;
|
2188 |
|
|
data_in_x4 <= reg06_tv_net;
|
2189 |
|
|
data_in_x5 <= reg06_td_net;
|
2190 |
|
|
data_in_x6 <= reg07_tv_net;
|
2191 |
|
|
data_in_x7 <= reg07_td_net;
|
2192 |
|
|
data_in_x8 <= dma_host2board_busy_net;
|
2193 |
|
|
data_in_x9 <= dma_host2board_done_net;
|
2194 |
|
|
en <= constant5_op_net_x0;
|
2195 |
|
|
en_x0 <= constant5_op_net_x0;
|
2196 |
|
|
en_x1 <= constant5_op_net_x0;
|
2197 |
|
|
en_x10 <= constant5_op_net_x0;
|
2198 |
|
|
en_x11 <= constant5_op_net_x0;
|
2199 |
|
|
en_x12 <= constant1_op_net_x0;
|
2200 |
|
|
en_x13 <= constant1_op_net_x0;
|
2201 |
|
|
en_x14 <= constant1_op_net_x0;
|
2202 |
|
|
en_x15 <= constant1_op_net_x0;
|
2203 |
|
|
en_x16 <= constant1_op_net_x0;
|
2204 |
|
|
en_x17 <= constant1_op_net_x0;
|
2205 |
|
|
en_x18 <= constant1_op_net_x0;
|
2206 |
|
|
en_x19 <= constant1_op_net_x0;
|
2207 |
|
|
en_x2 <= constant5_op_net_x0;
|
2208 |
|
|
en_x20 <= constant1_op_net_x0;
|
2209 |
|
|
en_x21 <= constant5_op_net_x0;
|
2210 |
|
|
en_x22 <= constant1_op_net_x0;
|
2211 |
|
|
en_x23 <= constant1_op_net_x0;
|
2212 |
|
|
en_x24 <= constant1_op_net_x0;
|
2213 |
|
|
en_x25 <= constant1_op_net_x0;
|
2214 |
|
|
en_x26 <= constant1_op_net_x0;
|
2215 |
|
|
en_x27 <= constant5_op_net_x0;
|
2216 |
|
|
en_x28 <= constant5_op_net_x0;
|
2217 |
|
|
en_x29 <= constant5_op_net_x0;
|
2218 |
|
|
en_x3 <= constant5_op_net_x0;
|
2219 |
|
|
en_x30 <= constant5_op_net_x0;
|
2220 |
|
|
en_x31 <= constant5_op_net_x0;
|
2221 |
|
|
en_x32 <= constant5_op_net_x0;
|
2222 |
|
|
en_x4 <= constant5_op_net_x0;
|
2223 |
|
|
en_x5 <= constant5_op_net_x0;
|
2224 |
|
|
en_x6 <= constant5_op_net_x0;
|
2225 |
|
|
en_x7 <= constant5_op_net_x0;
|
2226 |
|
|
en_x8 <= constant5_op_net_x0;
|
2227 |
|
|
en_x9 <= constant5_op_net_x0;
|
2228 |
|
|
reg01_rd <= from_register3_data_out_net;
|
2229 |
|
|
reg01_rv <= from_register1_data_out_net;
|
2230 |
|
|
reg02_rd <= from_register5_data_out_net;
|
2231 |
|
|
reg02_rv <= from_register2_data_out_net;
|
2232 |
|
|
reg03_rd <= from_register7_data_out_net;
|
2233 |
|
|
reg03_rv <= from_register6_data_out_net;
|
2234 |
|
|
reg04_rd <= from_register8_data_out_net;
|
2235 |
|
|
reg04_rv <= from_register4_data_out_net;
|
2236 |
|
|
reg05_rd <= from_register10_data_out_net;
|
2237 |
|
|
reg05_rv <= from_register9_data_out_net;
|
2238 |
|
|
reg06_rd <= from_register11_data_out_net;
|
2239 |
|
|
reg06_rv <= from_register12_data_out_net;
|
2240 |
|
|
reg07_rd <= from_register13_data_out_net;
|
2241 |
|
|
reg07_rv <= from_register14_data_out_net;
|
2242 |
|
|
reg08_rd <= from_register15_data_out_net;
|
2243 |
|
|
reg08_rv <= from_register16_data_out_net;
|
2244 |
|
|
reg09_rd <= from_register17_data_out_net;
|
2245 |
|
|
reg09_rv <= from_register18_data_out_net;
|
2246 |
|
|
reg10_rd <= from_register19_data_out_net;
|
2247 |
|
|
reg10_rv <= from_register20_data_out_net;
|
2248 |
|
|
reg11_rd <= from_register21_data_out_net;
|
2249 |
|
|
reg11_rv <= from_register22_data_out_net;
|
2250 |
|
|
reg12_rd <= from_register23_data_out_net;
|
2251 |
|
|
reg12_rv <= from_register24_data_out_net;
|
2252 |
|
|
reg13_rd <= from_register25_data_out_net;
|
2253 |
|
|
reg13_rv <= from_register26_data_out_net;
|
2254 |
|
|
reg14_rd <= from_register27_data_out_net;
|
2255 |
|
|
reg14_rv <= from_register28_data_out_net;
|
2256 |
|
|
|
2257 |
|
|
constant1: entity work.constant_6293007044
|
2258 |
|
|
port map (
|
2259 |
|
|
ce => '0',
|
2260 |
|
|
clk => '0',
|
2261 |
|
|
clr => '0',
|
2262 |
|
|
op(0) => constant1_op_net_x0
|
2263 |
|
|
);
|
2264 |
|
|
|
2265 |
|
|
constant5: entity work.constant_6293007044
|
2266 |
|
|
port map (
|
2267 |
|
|
ce => '0',
|
2268 |
|
|
clk => '0',
|
2269 |
|
|
clr => '0',
|
2270 |
|
|
op(0) => constant5_op_net_x0
|
2271 |
|
|
);
|
2272 |
|
|
|
2273 |
|
|
end structural;
|