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barabba |
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-------------------------------------------------------------------
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-- System Generator version 13.2 VHDL source file.
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--
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-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
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-- text/file contains proprietary, confidential information of Xilinx,
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-- Inc., is distributed under license from Xilinx, Inc., and may be used,
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-- copied and/or disclosed only pursuant to the terms of a valid license
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-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
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-- this text/file solely for design, simulation, implementation and
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-- creation of design files limited to Xilinx devices or technologies.
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-- Use with non-Xilinx devices or technologies is expressly prohibited
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-- and immediately terminates your license unless covered by a separate
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-- agreement.
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--
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-- Xilinx is providing this design, code, or information "as is" solely
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-- for use in developing programs and solutions for Xilinx devices. By
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-- providing this design, code, or information as one possible
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-- implementation of this feature, application or standard, Xilinx is
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-- making no representation that this implementation is free from any
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-- claims of infringement. You are responsible for obtaining any rights
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-- you may require for your implementation. Xilinx expressly disclaims
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-- any warranty whatsoever with respect to the adequacy of the
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-- implementation, including but not limited to warranties of
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-- merchantability or fitness for a particular purpose.
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--
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-- Xilinx products are not intended for use in life support appliances,
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-- devices, or systems. Use in such applications is expressly prohibited.
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--
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-- Any modifications that are made to the source code are done at the user's
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-- sole risk and will be unsupported.
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--
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-- This copyright and support notice must be retained as part of this
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-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
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-- reserved.
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- System Generator version 13.2 VHDL source file.
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40 |
|
|
--
|
41 |
|
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-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
42 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
43 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
44 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
45 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
46 |
|
|
-- this text/file solely for design, simulation, implementation and
|
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|
|
-- creation of design files limited to Xilinx devices or technologies.
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-- Use with non-Xilinx devices or technologies is expressly prohibited
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-- and immediately terminates your license unless covered by a separate
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-- agreement.
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--
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-- Xilinx is providing this design, code, or information "as is" solely
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-- for use in developing programs and solutions for Xilinx devices. By
|
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|
-- providing this design, code, or information as one possible
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|
-- implementation of this feature, application or standard, Xilinx is
|
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-- making no representation that this implementation is free from any
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-- claims of infringement. You are responsible for obtaining any rights
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-- you may require for your implementation. Xilinx expressly disclaims
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-- any warranty whatsoever with respect to the adequacy of the
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-- implementation, including but not limited to warranties of
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-- merchantability or fitness for a particular purpose.
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--
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-- Xilinx products are not intended for use in life support appliances,
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-- devices, or systems. Use in such applications is expressly prohibited.
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--
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-- Any modifications that are made to the source code are done at the user's
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-- sole risk and will be unsupported.
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--
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-- This copyright and support notice must be retained as part of this
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-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
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-- reserved.
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-------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.conv_pkg.all;
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-- synopsys translate_off
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library unisim;
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use unisim.vcomponents.all;
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-- synopsys translate_on
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entity xlclockdriver is
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generic (
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period: integer := 2;
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log_2_period: integer := 0;
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pipeline_regs: integer := 5;
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use_bufg: integer := 0
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);
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port (
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sysclk: in std_logic;
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sysclr: in std_logic;
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sysce: in std_logic;
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clk: out std_logic;
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clr: out std_logic;
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ce: out std_logic;
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ce_logic: out std_logic
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);
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end xlclockdriver;
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architecture behavior of xlclockdriver is
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component bufg
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port (
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i: in std_logic;
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o: out std_logic
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);
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end component;
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component synth_reg_w_init
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generic (
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width: integer;
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init_index: integer;
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init_value: bit_vector;
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latency: integer
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);
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port (
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i: in std_logic_vector(width - 1 downto 0);
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ce: in std_logic;
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clr: in std_logic;
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clk: in std_logic;
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o: out std_logic_vector(width - 1 downto 0)
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);
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end component;
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function size_of_uint(inp: integer; power_of_2: boolean)
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return integer
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is
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constant inp_vec: std_logic_vector(31 downto 0) :=
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integer_to_std_logic_vector(inp,32, xlUnsigned);
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variable result: integer;
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begin
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result := 32;
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for i in 0 to 31 loop
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if inp_vec(i) = '1' then
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result := i;
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end if;
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end loop;
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if power_of_2 then
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return result;
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else
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return result+1;
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end if;
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end;
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function is_power_of_2(inp: std_logic_vector)
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return boolean
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is
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constant width: integer := inp'length;
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variable vec: std_logic_vector(width - 1 downto 0);
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variable single_bit_set: boolean;
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variable more_than_one_bit_set: boolean;
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variable result: boolean;
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begin
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vec := inp;
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single_bit_set := false;
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more_than_one_bit_set := false;
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-- synopsys translate_off
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if (is_XorU(vec)) then
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return false;
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end if;
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-- synopsys translate_on
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if width > 0 then
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for i in 0 to width - 1 loop
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if vec(i) = '1' then
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if single_bit_set then
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more_than_one_bit_set := true;
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end if;
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single_bit_set := true;
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end if;
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end loop;
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end if;
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if (single_bit_set and not(more_than_one_bit_set)) then
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result := true;
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else
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result := false;
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end if;
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return result;
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end;
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function ce_reg_init_val(index, period : integer)
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return integer
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is
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variable result: integer;
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begin
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result := 0;
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if ((index mod period) = 0) then
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result := 1;
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end if;
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return result;
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end;
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function remaining_pipe_regs(num_pipeline_regs, period : integer)
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return integer
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is
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variable factor, result: integer;
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begin
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189 |
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factor := (num_pipeline_regs / period);
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result := num_pipeline_regs - (period * factor) + 1;
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return result;
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end;
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function sg_min(L, R: INTEGER) return INTEGER is
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begin
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if L < R then
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return L;
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else
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return R;
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end if;
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end;
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constant max_pipeline_regs : integer := 8;
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constant pipe_regs : integer := 5;
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constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
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constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
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constant period_floor: integer := max(2, period);
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constant power_of_2_counter: boolean :=
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is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
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constant cnt_width: integer :=
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size_of_uint(period_floor, power_of_2_counter);
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constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
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integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
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constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
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integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
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constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
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integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
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signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
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signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
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attribute MAX_FANOUT : string;
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attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
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signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
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attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
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signal internal_ce: std_logic_vector(0 downto 0);
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signal internal_ce_logic: std_logic_vector(0 downto 0);
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signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
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begin
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clk <= sysclk;
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clr <= sysclr;
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cntr_gen: process(sysclk)
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begin
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if sysclk'event and sysclk = '1' then
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232 |
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if (sysce = '1') then
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if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
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clk_num <= (others => '0');
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else
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clk_num <= clk_num + 1;
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end if;
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end if;
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end if;
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end process;
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241 |
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clr_gen: process(clk_num, sysclr)
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242 |
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begin
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243 |
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if power_of_2_counter then
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244 |
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cnt_clr(0) <= sysclr;
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else
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246 |
|
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if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
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247 |
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or sysclr = '1') then
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248 |
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cnt_clr(0) <= '1';
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249 |
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else
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250 |
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cnt_clr(0) <= '0';
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end if;
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252 |
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end if;
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253 |
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end process;
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254 |
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clr_reg: synth_reg_w_init
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255 |
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generic map (
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256 |
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width => 1,
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257 |
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init_index => 0,
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258 |
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init_value => b"0000",
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259 |
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latency => 1
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260 |
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)
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261 |
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port map (
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262 |
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i => cnt_clr,
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263 |
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ce => sysce,
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264 |
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clr => sysclr,
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265 |
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clk => sysclk,
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266 |
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o => cnt_clr_dly
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267 |
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);
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268 |
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pipelined_ce : if period > 1 generate
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269 |
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ce_gen: process(clk_num)
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270 |
|
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begin
|
271 |
|
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if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
|
272 |
|
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ce_vec(num_pipeline_regs) <= '1';
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273 |
|
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else
|
274 |
|
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ce_vec(num_pipeline_regs) <= '0';
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275 |
|
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end if;
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276 |
|
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end process;
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277 |
|
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ce_pipeline: for index in num_pipeline_regs downto 1 generate
|
278 |
|
|
ce_reg : synth_reg_w_init
|
279 |
|
|
generic map (
|
280 |
|
|
width => 1,
|
281 |
|
|
init_index => ce_reg_init_val(index, period),
|
282 |
|
|
init_value => b"0000",
|
283 |
|
|
latency => 1
|
284 |
|
|
)
|
285 |
|
|
port map (
|
286 |
|
|
i => ce_vec(index downto index),
|
287 |
|
|
ce => sysce,
|
288 |
|
|
clr => sysclr,
|
289 |
|
|
clk => sysclk,
|
290 |
|
|
o => ce_vec(index-1 downto index-1)
|
291 |
|
|
);
|
292 |
|
|
end generate;
|
293 |
|
|
internal_ce <= ce_vec(0 downto 0);
|
294 |
|
|
end generate;
|
295 |
|
|
pipelined_ce_logic: if period > 1 generate
|
296 |
|
|
ce_gen_logic: process(clk_num)
|
297 |
|
|
begin
|
298 |
|
|
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
|
299 |
|
|
ce_vec_logic(num_pipeline_regs) <= '1';
|
300 |
|
|
else
|
301 |
|
|
ce_vec_logic(num_pipeline_regs) <= '0';
|
302 |
|
|
end if;
|
303 |
|
|
end process;
|
304 |
|
|
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
|
305 |
|
|
ce_logic_reg : synth_reg_w_init
|
306 |
|
|
generic map (
|
307 |
|
|
width => 1,
|
308 |
|
|
init_index => ce_reg_init_val(index, period),
|
309 |
|
|
init_value => b"0000",
|
310 |
|
|
latency => 1
|
311 |
|
|
)
|
312 |
|
|
port map (
|
313 |
|
|
i => ce_vec_logic(index downto index),
|
314 |
|
|
ce => sysce,
|
315 |
|
|
clr => sysclr,
|
316 |
|
|
clk => sysclk,
|
317 |
|
|
o => ce_vec_logic(index-1 downto index-1)
|
318 |
|
|
);
|
319 |
|
|
end generate;
|
320 |
|
|
internal_ce_logic <= ce_vec_logic(0 downto 0);
|
321 |
|
|
end generate;
|
322 |
|
|
use_bufg_true: if period > 1 and use_bufg = 1 generate
|
323 |
|
|
ce_bufg_inst: bufg
|
324 |
|
|
port map (
|
325 |
|
|
i => internal_ce(0),
|
326 |
|
|
o => ce
|
327 |
|
|
);
|
328 |
|
|
ce_bufg_inst_logic: bufg
|
329 |
|
|
port map (
|
330 |
|
|
i => internal_ce_logic(0),
|
331 |
|
|
o => ce_logic
|
332 |
|
|
);
|
333 |
|
|
end generate;
|
334 |
|
|
use_bufg_false: if period > 1 and (use_bufg = 0) generate
|
335 |
|
|
ce <= internal_ce(0);
|
336 |
|
|
ce_logic <= internal_ce_logic(0);
|
337 |
|
|
end generate;
|
338 |
|
|
generate_system_clk: if period = 1 generate
|
339 |
|
|
ce <= sysce;
|
340 |
|
|
ce_logic <= sysce;
|
341 |
|
|
end generate;
|
342 |
|
|
end architecture behavior;
|
343 |
|
|
library IEEE;
|
344 |
|
|
use IEEE.std_logic_1164.all;
|
345 |
|
|
use work.conv_pkg.all;
|
346 |
|
|
|
347 |
|
|
entity default_clock_driver is
|
348 |
|
|
port (
|
349 |
|
|
sysce: in std_logic;
|
350 |
|
|
sysce_clr: in std_logic;
|
351 |
|
|
sysclk: in std_logic;
|
352 |
|
|
ce_1: out std_logic;
|
353 |
|
|
clk_1: out std_logic
|
354 |
|
|
);
|
355 |
|
|
end default_clock_driver;
|
356 |
|
|
|
357 |
|
|
architecture structural of default_clock_driver is
|
358 |
|
|
attribute syn_noprune: boolean;
|
359 |
|
|
attribute syn_noprune of structural : architecture is true;
|
360 |
|
|
attribute optimize_primitives: boolean;
|
361 |
|
|
attribute optimize_primitives of structural : architecture is false;
|
362 |
|
|
attribute dont_touch: boolean;
|
363 |
|
|
attribute dont_touch of structural : architecture is true;
|
364 |
|
|
|
365 |
|
|
signal sysce_clr_x0: std_logic;
|
366 |
|
|
signal sysce_x0: std_logic;
|
367 |
|
|
signal sysclk_x0: std_logic;
|
368 |
|
|
signal xlclockdriver_1_ce: std_logic;
|
369 |
|
|
signal xlclockdriver_1_clk: std_logic;
|
370 |
|
|
|
371 |
|
|
begin
|
372 |
|
|
sysce_x0 <= sysce;
|
373 |
|
|
sysce_clr_x0 <= sysce_clr;
|
374 |
|
|
sysclk_x0 <= sysclk;
|
375 |
|
|
ce_1 <= xlclockdriver_1_ce;
|
376 |
|
|
clk_1 <= xlclockdriver_1_clk;
|
377 |
|
|
|
378 |
|
|
xlclockdriver_1: entity work.xlclockdriver
|
379 |
|
|
generic map (
|
380 |
|
|
log_2_period => 1,
|
381 |
|
|
period => 1,
|
382 |
|
|
use_bufg => 0
|
383 |
|
|
)
|
384 |
|
|
port map (
|
385 |
|
|
sysce => sysce_x0,
|
386 |
|
|
sysclk => sysclk_x0,
|
387 |
|
|
sysclr => sysce_clr_x0,
|
388 |
|
|
ce => xlclockdriver_1_ce,
|
389 |
|
|
clk => xlclockdriver_1_clk
|
390 |
|
|
);
|
391 |
|
|
|
392 |
|
|
end structural;
|
393 |
|
|
library IEEE;
|
394 |
|
|
use IEEE.std_logic_1164.all;
|
395 |
|
|
use work.conv_pkg.all;
|
396 |
|
|
|
397 |
|
|
entity inout_logic_cw is
|
398 |
|
|
port (
|
399 |
|
|
ce: in std_logic := '1';
|
400 |
|
|
clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
401 |
|
|
debug_in_1i: in std_logic_vector(31 downto 0);
|
402 |
|
|
debug_in_2i: in std_logic_vector(31 downto 0);
|
403 |
|
|
debug_in_3i: in std_logic_vector(31 downto 0);
|
404 |
|
|
debug_in_4i: in std_logic_vector(31 downto 0);
|
405 |
|
|
dma_host2board_busy: in std_logic;
|
406 |
|
|
dma_host2board_done: in std_logic;
|
407 |
|
|
from_register10_data_out: in std_logic_vector(31 downto 0);
|
408 |
|
|
from_register11_data_out: in std_logic_vector(31 downto 0);
|
409 |
|
|
from_register12_data_out: in std_logic_vector(0 downto 0);
|
410 |
|
|
from_register13_data_out: in std_logic_vector(31 downto 0);
|
411 |
|
|
from_register14_data_out: in std_logic_vector(0 downto 0);
|
412 |
|
|
from_register15_data_out: in std_logic_vector(31 downto 0);
|
413 |
|
|
from_register16_data_out: in std_logic_vector(0 downto 0);
|
414 |
|
|
from_register17_data_out: in std_logic_vector(31 downto 0);
|
415 |
|
|
from_register18_data_out: in std_logic_vector(0 downto 0);
|
416 |
|
|
from_register19_data_out: in std_logic_vector(31 downto 0);
|
417 |
|
|
from_register1_data_out: in std_logic_vector(0 downto 0);
|
418 |
|
|
from_register20_data_out: in std_logic_vector(0 downto 0);
|
419 |
|
|
from_register21_data_out: in std_logic_vector(31 downto 0);
|
420 |
|
|
from_register22_data_out: in std_logic_vector(0 downto 0);
|
421 |
|
|
from_register23_data_out: in std_logic_vector(31 downto 0);
|
422 |
|
|
from_register24_data_out: in std_logic_vector(0 downto 0);
|
423 |
|
|
from_register25_data_out: in std_logic_vector(31 downto 0);
|
424 |
|
|
from_register26_data_out: in std_logic_vector(0 downto 0);
|
425 |
|
|
from_register27_data_out: in std_logic_vector(31 downto 0);
|
426 |
|
|
from_register28_data_out: in std_logic_vector(0 downto 0);
|
427 |
|
|
from_register2_data_out: in std_logic_vector(0 downto 0);
|
428 |
|
|
from_register3_data_out: in std_logic_vector(31 downto 0);
|
429 |
|
|
from_register4_data_out: in std_logic_vector(0 downto 0);
|
430 |
|
|
from_register5_data_out: in std_logic_vector(31 downto 0);
|
431 |
|
|
from_register6_data_out: in std_logic_vector(0 downto 0);
|
432 |
|
|
from_register7_data_out: in std_logic_vector(31 downto 0);
|
433 |
|
|
from_register8_data_out: in std_logic_vector(31 downto 0);
|
434 |
|
|
from_register9_data_out: in std_logic_vector(0 downto 0);
|
435 |
|
|
reg01_td: in std_logic_vector(31 downto 0);
|
436 |
|
|
reg01_tv: in std_logic;
|
437 |
|
|
reg02_td: in std_logic_vector(31 downto 0);
|
438 |
|
|
reg02_tv: in std_logic;
|
439 |
|
|
reg03_td: in std_logic_vector(31 downto 0);
|
440 |
|
|
reg03_tv: in std_logic;
|
441 |
|
|
reg04_td: in std_logic_vector(31 downto 0);
|
442 |
|
|
reg04_tv: in std_logic;
|
443 |
|
|
reg05_td: in std_logic_vector(31 downto 0);
|
444 |
|
|
reg05_tv: in std_logic;
|
445 |
|
|
reg06_td: in std_logic_vector(31 downto 0);
|
446 |
|
|
reg06_tv: in std_logic;
|
447 |
|
|
reg07_td: in std_logic_vector(31 downto 0);
|
448 |
|
|
reg07_tv: in std_logic;
|
449 |
|
|
reg08_td: in std_logic_vector(31 downto 0);
|
450 |
|
|
reg08_tv: in std_logic;
|
451 |
|
|
reg09_td: in std_logic_vector(31 downto 0);
|
452 |
|
|
reg09_tv: in std_logic;
|
453 |
|
|
reg10_td: in std_logic_vector(31 downto 0);
|
454 |
|
|
reg10_tv: in std_logic;
|
455 |
|
|
reg11_td: in std_logic_vector(31 downto 0);
|
456 |
|
|
reg11_tv: in std_logic;
|
457 |
|
|
reg12_td: in std_logic_vector(31 downto 0);
|
458 |
|
|
reg12_tv: in std_logic;
|
459 |
|
|
reg13_td: in std_logic_vector(31 downto 0);
|
460 |
|
|
reg13_tv: in std_logic;
|
461 |
|
|
reg14_td: in std_logic_vector(31 downto 0);
|
462 |
|
|
reg14_tv: in std_logic;
|
463 |
|
|
to_register10_dout: in std_logic_vector(0 downto 0);
|
464 |
|
|
to_register11_dout: in std_logic_vector(31 downto 0);
|
465 |
|
|
to_register12_dout: in std_logic_vector(0 downto 0);
|
466 |
|
|
to_register13_dout: in std_logic_vector(31 downto 0);
|
467 |
|
|
to_register14_dout: in std_logic_vector(0 downto 0);
|
468 |
|
|
to_register15_dout: in std_logic_vector(31 downto 0);
|
469 |
|
|
to_register16_dout: in std_logic_vector(0 downto 0);
|
470 |
|
|
to_register17_dout: in std_logic_vector(31 downto 0);
|
471 |
|
|
to_register18_dout: in std_logic_vector(0 downto 0);
|
472 |
|
|
to_register19_dout: in std_logic_vector(0 downto 0);
|
473 |
|
|
to_register1_dout: in std_logic_vector(31 downto 0);
|
474 |
|
|
to_register20_dout: in std_logic_vector(31 downto 0);
|
475 |
|
|
to_register21_dout: in std_logic_vector(0 downto 0);
|
476 |
|
|
to_register22_dout: in std_logic_vector(31 downto 0);
|
477 |
|
|
to_register23_dout: in std_logic_vector(0 downto 0);
|
478 |
|
|
to_register24_dout: in std_logic_vector(31 downto 0);
|
479 |
|
|
to_register25_dout: in std_logic_vector(0 downto 0);
|
480 |
|
|
to_register26_dout: in std_logic_vector(31 downto 0);
|
481 |
|
|
to_register27_dout: in std_logic_vector(0 downto 0);
|
482 |
|
|
to_register28_dout: in std_logic_vector(31 downto 0);
|
483 |
|
|
to_register29_dout: in std_logic_vector(0 downto 0);
|
484 |
|
|
to_register2_dout: in std_logic_vector(31 downto 0);
|
485 |
|
|
to_register30_dout: in std_logic_vector(31 downto 0);
|
486 |
|
|
to_register31_dout: in std_logic_vector(0 downto 0);
|
487 |
|
|
to_register32_dout: in std_logic_vector(31 downto 0);
|
488 |
|
|
to_register33_dout: in std_logic_vector(0 downto 0);
|
489 |
|
|
to_register34_dout: in std_logic_vector(31 downto 0);
|
490 |
|
|
to_register3_dout: in std_logic_vector(0 downto 0);
|
491 |
|
|
to_register4_dout: in std_logic_vector(0 downto 0);
|
492 |
|
|
to_register5_dout: in std_logic_vector(31 downto 0);
|
493 |
|
|
to_register6_dout: in std_logic_vector(31 downto 0);
|
494 |
|
|
to_register7_dout: in std_logic_vector(31 downto 0);
|
495 |
|
|
to_register8_dout: in std_logic_vector(0 downto 0);
|
496 |
|
|
to_register9_dout: in std_logic_vector(31 downto 0);
|
497 |
|
|
reg01_rd: out std_logic_vector(31 downto 0);
|
498 |
|
|
reg01_rv: out std_logic;
|
499 |
|
|
reg02_rd: out std_logic_vector(31 downto 0);
|
500 |
|
|
reg02_rv: out std_logic;
|
501 |
|
|
reg03_rd: out std_logic_vector(31 downto 0);
|
502 |
|
|
reg03_rv: out std_logic;
|
503 |
|
|
reg04_rd: out std_logic_vector(31 downto 0);
|
504 |
|
|
reg04_rv: out std_logic;
|
505 |
|
|
reg05_rd: out std_logic_vector(31 downto 0);
|
506 |
|
|
reg05_rv: out std_logic;
|
507 |
|
|
reg06_rd: out std_logic_vector(31 downto 0);
|
508 |
|
|
reg06_rv: out std_logic;
|
509 |
|
|
reg07_rd: out std_logic_vector(31 downto 0);
|
510 |
|
|
reg07_rv: out std_logic;
|
511 |
|
|
reg08_rd: out std_logic_vector(31 downto 0);
|
512 |
|
|
reg08_rv: out std_logic;
|
513 |
|
|
reg09_rd: out std_logic_vector(31 downto 0);
|
514 |
|
|
reg09_rv: out std_logic;
|
515 |
|
|
reg10_rd: out std_logic_vector(31 downto 0);
|
516 |
|
|
reg10_rv: out std_logic;
|
517 |
|
|
reg11_rd: out std_logic_vector(31 downto 0);
|
518 |
|
|
reg11_rv: out std_logic;
|
519 |
|
|
reg12_rd: out std_logic_vector(31 downto 0);
|
520 |
|
|
reg12_rv: out std_logic;
|
521 |
|
|
reg13_rd: out std_logic_vector(31 downto 0);
|
522 |
|
|
reg13_rv: out std_logic;
|
523 |
|
|
reg14_rd: out std_logic_vector(31 downto 0);
|
524 |
|
|
reg14_rv: out std_logic;
|
525 |
|
|
to_register10_ce: out std_logic;
|
526 |
|
|
to_register10_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
527 |
|
|
to_register10_clr: out std_logic;
|
528 |
|
|
to_register10_data_in: out std_logic_vector(0 downto 0);
|
529 |
|
|
to_register10_en: out std_logic_vector(0 downto 0);
|
530 |
|
|
to_register11_ce: out std_logic;
|
531 |
|
|
to_register11_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
532 |
|
|
to_register11_clr: out std_logic;
|
533 |
|
|
to_register11_data_in: out std_logic_vector(31 downto 0);
|
534 |
|
|
to_register11_en: out std_logic_vector(0 downto 0);
|
535 |
|
|
to_register12_ce: out std_logic;
|
536 |
|
|
to_register12_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
537 |
|
|
to_register12_clr: out std_logic;
|
538 |
|
|
to_register12_data_in: out std_logic_vector(0 downto 0);
|
539 |
|
|
to_register12_en: out std_logic_vector(0 downto 0);
|
540 |
|
|
to_register13_ce: out std_logic;
|
541 |
|
|
to_register13_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
542 |
|
|
to_register13_clr: out std_logic;
|
543 |
|
|
to_register13_data_in: out std_logic_vector(31 downto 0);
|
544 |
|
|
to_register13_en: out std_logic_vector(0 downto 0);
|
545 |
|
|
to_register14_ce: out std_logic;
|
546 |
|
|
to_register14_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
547 |
|
|
to_register14_clr: out std_logic;
|
548 |
|
|
to_register14_data_in: out std_logic_vector(0 downto 0);
|
549 |
|
|
to_register14_en: out std_logic_vector(0 downto 0);
|
550 |
|
|
to_register15_ce: out std_logic;
|
551 |
|
|
to_register15_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
552 |
|
|
to_register15_clr: out std_logic;
|
553 |
|
|
to_register15_data_in: out std_logic_vector(31 downto 0);
|
554 |
|
|
to_register15_en: out std_logic_vector(0 downto 0);
|
555 |
|
|
to_register16_ce: out std_logic;
|
556 |
|
|
to_register16_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
557 |
|
|
to_register16_clr: out std_logic;
|
558 |
|
|
to_register16_data_in: out std_logic_vector(0 downto 0);
|
559 |
|
|
to_register16_en: out std_logic_vector(0 downto 0);
|
560 |
|
|
to_register17_ce: out std_logic;
|
561 |
|
|
to_register17_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
562 |
|
|
to_register17_clr: out std_logic;
|
563 |
|
|
to_register17_data_in: out std_logic_vector(31 downto 0);
|
564 |
|
|
to_register17_en: out std_logic_vector(0 downto 0);
|
565 |
|
|
to_register18_ce: out std_logic;
|
566 |
|
|
to_register18_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
567 |
|
|
to_register18_clr: out std_logic;
|
568 |
|
|
to_register18_data_in: out std_logic_vector(0 downto 0);
|
569 |
|
|
to_register18_en: out std_logic_vector(0 downto 0);
|
570 |
|
|
to_register19_ce: out std_logic;
|
571 |
|
|
to_register19_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
572 |
|
|
to_register19_clr: out std_logic;
|
573 |
|
|
to_register19_data_in: out std_logic_vector(0 downto 0);
|
574 |
|
|
to_register19_en: out std_logic_vector(0 downto 0);
|
575 |
|
|
to_register1_ce: out std_logic;
|
576 |
|
|
to_register1_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
577 |
|
|
to_register1_clr: out std_logic;
|
578 |
|
|
to_register1_data_in: out std_logic_vector(31 downto 0);
|
579 |
|
|
to_register1_en: out std_logic_vector(0 downto 0);
|
580 |
|
|
to_register20_ce: out std_logic;
|
581 |
|
|
to_register20_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
582 |
|
|
to_register20_clr: out std_logic;
|
583 |
|
|
to_register20_data_in: out std_logic_vector(31 downto 0);
|
584 |
|
|
to_register20_en: out std_logic_vector(0 downto 0);
|
585 |
|
|
to_register21_ce: out std_logic;
|
586 |
|
|
to_register21_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
587 |
|
|
to_register21_clr: out std_logic;
|
588 |
|
|
to_register21_data_in: out std_logic_vector(0 downto 0);
|
589 |
|
|
to_register21_en: out std_logic_vector(0 downto 0);
|
590 |
|
|
to_register22_ce: out std_logic;
|
591 |
|
|
to_register22_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
592 |
|
|
to_register22_clr: out std_logic;
|
593 |
|
|
to_register22_data_in: out std_logic_vector(31 downto 0);
|
594 |
|
|
to_register22_en: out std_logic_vector(0 downto 0);
|
595 |
|
|
to_register23_ce: out std_logic;
|
596 |
|
|
to_register23_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
597 |
|
|
to_register23_clr: out std_logic;
|
598 |
|
|
to_register23_data_in: out std_logic_vector(0 downto 0);
|
599 |
|
|
to_register23_en: out std_logic_vector(0 downto 0);
|
600 |
|
|
to_register24_ce: out std_logic;
|
601 |
|
|
to_register24_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
602 |
|
|
to_register24_clr: out std_logic;
|
603 |
|
|
to_register24_data_in: out std_logic_vector(31 downto 0);
|
604 |
|
|
to_register24_en: out std_logic_vector(0 downto 0);
|
605 |
|
|
to_register25_ce: out std_logic;
|
606 |
|
|
to_register25_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
607 |
|
|
to_register25_clr: out std_logic;
|
608 |
|
|
to_register25_data_in: out std_logic_vector(0 downto 0);
|
609 |
|
|
to_register25_en: out std_logic_vector(0 downto 0);
|
610 |
|
|
to_register26_ce: out std_logic;
|
611 |
|
|
to_register26_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
612 |
|
|
to_register26_clr: out std_logic;
|
613 |
|
|
to_register26_data_in: out std_logic_vector(31 downto 0);
|
614 |
|
|
to_register26_en: out std_logic_vector(0 downto 0);
|
615 |
|
|
to_register27_ce: out std_logic;
|
616 |
|
|
to_register27_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
617 |
|
|
to_register27_clr: out std_logic;
|
618 |
|
|
to_register27_data_in: out std_logic_vector(0 downto 0);
|
619 |
|
|
to_register27_en: out std_logic_vector(0 downto 0);
|
620 |
|
|
to_register28_ce: out std_logic;
|
621 |
|
|
to_register28_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
622 |
|
|
to_register28_clr: out std_logic;
|
623 |
|
|
to_register28_data_in: out std_logic_vector(31 downto 0);
|
624 |
|
|
to_register28_en: out std_logic_vector(0 downto 0);
|
625 |
|
|
to_register29_ce: out std_logic;
|
626 |
|
|
to_register29_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
627 |
|
|
to_register29_clr: out std_logic;
|
628 |
|
|
to_register29_data_in: out std_logic_vector(0 downto 0);
|
629 |
|
|
to_register29_en: out std_logic_vector(0 downto 0);
|
630 |
|
|
to_register2_ce: out std_logic;
|
631 |
|
|
to_register2_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
632 |
|
|
to_register2_clr: out std_logic;
|
633 |
|
|
to_register2_data_in: out std_logic_vector(31 downto 0);
|
634 |
|
|
to_register2_en: out std_logic_vector(0 downto 0);
|
635 |
|
|
to_register30_ce: out std_logic;
|
636 |
|
|
to_register30_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
637 |
|
|
to_register30_clr: out std_logic;
|
638 |
|
|
to_register30_data_in: out std_logic_vector(31 downto 0);
|
639 |
|
|
to_register30_en: out std_logic_vector(0 downto 0);
|
640 |
|
|
to_register31_ce: out std_logic;
|
641 |
|
|
to_register31_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
642 |
|
|
to_register31_clr: out std_logic;
|
643 |
|
|
to_register31_data_in: out std_logic_vector(0 downto 0);
|
644 |
|
|
to_register31_en: out std_logic_vector(0 downto 0);
|
645 |
|
|
to_register32_ce: out std_logic;
|
646 |
|
|
to_register32_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
647 |
|
|
to_register32_clr: out std_logic;
|
648 |
|
|
to_register32_data_in: out std_logic_vector(31 downto 0);
|
649 |
|
|
to_register32_en: out std_logic_vector(0 downto 0);
|
650 |
|
|
to_register33_ce: out std_logic;
|
651 |
|
|
to_register33_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
652 |
|
|
to_register33_clr: out std_logic;
|
653 |
|
|
to_register33_data_in: out std_logic_vector(0 downto 0);
|
654 |
|
|
to_register33_en: out std_logic_vector(0 downto 0);
|
655 |
|
|
to_register34_ce: out std_logic;
|
656 |
|
|
to_register34_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
657 |
|
|
to_register34_clr: out std_logic;
|
658 |
|
|
to_register34_data_in: out std_logic_vector(31 downto 0);
|
659 |
|
|
to_register34_en: out std_logic_vector(0 downto 0);
|
660 |
|
|
to_register3_ce: out std_logic;
|
661 |
|
|
to_register3_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
662 |
|
|
to_register3_clr: out std_logic;
|
663 |
|
|
to_register3_data_in: out std_logic_vector(0 downto 0);
|
664 |
|
|
to_register3_en: out std_logic_vector(0 downto 0);
|
665 |
|
|
to_register4_ce: out std_logic;
|
666 |
|
|
to_register4_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
667 |
|
|
to_register4_clr: out std_logic;
|
668 |
|
|
to_register4_data_in: out std_logic_vector(0 downto 0);
|
669 |
|
|
to_register4_en: out std_logic_vector(0 downto 0);
|
670 |
|
|
to_register5_ce: out std_logic;
|
671 |
|
|
to_register5_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
672 |
|
|
to_register5_clr: out std_logic;
|
673 |
|
|
to_register5_data_in: out std_logic_vector(31 downto 0);
|
674 |
|
|
to_register5_en: out std_logic_vector(0 downto 0);
|
675 |
|
|
to_register6_ce: out std_logic;
|
676 |
|
|
to_register6_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
677 |
|
|
to_register6_clr: out std_logic;
|
678 |
|
|
to_register6_data_in: out std_logic_vector(31 downto 0);
|
679 |
|
|
to_register6_en: out std_logic_vector(0 downto 0);
|
680 |
|
|
to_register7_ce: out std_logic;
|
681 |
|
|
to_register7_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
682 |
|
|
to_register7_clr: out std_logic;
|
683 |
|
|
to_register7_data_in: out std_logic_vector(31 downto 0);
|
684 |
|
|
to_register7_en: out std_logic_vector(0 downto 0);
|
685 |
|
|
to_register8_ce: out std_logic;
|
686 |
|
|
to_register8_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
687 |
|
|
to_register8_clr: out std_logic;
|
688 |
|
|
to_register8_data_in: out std_logic_vector(0 downto 0);
|
689 |
|
|
to_register8_en: out std_logic_vector(0 downto 0);
|
690 |
|
|
to_register9_ce: out std_logic;
|
691 |
|
|
to_register9_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
692 |
|
|
to_register9_clr: out std_logic;
|
693 |
|
|
to_register9_data_in: out std_logic_vector(31 downto 0);
|
694 |
|
|
to_register9_en: out std_logic_vector(0 downto 0)
|
695 |
|
|
);
|
696 |
|
|
end inout_logic_cw;
|
697 |
|
|
|
698 |
|
|
architecture structural of inout_logic_cw is
|
699 |
|
|
component xlpersistentdff
|
700 |
|
|
port (
|
701 |
|
|
clk: in std_logic;
|
702 |
|
|
d: in std_logic;
|
703 |
|
|
q: out std_logic
|
704 |
|
|
);
|
705 |
|
|
end component;
|
706 |
|
|
attribute syn_black_box: boolean;
|
707 |
|
|
attribute syn_black_box of xlpersistentdff: component is true;
|
708 |
|
|
attribute box_type: string;
|
709 |
|
|
attribute box_type of xlpersistentdff: component is "black_box";
|
710 |
|
|
attribute syn_noprune: boolean;
|
711 |
|
|
attribute optimize_primitives: boolean;
|
712 |
|
|
attribute dont_touch: boolean;
|
713 |
|
|
attribute syn_noprune of xlpersistentdff: component is true;
|
714 |
|
|
attribute optimize_primitives of xlpersistentdff: component is false;
|
715 |
|
|
attribute dont_touch of xlpersistentdff: component is true;
|
716 |
|
|
|
717 |
|
|
signal ce_1_sg: std_logic;
|
718 |
|
|
attribute MAX_FANOUT: string;
|
719 |
|
|
attribute MAX_FANOUT of ce_1_sg: signal is "REDUCE";
|
720 |
|
|
signal clkNet: std_logic;
|
721 |
|
|
signal clk_1_sg: std_logic;
|
722 |
|
|
signal constant1_op_net_x0: std_logic;
|
723 |
|
|
signal constant1_op_net_x1: std_logic;
|
724 |
|
|
signal constant1_op_net_x10: std_logic;
|
725 |
|
|
signal constant1_op_net_x11: std_logic;
|
726 |
|
|
signal constant1_op_net_x12: std_logic;
|
727 |
|
|
signal constant1_op_net_x13: std_logic;
|
728 |
|
|
signal constant1_op_net_x2: std_logic;
|
729 |
|
|
signal constant1_op_net_x3: std_logic;
|
730 |
|
|
signal constant1_op_net_x4: std_logic;
|
731 |
|
|
signal constant1_op_net_x5: std_logic;
|
732 |
|
|
signal constant1_op_net_x6: std_logic;
|
733 |
|
|
signal constant1_op_net_x7: std_logic;
|
734 |
|
|
signal constant1_op_net_x8: std_logic;
|
735 |
|
|
signal constant1_op_net_x9: std_logic;
|
736 |
|
|
signal constant5_op_net_x0: std_logic;
|
737 |
|
|
signal constant5_op_net_x1: std_logic;
|
738 |
|
|
signal constant5_op_net_x10: std_logic;
|
739 |
|
|
signal constant5_op_net_x11: std_logic;
|
740 |
|
|
signal constant5_op_net_x12: std_logic;
|
741 |
|
|
signal constant5_op_net_x13: std_logic;
|
742 |
|
|
signal constant5_op_net_x14: std_logic;
|
743 |
|
|
signal constant5_op_net_x15: std_logic;
|
744 |
|
|
signal constant5_op_net_x16: std_logic;
|
745 |
|
|
signal constant5_op_net_x17: std_logic;
|
746 |
|
|
signal constant5_op_net_x18: std_logic;
|
747 |
|
|
signal constant5_op_net_x19: std_logic;
|
748 |
|
|
signal constant5_op_net_x2: std_logic;
|
749 |
|
|
signal constant5_op_net_x3: std_logic;
|
750 |
|
|
signal constant5_op_net_x4: std_logic;
|
751 |
|
|
signal constant5_op_net_x5: std_logic;
|
752 |
|
|
signal constant5_op_net_x6: std_logic;
|
753 |
|
|
signal constant5_op_net_x7: std_logic;
|
754 |
|
|
signal constant5_op_net_x8: std_logic;
|
755 |
|
|
signal constant5_op_net_x9: std_logic;
|
756 |
|
|
signal debug_in_1i_net: std_logic_vector(31 downto 0);
|
757 |
|
|
signal debug_in_1i_net_x0: std_logic_vector(31 downto 0);
|
758 |
|
|
signal debug_in_2i_net: std_logic_vector(31 downto 0);
|
759 |
|
|
signal debug_in_2i_net_x0: std_logic_vector(31 downto 0);
|
760 |
|
|
signal debug_in_3i_net: std_logic_vector(31 downto 0);
|
761 |
|
|
signal debug_in_3i_net_x0: std_logic_vector(31 downto 0);
|
762 |
|
|
signal debug_in_4i_net: std_logic_vector(31 downto 0);
|
763 |
|
|
signal debug_in_4i_net_x0: std_logic_vector(31 downto 0);
|
764 |
|
|
signal dma_host2board_busy_net: std_logic;
|
765 |
|
|
signal dma_host2board_busy_net_x0: std_logic;
|
766 |
|
|
signal dma_host2board_done_net: std_logic;
|
767 |
|
|
signal dma_host2board_done_net_x0: std_logic;
|
768 |
|
|
signal from_register10_data_out_net: std_logic_vector(31 downto 0);
|
769 |
|
|
signal from_register10_data_out_net_x0: std_logic_vector(31 downto 0);
|
770 |
|
|
signal from_register11_data_out_net: std_logic_vector(31 downto 0);
|
771 |
|
|
signal from_register11_data_out_net_x0: std_logic_vector(31 downto 0);
|
772 |
|
|
signal from_register12_data_out_net: std_logic;
|
773 |
|
|
signal from_register12_data_out_net_x0: std_logic;
|
774 |
|
|
signal from_register13_data_out_net: std_logic_vector(31 downto 0);
|
775 |
|
|
signal from_register13_data_out_net_x0: std_logic_vector(31 downto 0);
|
776 |
|
|
signal from_register14_data_out_net: std_logic;
|
777 |
|
|
signal from_register14_data_out_net_x0: std_logic;
|
778 |
|
|
signal from_register15_data_out_net: std_logic_vector(31 downto 0);
|
779 |
|
|
signal from_register15_data_out_net_x0: std_logic_vector(31 downto 0);
|
780 |
|
|
signal from_register16_data_out_net: std_logic;
|
781 |
|
|
signal from_register16_data_out_net_x0: std_logic;
|
782 |
|
|
signal from_register17_data_out_net: std_logic_vector(31 downto 0);
|
783 |
|
|
signal from_register17_data_out_net_x0: std_logic_vector(31 downto 0);
|
784 |
|
|
signal from_register18_data_out_net: std_logic;
|
785 |
|
|
signal from_register18_data_out_net_x0: std_logic;
|
786 |
|
|
signal from_register19_data_out_net: std_logic_vector(31 downto 0);
|
787 |
|
|
signal from_register19_data_out_net_x0: std_logic_vector(31 downto 0);
|
788 |
|
|
signal from_register1_data_out_net: std_logic;
|
789 |
|
|
signal from_register1_data_out_net_x0: std_logic;
|
790 |
|
|
signal from_register20_data_out_net: std_logic;
|
791 |
|
|
signal from_register20_data_out_net_x0: std_logic;
|
792 |
|
|
signal from_register21_data_out_net: std_logic_vector(31 downto 0);
|
793 |
|
|
signal from_register21_data_out_net_x0: std_logic_vector(31 downto 0);
|
794 |
|
|
signal from_register22_data_out_net: std_logic;
|
795 |
|
|
signal from_register22_data_out_net_x0: std_logic;
|
796 |
|
|
signal from_register23_data_out_net: std_logic_vector(31 downto 0);
|
797 |
|
|
signal from_register23_data_out_net_x0: std_logic_vector(31 downto 0);
|
798 |
|
|
signal from_register24_data_out_net: std_logic;
|
799 |
|
|
signal from_register24_data_out_net_x0: std_logic;
|
800 |
|
|
signal from_register25_data_out_net: std_logic_vector(31 downto 0);
|
801 |
|
|
signal from_register25_data_out_net_x0: std_logic_vector(31 downto 0);
|
802 |
|
|
signal from_register26_data_out_net: std_logic;
|
803 |
|
|
signal from_register26_data_out_net_x0: std_logic;
|
804 |
|
|
signal from_register27_data_out_net: std_logic_vector(31 downto 0);
|
805 |
|
|
signal from_register27_data_out_net_x0: std_logic_vector(31 downto 0);
|
806 |
|
|
signal from_register28_data_out_net: std_logic;
|
807 |
|
|
signal from_register28_data_out_net_x0: std_logic;
|
808 |
|
|
signal from_register2_data_out_net: std_logic;
|
809 |
|
|
signal from_register2_data_out_net_x0: std_logic;
|
810 |
|
|
signal from_register3_data_out_net: std_logic_vector(31 downto 0);
|
811 |
|
|
signal from_register3_data_out_net_x0: std_logic_vector(31 downto 0);
|
812 |
|
|
signal from_register4_data_out_net: std_logic;
|
813 |
|
|
signal from_register4_data_out_net_x0: std_logic;
|
814 |
|
|
signal from_register5_data_out_net: std_logic_vector(31 downto 0);
|
815 |
|
|
signal from_register5_data_out_net_x0: std_logic_vector(31 downto 0);
|
816 |
|
|
signal from_register6_data_out_net: std_logic;
|
817 |
|
|
signal from_register6_data_out_net_x0: std_logic;
|
818 |
|
|
signal from_register7_data_out_net: std_logic_vector(31 downto 0);
|
819 |
|
|
signal from_register7_data_out_net_x0: std_logic_vector(31 downto 0);
|
820 |
|
|
signal from_register8_data_out_net: std_logic_vector(31 downto 0);
|
821 |
|
|
signal from_register8_data_out_net_x0: std_logic_vector(31 downto 0);
|
822 |
|
|
signal from_register9_data_out_net: std_logic;
|
823 |
|
|
signal from_register9_data_out_net_x0: std_logic;
|
824 |
|
|
signal persistentdff_inst_q: std_logic;
|
825 |
|
|
attribute syn_keep: boolean;
|
826 |
|
|
attribute syn_keep of persistentdff_inst_q: signal is true;
|
827 |
|
|
attribute keep: boolean;
|
828 |
|
|
attribute keep of persistentdff_inst_q: signal is true;
|
829 |
|
|
attribute preserve_signal: boolean;
|
830 |
|
|
attribute preserve_signal of persistentdff_inst_q: signal is true;
|
831 |
|
|
signal reg01_td_net: std_logic_vector(31 downto 0);
|
832 |
|
|
signal reg01_td_net_x0: std_logic_vector(31 downto 0);
|
833 |
|
|
signal reg01_tv_net: std_logic;
|
834 |
|
|
signal reg01_tv_net_x0: std_logic;
|
835 |
|
|
signal reg02_td_net: std_logic_vector(31 downto 0);
|
836 |
|
|
signal reg02_td_net_x0: std_logic_vector(31 downto 0);
|
837 |
|
|
signal reg02_tv_net: std_logic;
|
838 |
|
|
signal reg02_tv_net_x0: std_logic;
|
839 |
|
|
signal reg03_td_net: std_logic_vector(31 downto 0);
|
840 |
|
|
signal reg03_td_net_x0: std_logic_vector(31 downto 0);
|
841 |
|
|
signal reg03_tv_net: std_logic;
|
842 |
|
|
signal reg03_tv_net_x0: std_logic;
|
843 |
|
|
signal reg04_td_net: std_logic_vector(31 downto 0);
|
844 |
|
|
signal reg04_td_net_x0: std_logic_vector(31 downto 0);
|
845 |
|
|
signal reg04_tv_net: std_logic;
|
846 |
|
|
signal reg04_tv_net_x0: std_logic;
|
847 |
|
|
signal reg05_td_net: std_logic_vector(31 downto 0);
|
848 |
|
|
signal reg05_td_net_x0: std_logic_vector(31 downto 0);
|
849 |
|
|
signal reg05_tv_net: std_logic;
|
850 |
|
|
signal reg05_tv_net_x0: std_logic;
|
851 |
|
|
signal reg06_td_net: std_logic_vector(31 downto 0);
|
852 |
|
|
signal reg06_td_net_x0: std_logic_vector(31 downto 0);
|
853 |
|
|
signal reg06_tv_net: std_logic;
|
854 |
|
|
signal reg06_tv_net_x0: std_logic;
|
855 |
|
|
signal reg07_td_net: std_logic_vector(31 downto 0);
|
856 |
|
|
signal reg07_td_net_x0: std_logic_vector(31 downto 0);
|
857 |
|
|
signal reg07_tv_net: std_logic;
|
858 |
|
|
signal reg07_tv_net_x0: std_logic;
|
859 |
|
|
signal reg08_td_net: std_logic_vector(31 downto 0);
|
860 |
|
|
signal reg08_td_net_x0: std_logic_vector(31 downto 0);
|
861 |
|
|
signal reg08_tv_net: std_logic;
|
862 |
|
|
signal reg08_tv_net_x0: std_logic;
|
863 |
|
|
signal reg09_td_net: std_logic_vector(31 downto 0);
|
864 |
|
|
signal reg09_td_net_x0: std_logic_vector(31 downto 0);
|
865 |
|
|
signal reg09_tv_net: std_logic;
|
866 |
|
|
signal reg09_tv_net_x0: std_logic;
|
867 |
|
|
signal reg10_td_net: std_logic_vector(31 downto 0);
|
868 |
|
|
signal reg10_td_net_x0: std_logic_vector(31 downto 0);
|
869 |
|
|
signal reg10_tv_net: std_logic;
|
870 |
|
|
signal reg10_tv_net_x0: std_logic;
|
871 |
|
|
signal reg11_td_net: std_logic_vector(31 downto 0);
|
872 |
|
|
signal reg11_td_net_x0: std_logic_vector(31 downto 0);
|
873 |
|
|
signal reg11_tv_net: std_logic;
|
874 |
|
|
signal reg11_tv_net_x0: std_logic;
|
875 |
|
|
signal reg12_td_net: std_logic_vector(31 downto 0);
|
876 |
|
|
signal reg12_td_net_x0: std_logic_vector(31 downto 0);
|
877 |
|
|
signal reg12_tv_net: std_logic;
|
878 |
|
|
signal reg12_tv_net_x0: std_logic;
|
879 |
|
|
signal reg13_td_net: std_logic_vector(31 downto 0);
|
880 |
|
|
signal reg13_td_net_x0: std_logic_vector(31 downto 0);
|
881 |
|
|
signal reg13_tv_net: std_logic;
|
882 |
|
|
signal reg13_tv_net_x0: std_logic;
|
883 |
|
|
signal reg14_td_net: std_logic_vector(31 downto 0);
|
884 |
|
|
signal reg14_td_net_x0: std_logic_vector(31 downto 0);
|
885 |
|
|
signal reg14_tv_net: std_logic;
|
886 |
|
|
signal reg14_tv_net_x0: std_logic;
|
887 |
|
|
signal to_register10_dout_net: std_logic;
|
888 |
|
|
signal to_register11_dout_net: std_logic_vector(31 downto 0);
|
889 |
|
|
signal to_register12_dout_net: std_logic;
|
890 |
|
|
signal to_register13_dout_net: std_logic_vector(31 downto 0);
|
891 |
|
|
signal to_register14_dout_net: std_logic;
|
892 |
|
|
signal to_register15_dout_net: std_logic_vector(31 downto 0);
|
893 |
|
|
signal to_register16_dout_net: std_logic;
|
894 |
|
|
signal to_register17_dout_net: std_logic_vector(31 downto 0);
|
895 |
|
|
signal to_register18_dout_net: std_logic;
|
896 |
|
|
signal to_register19_dout_net: std_logic;
|
897 |
|
|
signal to_register1_dout_net: std_logic_vector(31 downto 0);
|
898 |
|
|
signal to_register20_dout_net: std_logic_vector(31 downto 0);
|
899 |
|
|
signal to_register21_dout_net: std_logic;
|
900 |
|
|
signal to_register22_dout_net: std_logic_vector(31 downto 0);
|
901 |
|
|
signal to_register23_dout_net: std_logic;
|
902 |
|
|
signal to_register24_dout_net: std_logic_vector(31 downto 0);
|
903 |
|
|
signal to_register25_dout_net: std_logic;
|
904 |
|
|
signal to_register26_dout_net: std_logic_vector(31 downto 0);
|
905 |
|
|
signal to_register27_dout_net: std_logic;
|
906 |
|
|
signal to_register28_dout_net: std_logic_vector(31 downto 0);
|
907 |
|
|
signal to_register29_dout_net: std_logic;
|
908 |
|
|
signal to_register2_dout_net: std_logic_vector(31 downto 0);
|
909 |
|
|
signal to_register30_dout_net: std_logic_vector(31 downto 0);
|
910 |
|
|
signal to_register31_dout_net: std_logic;
|
911 |
|
|
signal to_register32_dout_net: std_logic_vector(31 downto 0);
|
912 |
|
|
signal to_register33_dout_net: std_logic;
|
913 |
|
|
signal to_register34_dout_net: std_logic_vector(31 downto 0);
|
914 |
|
|
signal to_register3_dout_net: std_logic;
|
915 |
|
|
signal to_register4_dout_net: std_logic;
|
916 |
|
|
signal to_register5_dout_net: std_logic_vector(31 downto 0);
|
917 |
|
|
signal to_register6_dout_net: std_logic_vector(31 downto 0);
|
918 |
|
|
signal to_register7_dout_net: std_logic_vector(31 downto 0);
|
919 |
|
|
signal to_register8_dout_net: std_logic;
|
920 |
|
|
signal to_register9_dout_net: std_logic_vector(31 downto 0);
|
921 |
|
|
|
922 |
|
|
begin
|
923 |
|
|
clkNet <= clk;
|
924 |
|
|
debug_in_1i_net <= debug_in_1i;
|
925 |
|
|
debug_in_2i_net <= debug_in_2i;
|
926 |
|
|
debug_in_3i_net <= debug_in_3i;
|
927 |
|
|
debug_in_4i_net <= debug_in_4i;
|
928 |
|
|
dma_host2board_busy_net <= dma_host2board_busy;
|
929 |
|
|
dma_host2board_done_net <= dma_host2board_done;
|
930 |
|
|
from_register10_data_out_net <= from_register10_data_out;
|
931 |
|
|
from_register11_data_out_net <= from_register11_data_out;
|
932 |
|
|
from_register12_data_out_net <= from_register12_data_out(0);
|
933 |
|
|
from_register13_data_out_net <= from_register13_data_out;
|
934 |
|
|
from_register14_data_out_net <= from_register14_data_out(0);
|
935 |
|
|
from_register15_data_out_net <= from_register15_data_out;
|
936 |
|
|
from_register16_data_out_net <= from_register16_data_out(0);
|
937 |
|
|
from_register17_data_out_net <= from_register17_data_out;
|
938 |
|
|
from_register18_data_out_net <= from_register18_data_out(0);
|
939 |
|
|
from_register19_data_out_net <= from_register19_data_out;
|
940 |
|
|
from_register1_data_out_net <= from_register1_data_out(0);
|
941 |
|
|
from_register20_data_out_net <= from_register20_data_out(0);
|
942 |
|
|
from_register21_data_out_net <= from_register21_data_out;
|
943 |
|
|
from_register22_data_out_net <= from_register22_data_out(0);
|
944 |
|
|
from_register23_data_out_net <= from_register23_data_out;
|
945 |
|
|
from_register24_data_out_net <= from_register24_data_out(0);
|
946 |
|
|
from_register25_data_out_net <= from_register25_data_out;
|
947 |
|
|
from_register26_data_out_net <= from_register26_data_out(0);
|
948 |
|
|
from_register27_data_out_net <= from_register27_data_out;
|
949 |
|
|
from_register28_data_out_net <= from_register28_data_out(0);
|
950 |
|
|
from_register2_data_out_net <= from_register2_data_out(0);
|
951 |
|
|
from_register3_data_out_net <= from_register3_data_out;
|
952 |
|
|
from_register4_data_out_net <= from_register4_data_out(0);
|
953 |
|
|
from_register5_data_out_net <= from_register5_data_out;
|
954 |
|
|
from_register6_data_out_net <= from_register6_data_out(0);
|
955 |
|
|
from_register7_data_out_net <= from_register7_data_out;
|
956 |
|
|
from_register8_data_out_net <= from_register8_data_out;
|
957 |
|
|
from_register9_data_out_net <= from_register9_data_out(0);
|
958 |
|
|
reg01_td_net <= reg01_td;
|
959 |
|
|
reg01_tv_net <= reg01_tv;
|
960 |
|
|
reg02_td_net <= reg02_td;
|
961 |
|
|
reg02_tv_net <= reg02_tv;
|
962 |
|
|
reg03_td_net <= reg03_td;
|
963 |
|
|
reg03_tv_net <= reg03_tv;
|
964 |
|
|
reg04_td_net <= reg04_td;
|
965 |
|
|
reg04_tv_net <= reg04_tv;
|
966 |
|
|
reg05_td_net <= reg05_td;
|
967 |
|
|
reg05_tv_net <= reg05_tv;
|
968 |
|
|
reg06_td_net <= reg06_td;
|
969 |
|
|
reg06_tv_net <= reg06_tv;
|
970 |
|
|
reg07_td_net <= reg07_td;
|
971 |
|
|
reg07_tv_net <= reg07_tv;
|
972 |
|
|
reg08_td_net <= reg08_td;
|
973 |
|
|
reg08_tv_net <= reg08_tv;
|
974 |
|
|
reg09_td_net <= reg09_td;
|
975 |
|
|
reg09_tv_net <= reg09_tv;
|
976 |
|
|
reg10_td_net <= reg10_td;
|
977 |
|
|
reg10_tv_net <= reg10_tv;
|
978 |
|
|
reg11_td_net <= reg11_td;
|
979 |
|
|
reg11_tv_net <= reg11_tv;
|
980 |
|
|
reg12_td_net <= reg12_td;
|
981 |
|
|
reg12_tv_net <= reg12_tv;
|
982 |
|
|
reg13_td_net <= reg13_td;
|
983 |
|
|
reg13_tv_net <= reg13_tv;
|
984 |
|
|
reg14_td_net <= reg14_td;
|
985 |
|
|
reg14_tv_net <= reg14_tv;
|
986 |
|
|
to_register10_dout_net <= to_register10_dout(0);
|
987 |
|
|
to_register11_dout_net <= to_register11_dout;
|
988 |
|
|
to_register12_dout_net <= to_register12_dout(0);
|
989 |
|
|
to_register13_dout_net <= to_register13_dout;
|
990 |
|
|
to_register14_dout_net <= to_register14_dout(0);
|
991 |
|
|
to_register15_dout_net <= to_register15_dout;
|
992 |
|
|
to_register16_dout_net <= to_register16_dout(0);
|
993 |
|
|
to_register17_dout_net <= to_register17_dout;
|
994 |
|
|
to_register18_dout_net <= to_register18_dout(0);
|
995 |
|
|
to_register19_dout_net <= to_register19_dout(0);
|
996 |
|
|
to_register1_dout_net <= to_register1_dout;
|
997 |
|
|
to_register20_dout_net <= to_register20_dout;
|
998 |
|
|
to_register21_dout_net <= to_register21_dout(0);
|
999 |
|
|
to_register22_dout_net <= to_register22_dout;
|
1000 |
|
|
to_register23_dout_net <= to_register23_dout(0);
|
1001 |
|
|
to_register24_dout_net <= to_register24_dout;
|
1002 |
|
|
to_register25_dout_net <= to_register25_dout(0);
|
1003 |
|
|
to_register26_dout_net <= to_register26_dout;
|
1004 |
|
|
to_register27_dout_net <= to_register27_dout(0);
|
1005 |
|
|
to_register28_dout_net <= to_register28_dout;
|
1006 |
|
|
to_register29_dout_net <= to_register29_dout(0);
|
1007 |
|
|
to_register2_dout_net <= to_register2_dout;
|
1008 |
|
|
to_register30_dout_net <= to_register30_dout;
|
1009 |
|
|
to_register31_dout_net <= to_register31_dout(0);
|
1010 |
|
|
to_register32_dout_net <= to_register32_dout;
|
1011 |
|
|
to_register33_dout_net <= to_register33_dout(0);
|
1012 |
|
|
to_register34_dout_net <= to_register34_dout;
|
1013 |
|
|
to_register3_dout_net <= to_register3_dout(0);
|
1014 |
|
|
to_register4_dout_net <= to_register4_dout(0);
|
1015 |
|
|
to_register5_dout_net <= to_register5_dout;
|
1016 |
|
|
to_register6_dout_net <= to_register6_dout;
|
1017 |
|
|
to_register7_dout_net <= to_register7_dout;
|
1018 |
|
|
to_register8_dout_net <= to_register8_dout(0);
|
1019 |
|
|
to_register9_dout_net <= to_register9_dout;
|
1020 |
|
|
reg01_rd <= from_register3_data_out_net_x0;
|
1021 |
|
|
reg01_rv <= from_register1_data_out_net_x0;
|
1022 |
|
|
reg02_rd <= from_register5_data_out_net_x0;
|
1023 |
|
|
reg02_rv <= from_register2_data_out_net_x0;
|
1024 |
|
|
reg03_rd <= from_register7_data_out_net_x0;
|
1025 |
|
|
reg03_rv <= from_register6_data_out_net_x0;
|
1026 |
|
|
reg04_rd <= from_register8_data_out_net_x0;
|
1027 |
|
|
reg04_rv <= from_register4_data_out_net_x0;
|
1028 |
|
|
reg05_rd <= from_register10_data_out_net_x0;
|
1029 |
|
|
reg05_rv <= from_register9_data_out_net_x0;
|
1030 |
|
|
reg06_rd <= from_register11_data_out_net_x0;
|
1031 |
|
|
reg06_rv <= from_register12_data_out_net_x0;
|
1032 |
|
|
reg07_rd <= from_register13_data_out_net_x0;
|
1033 |
|
|
reg07_rv <= from_register14_data_out_net_x0;
|
1034 |
|
|
reg08_rd <= from_register15_data_out_net_x0;
|
1035 |
|
|
reg08_rv <= from_register16_data_out_net_x0;
|
1036 |
|
|
reg09_rd <= from_register17_data_out_net_x0;
|
1037 |
|
|
reg09_rv <= from_register18_data_out_net_x0;
|
1038 |
|
|
reg10_rd <= from_register19_data_out_net_x0;
|
1039 |
|
|
reg10_rv <= from_register20_data_out_net_x0;
|
1040 |
|
|
reg11_rd <= from_register21_data_out_net_x0;
|
1041 |
|
|
reg11_rv <= from_register22_data_out_net_x0;
|
1042 |
|
|
reg12_rd <= from_register23_data_out_net_x0;
|
1043 |
|
|
reg12_rv <= from_register24_data_out_net_x0;
|
1044 |
|
|
reg13_rd <= from_register25_data_out_net_x0;
|
1045 |
|
|
reg13_rv <= from_register26_data_out_net_x0;
|
1046 |
|
|
reg14_rd <= from_register27_data_out_net_x0;
|
1047 |
|
|
reg14_rv <= from_register28_data_out_net_x0;
|
1048 |
|
|
to_register10_ce <= ce_1_sg;
|
1049 |
|
|
to_register10_clk <= clk_1_sg;
|
1050 |
|
|
to_register10_clr <= '0';
|
1051 |
|
|
to_register10_data_in(0) <= reg04_tv_net_x0;
|
1052 |
|
|
to_register10_en(0) <= constant5_op_net_x1;
|
1053 |
|
|
to_register11_ce <= ce_1_sg;
|
1054 |
|
|
to_register11_clk <= clk_1_sg;
|
1055 |
|
|
to_register11_clr <= '0';
|
1056 |
|
|
to_register11_data_in <= reg04_td_net_x0;
|
1057 |
|
|
to_register11_en(0) <= constant5_op_net_x2;
|
1058 |
|
|
to_register12_ce <= ce_1_sg;
|
1059 |
|
|
to_register12_clk <= clk_1_sg;
|
1060 |
|
|
to_register12_clr <= '0';
|
1061 |
|
|
to_register12_data_in(0) <= reg05_tv_net_x0;
|
1062 |
|
|
to_register12_en(0) <= constant5_op_net_x3;
|
1063 |
|
|
to_register13_ce <= ce_1_sg;
|
1064 |
|
|
to_register13_clk <= clk_1_sg;
|
1065 |
|
|
to_register13_clr <= '0';
|
1066 |
|
|
to_register13_data_in <= reg05_td_net_x0;
|
1067 |
|
|
to_register13_en(0) <= constant5_op_net_x4;
|
1068 |
|
|
to_register14_ce <= ce_1_sg;
|
1069 |
|
|
to_register14_clk <= clk_1_sg;
|
1070 |
|
|
to_register14_clr <= '0';
|
1071 |
|
|
to_register14_data_in(0) <= reg06_tv_net_x0;
|
1072 |
|
|
to_register14_en(0) <= constant5_op_net_x5;
|
1073 |
|
|
to_register15_ce <= ce_1_sg;
|
1074 |
|
|
to_register15_clk <= clk_1_sg;
|
1075 |
|
|
to_register15_clr <= '0';
|
1076 |
|
|
to_register15_data_in <= reg06_td_net_x0;
|
1077 |
|
|
to_register15_en(0) <= constant5_op_net_x6;
|
1078 |
|
|
to_register16_ce <= ce_1_sg;
|
1079 |
|
|
to_register16_clk <= clk_1_sg;
|
1080 |
|
|
to_register16_clr <= '0';
|
1081 |
|
|
to_register16_data_in(0) <= reg07_tv_net_x0;
|
1082 |
|
|
to_register16_en(0) <= constant5_op_net_x7;
|
1083 |
|
|
to_register17_ce <= ce_1_sg;
|
1084 |
|
|
to_register17_clk <= clk_1_sg;
|
1085 |
|
|
to_register17_clr <= '0';
|
1086 |
|
|
to_register17_data_in <= reg07_td_net_x0;
|
1087 |
|
|
to_register17_en(0) <= constant5_op_net_x8;
|
1088 |
|
|
to_register18_ce <= ce_1_sg;
|
1089 |
|
|
to_register18_clk <= clk_1_sg;
|
1090 |
|
|
to_register18_clr <= '0';
|
1091 |
|
|
to_register18_data_in(0) <= dma_host2board_busy_net_x0;
|
1092 |
|
|
to_register18_en(0) <= constant5_op_net_x9;
|
1093 |
|
|
to_register19_ce <= ce_1_sg;
|
1094 |
|
|
to_register19_clk <= clk_1_sg;
|
1095 |
|
|
to_register19_clr <= '0';
|
1096 |
|
|
to_register19_data_in(0) <= dma_host2board_done_net_x0;
|
1097 |
|
|
to_register19_en(0) <= constant5_op_net_x10;
|
1098 |
|
|
to_register1_ce <= ce_1_sg;
|
1099 |
|
|
to_register1_clk <= clk_1_sg;
|
1100 |
|
|
to_register1_clr <= '0';
|
1101 |
|
|
to_register1_data_in <= debug_in_2i_net_x0;
|
1102 |
|
|
to_register1_en(0) <= constant5_op_net_x0;
|
1103 |
|
|
to_register20_ce <= ce_1_sg;
|
1104 |
|
|
to_register20_clk <= clk_1_sg;
|
1105 |
|
|
to_register20_clr <= '0';
|
1106 |
|
|
to_register20_data_in <= debug_in_4i_net_x0;
|
1107 |
|
|
to_register20_en(0) <= constant5_op_net_x12;
|
1108 |
|
|
to_register21_ce <= ce_1_sg;
|
1109 |
|
|
to_register21_clk <= clk_1_sg;
|
1110 |
|
|
to_register21_clr <= '0';
|
1111 |
|
|
to_register21_data_in(0) <= reg09_tv_net_x0;
|
1112 |
|
|
to_register21_en(0) <= constant1_op_net_x0;
|
1113 |
|
|
to_register22_ce <= ce_1_sg;
|
1114 |
|
|
to_register22_clk <= clk_1_sg;
|
1115 |
|
|
to_register22_clr <= '0';
|
1116 |
|
|
to_register22_data_in <= reg09_td_net_x0;
|
1117 |
|
|
to_register22_en(0) <= constant1_op_net_x1;
|
1118 |
|
|
to_register23_ce <= ce_1_sg;
|
1119 |
|
|
to_register23_clk <= clk_1_sg;
|
1120 |
|
|
to_register23_clr <= '0';
|
1121 |
|
|
to_register23_data_in(0) <= reg10_tv_net_x0;
|
1122 |
|
|
to_register23_en(0) <= constant1_op_net_x2;
|
1123 |
|
|
to_register24_ce <= ce_1_sg;
|
1124 |
|
|
to_register24_clk <= clk_1_sg;
|
1125 |
|
|
to_register24_clr <= '0';
|
1126 |
|
|
to_register24_data_in <= reg10_td_net_x0;
|
1127 |
|
|
to_register24_en(0) <= constant1_op_net_x3;
|
1128 |
|
|
to_register25_ce <= ce_1_sg;
|
1129 |
|
|
to_register25_clk <= clk_1_sg;
|
1130 |
|
|
to_register25_clr <= '0';
|
1131 |
|
|
to_register25_data_in(0) <= reg08_tv_net_x0;
|
1132 |
|
|
to_register25_en(0) <= constant1_op_net_x4;
|
1133 |
|
|
to_register26_ce <= ce_1_sg;
|
1134 |
|
|
to_register26_clk <= clk_1_sg;
|
1135 |
|
|
to_register26_clr <= '0';
|
1136 |
|
|
to_register26_data_in <= reg08_td_net_x0;
|
1137 |
|
|
to_register26_en(0) <= constant1_op_net_x5;
|
1138 |
|
|
to_register27_ce <= ce_1_sg;
|
1139 |
|
|
to_register27_clk <= clk_1_sg;
|
1140 |
|
|
to_register27_clr <= '0';
|
1141 |
|
|
to_register27_data_in(0) <= reg11_tv_net_x0;
|
1142 |
|
|
to_register27_en(0) <= constant1_op_net_x6;
|
1143 |
|
|
to_register28_ce <= ce_1_sg;
|
1144 |
|
|
to_register28_clk <= clk_1_sg;
|
1145 |
|
|
to_register28_clr <= '0';
|
1146 |
|
|
to_register28_data_in <= reg11_td_net_x0;
|
1147 |
|
|
to_register28_en(0) <= constant1_op_net_x7;
|
1148 |
|
|
to_register29_ce <= ce_1_sg;
|
1149 |
|
|
to_register29_clk <= clk_1_sg;
|
1150 |
|
|
to_register29_clr <= '0';
|
1151 |
|
|
to_register29_data_in(0) <= reg12_tv_net_x0;
|
1152 |
|
|
to_register29_en(0) <= constant1_op_net_x8;
|
1153 |
|
|
to_register2_ce <= ce_1_sg;
|
1154 |
|
|
to_register2_clk <= clk_1_sg;
|
1155 |
|
|
to_register2_clr <= '0';
|
1156 |
|
|
to_register2_data_in <= debug_in_3i_net_x0;
|
1157 |
|
|
to_register2_en(0) <= constant5_op_net_x11;
|
1158 |
|
|
to_register30_ce <= ce_1_sg;
|
1159 |
|
|
to_register30_clk <= clk_1_sg;
|
1160 |
|
|
to_register30_clr <= '0';
|
1161 |
|
|
to_register30_data_in <= reg12_td_net_x0;
|
1162 |
|
|
to_register30_en(0) <= constant1_op_net_x9;
|
1163 |
|
|
to_register31_ce <= ce_1_sg;
|
1164 |
|
|
to_register31_clk <= clk_1_sg;
|
1165 |
|
|
to_register31_clr <= '0';
|
1166 |
|
|
to_register31_data_in(0) <= reg13_tv_net_x0;
|
1167 |
|
|
to_register31_en(0) <= constant1_op_net_x10;
|
1168 |
|
|
to_register32_ce <= ce_1_sg;
|
1169 |
|
|
to_register32_clk <= clk_1_sg;
|
1170 |
|
|
to_register32_clr <= '0';
|
1171 |
|
|
to_register32_data_in <= reg13_td_net_x0;
|
1172 |
|
|
to_register32_en(0) <= constant1_op_net_x11;
|
1173 |
|
|
to_register33_ce <= ce_1_sg;
|
1174 |
|
|
to_register33_clk <= clk_1_sg;
|
1175 |
|
|
to_register33_clr <= '0';
|
1176 |
|
|
to_register33_data_in(0) <= reg14_tv_net_x0;
|
1177 |
|
|
to_register33_en(0) <= constant1_op_net_x12;
|
1178 |
|
|
to_register34_ce <= ce_1_sg;
|
1179 |
|
|
to_register34_clk <= clk_1_sg;
|
1180 |
|
|
to_register34_clr <= '0';
|
1181 |
|
|
to_register34_data_in <= reg14_td_net_x0;
|
1182 |
|
|
to_register34_en(0) <= constant1_op_net_x13;
|
1183 |
|
|
to_register3_ce <= ce_1_sg;
|
1184 |
|
|
to_register3_clk <= clk_1_sg;
|
1185 |
|
|
to_register3_clr <= '0';
|
1186 |
|
|
to_register3_data_in(0) <= reg01_tv_net_x0;
|
1187 |
|
|
to_register3_en(0) <= constant5_op_net_x13;
|
1188 |
|
|
to_register4_ce <= ce_1_sg;
|
1189 |
|
|
to_register4_clk <= clk_1_sg;
|
1190 |
|
|
to_register4_clr <= '0';
|
1191 |
|
|
to_register4_data_in(0) <= reg02_tv_net_x0;
|
1192 |
|
|
to_register4_en(0) <= constant5_op_net_x14;
|
1193 |
|
|
to_register5_ce <= ce_1_sg;
|
1194 |
|
|
to_register5_clk <= clk_1_sg;
|
1195 |
|
|
to_register5_clr <= '0';
|
1196 |
|
|
to_register5_data_in <= reg02_td_net_x0;
|
1197 |
|
|
to_register5_en(0) <= constant5_op_net_x15;
|
1198 |
|
|
to_register6_ce <= ce_1_sg;
|
1199 |
|
|
to_register6_clk <= clk_1_sg;
|
1200 |
|
|
to_register6_clr <= '0';
|
1201 |
|
|
to_register6_data_in <= debug_in_1i_net_x0;
|
1202 |
|
|
to_register6_en(0) <= constant5_op_net_x16;
|
1203 |
|
|
to_register7_ce <= ce_1_sg;
|
1204 |
|
|
to_register7_clk <= clk_1_sg;
|
1205 |
|
|
to_register7_clr <= '0';
|
1206 |
|
|
to_register7_data_in <= reg01_td_net_x0;
|
1207 |
|
|
to_register7_en(0) <= constant5_op_net_x17;
|
1208 |
|
|
to_register8_ce <= ce_1_sg;
|
1209 |
|
|
to_register8_clk <= clk_1_sg;
|
1210 |
|
|
to_register8_clr <= '0';
|
1211 |
|
|
to_register8_data_in(0) <= reg03_tv_net_x0;
|
1212 |
|
|
to_register8_en(0) <= constant5_op_net_x18;
|
1213 |
|
|
to_register9_ce <= ce_1_sg;
|
1214 |
|
|
to_register9_clk <= clk_1_sg;
|
1215 |
|
|
to_register9_clr <= '0';
|
1216 |
|
|
to_register9_data_in <= reg03_td_net_x0;
|
1217 |
|
|
to_register9_en(0) <= constant5_op_net_x19;
|
1218 |
|
|
|
1219 |
|
|
default_clock_driver_x0: entity work.default_clock_driver
|
1220 |
|
|
port map (
|
1221 |
|
|
sysce => '1',
|
1222 |
|
|
sysce_clr => '0',
|
1223 |
|
|
sysclk => clkNet,
|
1224 |
|
|
ce_1 => ce_1_sg,
|
1225 |
|
|
clk_1 => clk_1_sg
|
1226 |
|
|
);
|
1227 |
|
|
|
1228 |
|
|
inout_logic_x0: entity work.inout_logic
|
1229 |
|
|
port map (
|
1230 |
|
|
data_out => from_register1_data_out_net,
|
1231 |
|
|
data_out_x0 => from_register10_data_out_net,
|
1232 |
|
|
data_out_x1 => from_register11_data_out_net,
|
1233 |
|
|
data_out_x10 => from_register2_data_out_net,
|
1234 |
|
|
data_out_x11 => from_register20_data_out_net,
|
1235 |
|
|
data_out_x12 => from_register21_data_out_net,
|
1236 |
|
|
data_out_x13 => from_register22_data_out_net,
|
1237 |
|
|
data_out_x14 => from_register23_data_out_net,
|
1238 |
|
|
data_out_x15 => from_register24_data_out_net,
|
1239 |
|
|
data_out_x16 => from_register25_data_out_net,
|
1240 |
|
|
data_out_x17 => from_register26_data_out_net,
|
1241 |
|
|
data_out_x18 => from_register27_data_out_net,
|
1242 |
|
|
data_out_x19 => from_register28_data_out_net,
|
1243 |
|
|
data_out_x2 => from_register12_data_out_net,
|
1244 |
|
|
data_out_x20 => from_register3_data_out_net,
|
1245 |
|
|
data_out_x21 => from_register4_data_out_net,
|
1246 |
|
|
data_out_x22 => from_register5_data_out_net,
|
1247 |
|
|
data_out_x23 => from_register6_data_out_net,
|
1248 |
|
|
data_out_x24 => from_register7_data_out_net,
|
1249 |
|
|
data_out_x25 => from_register8_data_out_net,
|
1250 |
|
|
data_out_x26 => from_register9_data_out_net,
|
1251 |
|
|
data_out_x3 => from_register13_data_out_net,
|
1252 |
|
|
data_out_x4 => from_register14_data_out_net,
|
1253 |
|
|
data_out_x5 => from_register15_data_out_net,
|
1254 |
|
|
data_out_x6 => from_register16_data_out_net,
|
1255 |
|
|
data_out_x7 => from_register17_data_out_net,
|
1256 |
|
|
data_out_x8 => from_register18_data_out_net,
|
1257 |
|
|
data_out_x9 => from_register19_data_out_net,
|
1258 |
|
|
debug_in_1i => debug_in_1i_net,
|
1259 |
|
|
debug_in_2i => debug_in_2i_net,
|
1260 |
|
|
debug_in_3i => debug_in_3i_net,
|
1261 |
|
|
debug_in_4i => debug_in_4i_net,
|
1262 |
|
|
dma_host2board_busy => dma_host2board_busy_net,
|
1263 |
|
|
dma_host2board_done => dma_host2board_done_net,
|
1264 |
|
|
reg01_td => reg01_td_net,
|
1265 |
|
|
reg01_tv => reg01_tv_net,
|
1266 |
|
|
reg02_td => reg02_td_net,
|
1267 |
|
|
reg02_tv => reg02_tv_net,
|
1268 |
|
|
reg03_td => reg03_td_net,
|
1269 |
|
|
reg03_tv => reg03_tv_net,
|
1270 |
|
|
reg04_td => reg04_td_net,
|
1271 |
|
|
reg04_tv => reg04_tv_net,
|
1272 |
|
|
reg05_td => reg05_td_net,
|
1273 |
|
|
reg05_tv => reg05_tv_net,
|
1274 |
|
|
reg06_td => reg06_td_net,
|
1275 |
|
|
reg06_tv => reg06_tv_net,
|
1276 |
|
|
reg07_td => reg07_td_net,
|
1277 |
|
|
reg07_tv => reg07_tv_net,
|
1278 |
|
|
reg08_td => reg08_td_net,
|
1279 |
|
|
reg08_tv => reg08_tv_net,
|
1280 |
|
|
reg09_td => reg09_td_net,
|
1281 |
|
|
reg09_tv => reg09_tv_net,
|
1282 |
|
|
reg10_td => reg10_td_net,
|
1283 |
|
|
reg10_tv => reg10_tv_net,
|
1284 |
|
|
reg11_td => reg11_td_net,
|
1285 |
|
|
reg11_tv => reg11_tv_net,
|
1286 |
|
|
reg12_td => reg12_td_net,
|
1287 |
|
|
reg12_tv => reg12_tv_net,
|
1288 |
|
|
reg13_td => reg13_td_net,
|
1289 |
|
|
reg13_tv => reg13_tv_net,
|
1290 |
|
|
reg14_td => reg14_td_net,
|
1291 |
|
|
reg14_tv => reg14_tv_net,
|
1292 |
|
|
data_in => debug_in_2i_net_x0,
|
1293 |
|
|
data_in_x0 => reg04_tv_net_x0,
|
1294 |
|
|
data_in_x1 => reg04_td_net_x0,
|
1295 |
|
|
data_in_x10 => debug_in_3i_net_x0,
|
1296 |
|
|
data_in_x11 => debug_in_4i_net_x0,
|
1297 |
|
|
data_in_x12 => reg09_tv_net_x0,
|
1298 |
|
|
data_in_x13 => reg09_td_net_x0,
|
1299 |
|
|
data_in_x14 => reg10_tv_net_x0,
|
1300 |
|
|
data_in_x15 => reg10_td_net_x0,
|
1301 |
|
|
data_in_x16 => reg08_tv_net_x0,
|
1302 |
|
|
data_in_x17 => reg08_td_net_x0,
|
1303 |
|
|
data_in_x18 => reg11_tv_net_x0,
|
1304 |
|
|
data_in_x19 => reg11_td_net_x0,
|
1305 |
|
|
data_in_x2 => reg05_tv_net_x0,
|
1306 |
|
|
data_in_x20 => reg12_tv_net_x0,
|
1307 |
|
|
data_in_x21 => reg01_tv_net_x0,
|
1308 |
|
|
data_in_x22 => reg12_td_net_x0,
|
1309 |
|
|
data_in_x23 => reg13_tv_net_x0,
|
1310 |
|
|
data_in_x24 => reg13_td_net_x0,
|
1311 |
|
|
data_in_x25 => reg14_tv_net_x0,
|
1312 |
|
|
data_in_x26 => reg14_td_net_x0,
|
1313 |
|
|
data_in_x27 => reg02_tv_net_x0,
|
1314 |
|
|
data_in_x28 => reg02_td_net_x0,
|
1315 |
|
|
data_in_x29 => debug_in_1i_net_x0,
|
1316 |
|
|
data_in_x3 => reg05_td_net_x0,
|
1317 |
|
|
data_in_x30 => reg01_td_net_x0,
|
1318 |
|
|
data_in_x31 => reg03_tv_net_x0,
|
1319 |
|
|
data_in_x32 => reg03_td_net_x0,
|
1320 |
|
|
data_in_x4 => reg06_tv_net_x0,
|
1321 |
|
|
data_in_x5 => reg06_td_net_x0,
|
1322 |
|
|
data_in_x6 => reg07_tv_net_x0,
|
1323 |
|
|
data_in_x7 => reg07_td_net_x0,
|
1324 |
|
|
data_in_x8 => dma_host2board_busy_net_x0,
|
1325 |
|
|
data_in_x9 => dma_host2board_done_net_x0,
|
1326 |
|
|
en => constant5_op_net_x0,
|
1327 |
|
|
en_x0 => constant5_op_net_x1,
|
1328 |
|
|
en_x1 => constant5_op_net_x2,
|
1329 |
|
|
en_x10 => constant5_op_net_x11,
|
1330 |
|
|
en_x11 => constant5_op_net_x12,
|
1331 |
|
|
en_x12 => constant1_op_net_x0,
|
1332 |
|
|
en_x13 => constant1_op_net_x1,
|
1333 |
|
|
en_x14 => constant1_op_net_x2,
|
1334 |
|
|
en_x15 => constant1_op_net_x3,
|
1335 |
|
|
en_x16 => constant1_op_net_x4,
|
1336 |
|
|
en_x17 => constant1_op_net_x5,
|
1337 |
|
|
en_x18 => constant1_op_net_x6,
|
1338 |
|
|
en_x19 => constant1_op_net_x7,
|
1339 |
|
|
en_x2 => constant5_op_net_x3,
|
1340 |
|
|
en_x20 => constant1_op_net_x8,
|
1341 |
|
|
en_x21 => constant5_op_net_x13,
|
1342 |
|
|
en_x22 => constant1_op_net_x9,
|
1343 |
|
|
en_x23 => constant1_op_net_x10,
|
1344 |
|
|
en_x24 => constant1_op_net_x11,
|
1345 |
|
|
en_x25 => constant1_op_net_x12,
|
1346 |
|
|
en_x26 => constant1_op_net_x13,
|
1347 |
|
|
en_x27 => constant5_op_net_x14,
|
1348 |
|
|
en_x28 => constant5_op_net_x15,
|
1349 |
|
|
en_x29 => constant5_op_net_x16,
|
1350 |
|
|
en_x3 => constant5_op_net_x4,
|
1351 |
|
|
en_x30 => constant5_op_net_x17,
|
1352 |
|
|
en_x31 => constant5_op_net_x18,
|
1353 |
|
|
en_x32 => constant5_op_net_x19,
|
1354 |
|
|
en_x4 => constant5_op_net_x5,
|
1355 |
|
|
en_x5 => constant5_op_net_x6,
|
1356 |
|
|
en_x6 => constant5_op_net_x7,
|
1357 |
|
|
en_x7 => constant5_op_net_x8,
|
1358 |
|
|
en_x8 => constant5_op_net_x9,
|
1359 |
|
|
en_x9 => constant5_op_net_x10,
|
1360 |
|
|
reg01_rd => from_register3_data_out_net_x0,
|
1361 |
|
|
reg01_rv => from_register1_data_out_net_x0,
|
1362 |
|
|
reg02_rd => from_register5_data_out_net_x0,
|
1363 |
|
|
reg02_rv => from_register2_data_out_net_x0,
|
1364 |
|
|
reg03_rd => from_register7_data_out_net_x0,
|
1365 |
|
|
reg03_rv => from_register6_data_out_net_x0,
|
1366 |
|
|
reg04_rd => from_register8_data_out_net_x0,
|
1367 |
|
|
reg04_rv => from_register4_data_out_net_x0,
|
1368 |
|
|
reg05_rd => from_register10_data_out_net_x0,
|
1369 |
|
|
reg05_rv => from_register9_data_out_net_x0,
|
1370 |
|
|
reg06_rd => from_register11_data_out_net_x0,
|
1371 |
|
|
reg06_rv => from_register12_data_out_net_x0,
|
1372 |
|
|
reg07_rd => from_register13_data_out_net_x0,
|
1373 |
|
|
reg07_rv => from_register14_data_out_net_x0,
|
1374 |
|
|
reg08_rd => from_register15_data_out_net_x0,
|
1375 |
|
|
reg08_rv => from_register16_data_out_net_x0,
|
1376 |
|
|
reg09_rd => from_register17_data_out_net_x0,
|
1377 |
|
|
reg09_rv => from_register18_data_out_net_x0,
|
1378 |
|
|
reg10_rd => from_register19_data_out_net_x0,
|
1379 |
|
|
reg10_rv => from_register20_data_out_net_x0,
|
1380 |
|
|
reg11_rd => from_register21_data_out_net_x0,
|
1381 |
|
|
reg11_rv => from_register22_data_out_net_x0,
|
1382 |
|
|
reg12_rd => from_register23_data_out_net_x0,
|
1383 |
|
|
reg12_rv => from_register24_data_out_net_x0,
|
1384 |
|
|
reg13_rd => from_register25_data_out_net_x0,
|
1385 |
|
|
reg13_rv => from_register26_data_out_net_x0,
|
1386 |
|
|
reg14_rd => from_register27_data_out_net_x0,
|
1387 |
|
|
reg14_rv => from_register28_data_out_net_x0
|
1388 |
|
|
);
|
1389 |
|
|
|
1390 |
|
|
persistentdff_inst: xlpersistentdff
|
1391 |
|
|
port map (
|
1392 |
|
|
clk => clkNet,
|
1393 |
|
|
d => persistentdff_inst_q,
|
1394 |
|
|
q => persistentdff_inst_q
|
1395 |
|
|
);
|
1396 |
|
|
|
1397 |
|
|
end structural;
|