OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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      'hdlType' => 'std_logic',
477 
      'width' => 1,
478 
    },
479 
    '.reg10_td' => {
480 
      'hdlType' => 'std_logic_vector(31 downto 0)',
481 
      'width' => 32,
482 
    },
483 
    '.reg10_tv' => {
484 
      'hdlType' => 'std_logic',
485 
      'width' => 1,
486 
    },
487 
    '.reg11_td' => {
488 
      'hdlType' => 'std_logic_vector(31 downto 0)',
489 
      'width' => 32,
490 
    },
491 
    '.reg11_tv' => {
492 
      'hdlType' => 'std_logic',
493 
      'width' => 1,
494 
    },
495 
    '.reg12_td' => {
496 
      'hdlType' => 'std_logic_vector(31 downto 0)',
497 
      'width' => 32,
498 
    },
499 
    '.reg12_tv' => {
500 
      'hdlType' => 'std_logic',
501 
      'width' => 1,
502 
    },
503 
    '.reg13_td' => {
504 
      'hdlType' => 'std_logic_vector(31 downto 0)',
505 
      'width' => 32,
506 
    },
507 
    '.reg13_tv' => {
508 
      'hdlType' => 'std_logic',
509 
      'width' => 1,
510 
    },
511 
    '.reg14_td' => {
512 
      'hdlType' => 'std_logic_vector(31 downto 0)',
513 
      'width' => 32,
514 
    },
515 
    '.reg14_tv' => {
516 
      'hdlType' => 'std_logic',
517 
      'width' => 1,
518 
    },
519 
    'from_register1.data_out' => {
520 
      'hdlType' => 'std_logic',
521 
      'width' => 1,
522 
    },
523 
    'from_register10.data_out' => {
524 
      'hdlType' => 'std_logic_vector(31 downto 0)',
525 
      'width' => 32,
526 
    },
527 
    'from_register11.data_out' => {
528 
      'hdlType' => 'std_logic_vector(31 downto 0)',
529 
      'width' => 32,
530 
    },
531 
    'from_register12.data_out' => {
532 
      'hdlType' => 'std_logic',
533 
      'width' => 1,
534 
    },
535 
    'from_register13.data_out' => {
536 
      'hdlType' => 'std_logic_vector(31 downto 0)',
537 
      'width' => 32,
538 
    },
539 
    'from_register14.data_out' => {
540 
      'hdlType' => 'std_logic',
541 
      'width' => 1,
542 
    },
543 
    'from_register15.data_out' => {
544 
      'hdlType' => 'std_logic_vector(31 downto 0)',
545 
      'width' => 32,
546 
    },
547 
    'from_register16.data_out' => {
548 
      'hdlType' => 'std_logic',
549 
      'width' => 1,
550 
    },
551 
    'from_register17.data_out' => {
552 
      'hdlType' => 'std_logic_vector(31 downto 0)',
553 
      'width' => 32,
554 
    },
555 
    'from_register18.data_out' => {
556 
      'hdlType' => 'std_logic',
557 
      'width' => 1,
558 
    },
559 
    'from_register19.data_out' => {
560 
      'hdlType' => 'std_logic_vector(31 downto 0)',
561 
      'width' => 32,
562 
    },
563 
    'from_register2.data_out' => {
564 
      'hdlType' => 'std_logic',
565 
      'width' => 1,
566 
    },
567 
    'from_register20.data_out' => {
568 
      'hdlType' => 'std_logic',
569 
      'width' => 1,
570 
    },
571 
    'from_register21.data_out' => {
572 
      'hdlType' => 'std_logic_vector(31 downto 0)',
573 
      'width' => 32,
574 
    },
575 
    'from_register22.data_out' => {
576 
      'hdlType' => 'std_logic',
577 
      'width' => 1,
578 
    },
579 
    'from_register23.data_out' => {
580 
      'hdlType' => 'std_logic_vector(31 downto 0)',
581 
      'width' => 32,
582 
    },
583 
    'from_register24.data_out' => {
584 
      'hdlType' => 'std_logic',
585 
      'width' => 1,
586 
    },
587 
    'from_register25.data_out' => {
588 
      'hdlType' => 'std_logic_vector(31 downto 0)',
589 
      'width' => 32,
590 
    },
591 
    'from_register26.data_out' => {
592 
      'hdlType' => 'std_logic',
593 
      'width' => 1,
594 
    },
595 
    'from_register27.data_out' => {
596 
      'hdlType' => 'std_logic_vector(31 downto 0)',
597 
      'width' => 32,
598 
    },
599 
    'from_register28.data_out' => {
600 
      'hdlType' => 'std_logic',
601 
      'width' => 1,
602 
    },
603 
    'from_register3.data_out' => {
604 
      'hdlType' => 'std_logic_vector(31 downto 0)',
605 
      'width' => 32,
606 
    },
607 
    'from_register4.data_out' => {
608 
      'hdlType' => 'std_logic',
609 
      'width' => 1,
610 
    },
611 
    'from_register5.data_out' => {
612 
      'hdlType' => 'std_logic_vector(31 downto 0)',
613 
      'width' => 32,
614 
    },
615 
    'from_register6.data_out' => {
616 
      'hdlType' => 'std_logic',
617 
      'width' => 1,
618 
    },
619 
    'from_register7.data_out' => {
620 
      'hdlType' => 'std_logic_vector(31 downto 0)',
621 
      'width' => 32,
622 
    },
623 
    'from_register8.data_out' => {
624 
      'hdlType' => 'std_logic_vector(31 downto 0)',
625 
      'width' => 32,
626 
    },
627 
    'from_register9.data_out' => {
628 
      'hdlType' => 'std_logic',
629 
      'width' => 1,
630 
    },
631 
    'sysgen_dut.reg01_rd' => {
632 
      'hdlType' => 'std_logic_vector(31 downto 0)',
633 
      'width' => 32,
634 
    },
635 
    'sysgen_dut.reg01_rv' => {
636 
      'hdlType' => 'std_logic',
637 
      'width' => 1,
638 
    },
639 
    'sysgen_dut.reg02_rd' => {
640 
      'hdlType' => 'std_logic_vector(31 downto 0)',
641 
      'width' => 32,
642 
    },
643 
    'sysgen_dut.reg02_rv' => {
644 
      'hdlType' => 'std_logic',
645 
      'width' => 1,
646 
    },
647 
    'sysgen_dut.reg03_rd' => {
648 
      'hdlType' => 'std_logic_vector(31 downto 0)',
649 
      'width' => 32,
650 
    },
651 
    'sysgen_dut.reg03_rv' => {
652 
      'hdlType' => 'std_logic',
653 
      'width' => 1,
654 
    },
655 
    'sysgen_dut.reg04_rd' => {
656 
      'hdlType' => 'std_logic_vector(31 downto 0)',
657 
      'width' => 32,
658 
    },
659 
    'sysgen_dut.reg04_rv' => {
660 
      'hdlType' => 'std_logic',
661 
      'width' => 1,
662 
    },
663 
    'sysgen_dut.reg05_rd' => {
664 
      'hdlType' => 'std_logic_vector(31 downto 0)',
665 
      'width' => 32,
666 
    },
667 
    'sysgen_dut.reg05_rv' => {
668 
      'hdlType' => 'std_logic',
669 
      'width' => 1,
670 
    },
671 
    'sysgen_dut.reg06_rd' => {
672 
      'hdlType' => 'std_logic_vector(31 downto 0)',
673 
      'width' => 32,
674 
    },
675 
    'sysgen_dut.reg06_rv' => {
676 
      'hdlType' => 'std_logic',
677 
      'width' => 1,
678 
    },
679 
    'sysgen_dut.reg07_rd' => {
680 
      'hdlType' => 'std_logic_vector(31 downto 0)',
681 
      'width' => 32,
682 
    },
683 
    'sysgen_dut.reg07_rv' => {
684 
      'hdlType' => 'std_logic',
685 
      'width' => 1,
686 
    },
687 
    'sysgen_dut.reg08_rd' => {
688 
      'hdlType' => 'std_logic_vector(31 downto 0)',
689 
      'width' => 32,
690 
    },
691 
    'sysgen_dut.reg08_rv' => {
692 
      'hdlType' => 'std_logic',
693 
      'width' => 1,
694 
    },
695 
    'sysgen_dut.reg09_rd' => {
696 
      'hdlType' => 'std_logic_vector(31 downto 0)',
697 
      'width' => 32,
698 
    },
699 
    'sysgen_dut.reg09_rv' => {
700 
      'hdlType' => 'std_logic',
701 
      'width' => 1,
702 
    },
703 
    'sysgen_dut.reg10_rd' => {
704 
      'hdlType' => 'std_logic_vector(31 downto 0)',
705 
      'width' => 32,
706 
    },
707 
    'sysgen_dut.reg10_rv' => {
708 
      'hdlType' => 'std_logic',
709 
      'width' => 1,
710 
    },
711 
    'sysgen_dut.reg11_rd' => {
712 
      'hdlType' => 'std_logic_vector(31 downto 0)',
713 
      'width' => 32,
714 
    },
715 
    'sysgen_dut.reg11_rv' => {
716 
      'hdlType' => 'std_logic',
717 
      'width' => 1,
718 
    },
719 
    'sysgen_dut.reg12_rd' => {
720 
      'hdlType' => 'std_logic_vector(31 downto 0)',
721 
      'width' => 32,
722 
    },
723 
    'sysgen_dut.reg12_rv' => {
724 
      'hdlType' => 'std_logic',
725 
      'width' => 1,
726 
    },
727 
    'sysgen_dut.reg13_rd' => {
728 
      'hdlType' => 'std_logic_vector(31 downto 0)',
729 
      'width' => 32,
730 
    },
731 
    'sysgen_dut.reg13_rv' => {
732 
      'hdlType' => 'std_logic',
733 
      'width' => 1,
734 
    },
735 
    'sysgen_dut.reg14_rd' => {
736 
      'hdlType' => 'std_logic_vector(31 downto 0)',
737 
      'width' => 32,
738 
    },
739 
    'sysgen_dut.reg14_rv' => {
740 
      'hdlType' => 'std_logic',
741 
      'width' => 1,
742 
    },
743 
    'sysgen_dut.to_register10_ce' => {
744 
      'hdlType' => 'std_logic',
745 
      'width' => 1,
746 
    },
747 
    'sysgen_dut.to_register10_clk' => {
748 
      'hdlType' => 'std_logic',
749 
      'width' => 1,
750 
    },
751 
    'sysgen_dut.to_register10_clr' => {
752 
      'hdlType' => 'std_logic',
753 
      'width' => 1,
754 
    },
755 
    'sysgen_dut.to_register10_data_in' => {
756 
      'hdlType' => 'std_logic',
757 
      'width' => 1,
758 
    },
759 
    'sysgen_dut.to_register10_en' => {
760 
      'hdlType' => 'std_logic',
761 
      'width' => 1,
762 
    },
763 
    'sysgen_dut.to_register11_ce' => {
764 
      'hdlType' => 'std_logic',
765 
      'width' => 1,
766 
    },
767 
    'sysgen_dut.to_register11_clk' => {
768 
      'hdlType' => 'std_logic',
769 
      'width' => 1,
770 
    },
771 
    'sysgen_dut.to_register11_clr' => {
772 
      'hdlType' => 'std_logic',
773 
      'width' => 1,
774 
    },
775 
    'sysgen_dut.to_register11_data_in' => {
776 
      'hdlType' => 'std_logic_vector(31 downto 0)',
777 
      'width' => 32,
778 
    },
779 
    'sysgen_dut.to_register11_en' => {
780 
      'hdlType' => 'std_logic',
781 
      'width' => 1,
782 
    },
783 
    'sysgen_dut.to_register12_ce' => {
784 
      'hdlType' => 'std_logic',
785 
      'width' => 1,
786 
    },
787 
    'sysgen_dut.to_register12_clk' => {
788 
      'hdlType' => 'std_logic',
789 
      'width' => 1,
790 
    },
791 
    'sysgen_dut.to_register12_clr' => {
792 
      'hdlType' => 'std_logic',
793 
      'width' => 1,
794 
    },
795 
    'sysgen_dut.to_register12_data_in' => {
796 
      'hdlType' => 'std_logic',
797 
      'width' => 1,
798 
    },
799 
    'sysgen_dut.to_register12_en' => {
800 
      'hdlType' => 'std_logic',
801 
      'width' => 1,
802 
    },
803 
    'sysgen_dut.to_register13_ce' => {
804 
      'hdlType' => 'std_logic',
805 
      'width' => 1,
806 
    },
807 
    'sysgen_dut.to_register13_clk' => {
808 
      'hdlType' => 'std_logic',
809 
      'width' => 1,
810 
    },
811 
    'sysgen_dut.to_register13_clr' => {
812 
      'hdlType' => 'std_logic',
813 
      'width' => 1,
814 
    },
815 
    'sysgen_dut.to_register13_data_in' => {
816 
      'hdlType' => 'std_logic_vector(31 downto 0)',
817 
      'width' => 32,
818 
    },
819 
    'sysgen_dut.to_register13_en' => {
820 
      'hdlType' => 'std_logic',
821 
      'width' => 1,
822 
    },
823 
    'sysgen_dut.to_register14_ce' => {
824 
      'hdlType' => 'std_logic',
825 
      'width' => 1,
826 
    },
827 
    'sysgen_dut.to_register14_clk' => {
828 
      'hdlType' => 'std_logic',
829 
      'width' => 1,
830 
    },
831 
    'sysgen_dut.to_register14_clr' => {
832 
      'hdlType' => 'std_logic',
833 
      'width' => 1,
834 
    },
835 
    'sysgen_dut.to_register14_data_in' => {
836 
      'hdlType' => 'std_logic',
837 
      'width' => 1,
838 
    },
839 
    'sysgen_dut.to_register14_en' => {
840 
      'hdlType' => 'std_logic',
841 
      'width' => 1,
842 
    },
843 
    'sysgen_dut.to_register15_ce' => {
844 
      'hdlType' => 'std_logic',
845 
      'width' => 1,
846 
    },
847 
    'sysgen_dut.to_register15_clk' => {
848 
      'hdlType' => 'std_logic',
849 
      'width' => 1,
850 
    },
851 
    'sysgen_dut.to_register15_clr' => {
852 
      'hdlType' => 'std_logic',
853 
      'width' => 1,
854 
    },
855 
    'sysgen_dut.to_register15_data_in' => {
856 
      'hdlType' => 'std_logic_vector(31 downto 0)',
857 
      'width' => 32,
858 
    },
859 
    'sysgen_dut.to_register15_en' => {
860 
      'hdlType' => 'std_logic',
861 
      'width' => 1,
862 
    },
863 
    'sysgen_dut.to_register16_ce' => {
864 
      'hdlType' => 'std_logic',
865 
      'width' => 1,
866 
    },
867 
    'sysgen_dut.to_register16_clk' => {
868 
      'hdlType' => 'std_logic',
869 
      'width' => 1,
870 
    },
871 
    'sysgen_dut.to_register16_clr' => {
872 
      'hdlType' => 'std_logic',
873 
      'width' => 1,
874 
    },
875 
    'sysgen_dut.to_register16_data_in' => {
876 
      'hdlType' => 'std_logic',
877 
      'width' => 1,
878 
    },
879 
    'sysgen_dut.to_register16_en' => {
880 
      'hdlType' => 'std_logic',
881 
      'width' => 1,
882 
    },
883 
    'sysgen_dut.to_register17_ce' => {
884 
      'hdlType' => 'std_logic',
885 
      'width' => 1,
886 
    },
887 
    'sysgen_dut.to_register17_clk' => {
888 
      'hdlType' => 'std_logic',
889 
      'width' => 1,
890 
    },
891 
    'sysgen_dut.to_register17_clr' => {
892 
      'hdlType' => 'std_logic',
893 
      'width' => 1,
894 
    },
895 
    'sysgen_dut.to_register17_data_in' => {
896 
      'hdlType' => 'std_logic_vector(31 downto 0)',
897 
      'width' => 32,
898 
    },
899 
    'sysgen_dut.to_register17_en' => {
900 
      'hdlType' => 'std_logic',
901 
      'width' => 1,
902 
    },
903 
    'sysgen_dut.to_register18_ce' => {
904 
      'hdlType' => 'std_logic',
905 
      'width' => 1,
906 
    },
907 
    'sysgen_dut.to_register18_clk' => {
908 
      'hdlType' => 'std_logic',
909 
      'width' => 1,
910 
    },
911 
    'sysgen_dut.to_register18_clr' => {
912 
      'hdlType' => 'std_logic',
913 
      'width' => 1,
914 
    },
915 
    'sysgen_dut.to_register18_data_in' => {
916 
      'hdlType' => 'std_logic',
917 
      'width' => 1,
918 
    },
919 
    'sysgen_dut.to_register18_en' => {
920 
      'hdlType' => 'std_logic',
921 
      'width' => 1,
922 
    },
923 
    'sysgen_dut.to_register19_ce' => {
924 
      'hdlType' => 'std_logic',
925 
      'width' => 1,
926 
    },
927 
    'sysgen_dut.to_register19_clk' => {
928 
      'hdlType' => 'std_logic',
929 
      'width' => 1,
930 
    },
931 
    'sysgen_dut.to_register19_clr' => {
932 
      'hdlType' => 'std_logic',
933 
      'width' => 1,
934 
    },
935 
    'sysgen_dut.to_register19_data_in' => {
936 
      'hdlType' => 'std_logic',
937 
      'width' => 1,
938 
    },
939 
    'sysgen_dut.to_register19_en' => {
940 
      'hdlType' => 'std_logic',
941 
      'width' => 1,
942 
    },
943 
    'sysgen_dut.to_register1_ce' => {
944 
      'hdlType' => 'std_logic',
945 
      'width' => 1,
946 
    },
947 
    'sysgen_dut.to_register1_clk' => {
948 
      'hdlType' => 'std_logic',
949 
      'width' => 1,
950 
    },
951 
    'sysgen_dut.to_register1_clr' => {
952 
      'hdlType' => 'std_logic',
953 
      'width' => 1,
954 
    },
955 
    'sysgen_dut.to_register1_data_in' => {
956 
      'hdlType' => 'std_logic_vector(31 downto 0)',
957 
      'width' => 32,
958 
    },
959 
    'sysgen_dut.to_register1_en' => {
960 
      'hdlType' => 'std_logic',
961 
      'width' => 1,
962 
    },
963 
    'sysgen_dut.to_register20_ce' => {
964 
      'hdlType' => 'std_logic',
965 
      'width' => 1,
966 
    },
967 
    'sysgen_dut.to_register20_clk' => {
968 
      'hdlType' => 'std_logic',
969 
      'width' => 1,
970 
    },
971 
    'sysgen_dut.to_register20_clr' => {
972 
      'hdlType' => 'std_logic',
973 
      'width' => 1,
974 
    },
975 
    'sysgen_dut.to_register20_data_in' => {
976 
      'hdlType' => 'std_logic_vector(31 downto 0)',
977 
      'width' => 32,
978 
    },
979 
    'sysgen_dut.to_register20_en' => {
980 
      'hdlType' => 'std_logic',
981 
      'width' => 1,
982 
    },
983 
    'sysgen_dut.to_register21_ce' => {
984 
      'hdlType' => 'std_logic',
985 
      'width' => 1,
986 
    },
987 
    'sysgen_dut.to_register21_clk' => {
988 
      'hdlType' => 'std_logic',
989 
      'width' => 1,
990 
    },
991 
    'sysgen_dut.to_register21_clr' => {
992 
      'hdlType' => 'std_logic',
993 
      'width' => 1,
994 
    },
995 
    'sysgen_dut.to_register21_data_in' => {
996 
      'hdlType' => 'std_logic',
997 
      'width' => 1,
998 
    },
999 
    'sysgen_dut.to_register21_en' => {
1000 
      'hdlType' => 'std_logic',
1001 
      'width' => 1,
1002 
    },
1003 
    'sysgen_dut.to_register22_ce' => {
1004 
      'hdlType' => 'std_logic',
1005 
      'width' => 1,
1006 
    },
1007 
    'sysgen_dut.to_register22_clk' => {
1008 
      'hdlType' => 'std_logic',
1009 
      'width' => 1,
1010 
    },
1011 
    'sysgen_dut.to_register22_clr' => {
1012 
      'hdlType' => 'std_logic',
1013 
      'width' => 1,
1014 
    },
1015 
    'sysgen_dut.to_register22_data_in' => {
1016 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1017 
      'width' => 32,
1018 
    },
1019 
    'sysgen_dut.to_register22_en' => {
1020 
      'hdlType' => 'std_logic',
1021 
      'width' => 1,
1022 
    },
1023 
    'sysgen_dut.to_register23_ce' => {
1024 
      'hdlType' => 'std_logic',
1025 
      'width' => 1,
1026 
    },
1027 
    'sysgen_dut.to_register23_clk' => {
1028 
      'hdlType' => 'std_logic',
1029 
      'width' => 1,
1030 
    },
1031 
    'sysgen_dut.to_register23_clr' => {
1032 
      'hdlType' => 'std_logic',
1033 
      'width' => 1,
1034 
    },
1035 
    'sysgen_dut.to_register23_data_in' => {
1036 
      'hdlType' => 'std_logic',
1037 
      'width' => 1,
1038 
    },
1039 
    'sysgen_dut.to_register23_en' => {
1040 
      'hdlType' => 'std_logic',
1041 
      'width' => 1,
1042 
    },
1043 
    'sysgen_dut.to_register24_ce' => {
1044 
      'hdlType' => 'std_logic',
1045 
      'width' => 1,
1046 
    },
1047 
    'sysgen_dut.to_register24_clk' => {
1048 
      'hdlType' => 'std_logic',
1049 
      'width' => 1,
1050 
    },
1051 
    'sysgen_dut.to_register24_clr' => {
1052 
      'hdlType' => 'std_logic',
1053 
      'width' => 1,
1054 
    },
1055 
    'sysgen_dut.to_register24_data_in' => {
1056 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1057 
      'width' => 32,
1058 
    },
1059 
    'sysgen_dut.to_register24_en' => {
1060 
      'hdlType' => 'std_logic',
1061 
      'width' => 1,
1062 
    },
1063 
    'sysgen_dut.to_register25_ce' => {
1064 
      'hdlType' => 'std_logic',
1065 
      'width' => 1,
1066 
    },
1067 
    'sysgen_dut.to_register25_clk' => {
1068 
      'hdlType' => 'std_logic',
1069 
      'width' => 1,
1070 
    },
1071 
    'sysgen_dut.to_register25_clr' => {
1072 
      'hdlType' => 'std_logic',
1073 
      'width' => 1,
1074 
    },
1075 
    'sysgen_dut.to_register25_data_in' => {
1076 
      'hdlType' => 'std_logic',
1077 
      'width' => 1,
1078 
    },
1079 
    'sysgen_dut.to_register25_en' => {
1080 
      'hdlType' => 'std_logic',
1081 
      'width' => 1,
1082 
    },
1083 
    'sysgen_dut.to_register26_ce' => {
1084 
      'hdlType' => 'std_logic',
1085 
      'width' => 1,
1086 
    },
1087 
    'sysgen_dut.to_register26_clk' => {
1088 
      'hdlType' => 'std_logic',
1089 
      'width' => 1,
1090 
    },
1091 
    'sysgen_dut.to_register26_clr' => {
1092 
      'hdlType' => 'std_logic',
1093 
      'width' => 1,
1094 
    },
1095 
    'sysgen_dut.to_register26_data_in' => {
1096 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1097 
      'width' => 32,
1098 
    },
1099 
    'sysgen_dut.to_register26_en' => {
1100 
      'hdlType' => 'std_logic',
1101 
      'width' => 1,
1102 
    },
1103 
    'sysgen_dut.to_register27_ce' => {
1104 
      'hdlType' => 'std_logic',
1105 
      'width' => 1,
1106 
    },
1107 
    'sysgen_dut.to_register27_clk' => {
1108 
      'hdlType' => 'std_logic',
1109 
      'width' => 1,
1110 
    },
1111 
    'sysgen_dut.to_register27_clr' => {
1112 
      'hdlType' => 'std_logic',
1113 
      'width' => 1,
1114 
    },
1115 
    'sysgen_dut.to_register27_data_in' => {
1116 
      'hdlType' => 'std_logic',
1117 
      'width' => 1,
1118 
    },
1119 
    'sysgen_dut.to_register27_en' => {
1120 
      'hdlType' => 'std_logic',
1121 
      'width' => 1,
1122 
    },
1123 
    'sysgen_dut.to_register28_ce' => {
1124 
      'hdlType' => 'std_logic',
1125 
      'width' => 1,
1126 
    },
1127 
    'sysgen_dut.to_register28_clk' => {
1128 
      'hdlType' => 'std_logic',
1129 
      'width' => 1,
1130 
    },
1131 
    'sysgen_dut.to_register28_clr' => {
1132 
      'hdlType' => 'std_logic',
1133 
      'width' => 1,
1134 
    },
1135 
    'sysgen_dut.to_register28_data_in' => {
1136 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1137 
      'width' => 32,
1138 
    },
1139 
    'sysgen_dut.to_register28_en' => {
1140 
      'hdlType' => 'std_logic',
1141 
      'width' => 1,
1142 
    },
1143 
    'sysgen_dut.to_register29_ce' => {
1144 
      'hdlType' => 'std_logic',
1145 
      'width' => 1,
1146 
    },
1147 
    'sysgen_dut.to_register29_clk' => {
1148 
      'hdlType' => 'std_logic',
1149 
      'width' => 1,
1150 
    },
1151 
    'sysgen_dut.to_register29_clr' => {
1152 
      'hdlType' => 'std_logic',
1153 
      'width' => 1,
1154 
    },
1155 
    'sysgen_dut.to_register29_data_in' => {
1156 
      'hdlType' => 'std_logic',
1157 
      'width' => 1,
1158 
    },
1159 
    'sysgen_dut.to_register29_en' => {
1160 
      'hdlType' => 'std_logic',
1161 
      'width' => 1,
1162 
    },
1163 
    'sysgen_dut.to_register2_ce' => {
1164 
      'hdlType' => 'std_logic',
1165 
      'width' => 1,
1166 
    },
1167 
    'sysgen_dut.to_register2_clk' => {
1168 
      'hdlType' => 'std_logic',
1169 
      'width' => 1,
1170 
    },
1171 
    'sysgen_dut.to_register2_clr' => {
1172 
      'hdlType' => 'std_logic',
1173 
      'width' => 1,
1174 
    },
1175 
    'sysgen_dut.to_register2_data_in' => {
1176 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1177 
      'width' => 32,
1178 
    },
1179 
    'sysgen_dut.to_register2_en' => {
1180 
      'hdlType' => 'std_logic',
1181 
      'width' => 1,
1182 
    },
1183 
    'sysgen_dut.to_register30_ce' => {
1184 
      'hdlType' => 'std_logic',
1185 
      'width' => 1,
1186 
    },
1187 
    'sysgen_dut.to_register30_clk' => {
1188 
      'hdlType' => 'std_logic',
1189 
      'width' => 1,
1190 
    },
1191 
    'sysgen_dut.to_register30_clr' => {
1192 
      'hdlType' => 'std_logic',
1193 
      'width' => 1,
1194 
    },
1195 
    'sysgen_dut.to_register30_data_in' => {
1196 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1197 
      'width' => 32,
1198 
    },
1199 
    'sysgen_dut.to_register30_en' => {
1200 
      'hdlType' => 'std_logic',
1201 
      'width' => 1,
1202 
    },
1203 
    'sysgen_dut.to_register31_ce' => {
1204 
      'hdlType' => 'std_logic',
1205 
      'width' => 1,
1206 
    },
1207 
    'sysgen_dut.to_register31_clk' => {
1208 
      'hdlType' => 'std_logic',
1209 
      'width' => 1,
1210 
    },
1211 
    'sysgen_dut.to_register31_clr' => {
1212 
      'hdlType' => 'std_logic',
1213 
      'width' => 1,
1214 
    },
1215 
    'sysgen_dut.to_register31_data_in' => {
1216 
      'hdlType' => 'std_logic',
1217 
      'width' => 1,
1218 
    },
1219 
    'sysgen_dut.to_register31_en' => {
1220 
      'hdlType' => 'std_logic',
1221 
      'width' => 1,
1222 
    },
1223 
    'sysgen_dut.to_register32_ce' => {
1224 
      'hdlType' => 'std_logic',
1225 
      'width' => 1,
1226 
    },
1227 
    'sysgen_dut.to_register32_clk' => {
1228 
      'hdlType' => 'std_logic',
1229 
      'width' => 1,
1230 
    },
1231 
    'sysgen_dut.to_register32_clr' => {
1232 
      'hdlType' => 'std_logic',
1233 
      'width' => 1,
1234 
    },
1235 
    'sysgen_dut.to_register32_data_in' => {
1236 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1237 
      'width' => 32,
1238 
    },
1239 
    'sysgen_dut.to_register32_en' => {
1240 
      'hdlType' => 'std_logic',
1241 
      'width' => 1,
1242 
    },
1243 
    'sysgen_dut.to_register33_ce' => {
1244 
      'hdlType' => 'std_logic',
1245 
      'width' => 1,
1246 
    },
1247 
    'sysgen_dut.to_register33_clk' => {
1248 
      'hdlType' => 'std_logic',
1249 
      'width' => 1,
1250 
    },
1251 
    'sysgen_dut.to_register33_clr' => {
1252 
      'hdlType' => 'std_logic',
1253 
      'width' => 1,
1254 
    },
1255 
    'sysgen_dut.to_register33_data_in' => {
1256 
      'hdlType' => 'std_logic',
1257 
      'width' => 1,
1258 
    },
1259 
    'sysgen_dut.to_register33_en' => {
1260 
      'hdlType' => 'std_logic',
1261 
      'width' => 1,
1262 
    },
1263 
    'sysgen_dut.to_register34_ce' => {
1264 
      'hdlType' => 'std_logic',
1265 
      'width' => 1,
1266 
    },
1267 
    'sysgen_dut.to_register34_clk' => {
1268 
      'hdlType' => 'std_logic',
1269 
      'width' => 1,
1270 
    },
1271 
    'sysgen_dut.to_register34_clr' => {
1272 
      'hdlType' => 'std_logic',
1273 
      'width' => 1,
1274 
    },
1275 
    'sysgen_dut.to_register34_data_in' => {
1276 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1277 
      'width' => 32,
1278 
    },
1279 
    'sysgen_dut.to_register34_en' => {
1280 
      'hdlType' => 'std_logic',
1281 
      'width' => 1,
1282 
    },
1283 
    'sysgen_dut.to_register3_ce' => {
1284 
      'hdlType' => 'std_logic',
1285 
      'width' => 1,
1286 
    },
1287 
    'sysgen_dut.to_register3_clk' => {
1288 
      'hdlType' => 'std_logic',
1289 
      'width' => 1,
1290 
    },
1291 
    'sysgen_dut.to_register3_clr' => {
1292 
      'hdlType' => 'std_logic',
1293 
      'width' => 1,
1294 
    },
1295 
    'sysgen_dut.to_register3_data_in' => {
1296 
      'hdlType' => 'std_logic',
1297 
      'width' => 1,
1298 
    },
1299 
    'sysgen_dut.to_register3_en' => {
1300 
      'hdlType' => 'std_logic',
1301 
      'width' => 1,
1302 
    },
1303 
    'sysgen_dut.to_register4_ce' => {
1304 
      'hdlType' => 'std_logic',
1305 
      'width' => 1,
1306 
    },
1307 
    'sysgen_dut.to_register4_clk' => {
1308 
      'hdlType' => 'std_logic',
1309 
      'width' => 1,
1310 
    },
1311 
    'sysgen_dut.to_register4_clr' => {
1312 
      'hdlType' => 'std_logic',
1313 
      'width' => 1,
1314 
    },
1315 
    'sysgen_dut.to_register4_data_in' => {
1316 
      'hdlType' => 'std_logic',
1317 
      'width' => 1,
1318 
    },
1319 
    'sysgen_dut.to_register4_en' => {
1320 
      'hdlType' => 'std_logic',
1321 
      'width' => 1,
1322 
    },
1323 
    'sysgen_dut.to_register5_ce' => {
1324 
      'hdlType' => 'std_logic',
1325 
      'width' => 1,
1326 
    },
1327 
    'sysgen_dut.to_register5_clk' => {
1328 
      'hdlType' => 'std_logic',
1329 
      'width' => 1,
1330 
    },
1331 
    'sysgen_dut.to_register5_clr' => {
1332 
      'hdlType' => 'std_logic',
1333 
      'width' => 1,
1334 
    },
1335 
    'sysgen_dut.to_register5_data_in' => {
1336 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1337 
      'width' => 32,
1338 
    },
1339 
    'sysgen_dut.to_register5_en' => {
1340 
      'hdlType' => 'std_logic',
1341 
      'width' => 1,
1342 
    },
1343 
    'sysgen_dut.to_register6_ce' => {
1344 
      'hdlType' => 'std_logic',
1345 
      'width' => 1,
1346 
    },
1347 
    'sysgen_dut.to_register6_clk' => {
1348 
      'hdlType' => 'std_logic',
1349 
      'width' => 1,
1350 
    },
1351 
    'sysgen_dut.to_register6_clr' => {
1352 
      'hdlType' => 'std_logic',
1353 
      'width' => 1,
1354 
    },
1355 
    'sysgen_dut.to_register6_data_in' => {
1356 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1357 
      'width' => 32,
1358 
    },
1359 
    'sysgen_dut.to_register6_en' => {
1360 
      'hdlType' => 'std_logic',
1361 
      'width' => 1,
1362 
    },
1363 
    'sysgen_dut.to_register7_ce' => {
1364 
      'hdlType' => 'std_logic',
1365 
      'width' => 1,
1366 
    },
1367 
    'sysgen_dut.to_register7_clk' => {
1368 
      'hdlType' => 'std_logic',
1369 
      'width' => 1,
1370 
    },
1371 
    'sysgen_dut.to_register7_clr' => {
1372 
      'hdlType' => 'std_logic',
1373 
      'width' => 1,
1374 
    },
1375 
    'sysgen_dut.to_register7_data_in' => {
1376 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1377 
      'width' => 32,
1378 
    },
1379 
    'sysgen_dut.to_register7_en' => {
1380 
      'hdlType' => 'std_logic',
1381 
      'width' => 1,
1382 
    },
1383 
    'sysgen_dut.to_register8_ce' => {
1384 
      'hdlType' => 'std_logic',
1385 
      'width' => 1,
1386 
    },
1387 
    'sysgen_dut.to_register8_clk' => {
1388 
      'hdlType' => 'std_logic',
1389 
      'width' => 1,
1390 
    },
1391 
    'sysgen_dut.to_register8_clr' => {
1392 
      'hdlType' => 'std_logic',
1393 
      'width' => 1,
1394 
    },
1395 
    'sysgen_dut.to_register8_data_in' => {
1396 
      'hdlType' => 'std_logic',
1397 
      'width' => 1,
1398 
    },
1399 
    'sysgen_dut.to_register8_en' => {
1400 
      'hdlType' => 'std_logic',
1401 
      'width' => 1,
1402 
    },
1403 
    'sysgen_dut.to_register9_ce' => {
1404 
      'hdlType' => 'std_logic',
1405 
      'width' => 1,
1406 
    },
1407 
    'sysgen_dut.to_register9_clk' => {
1408 
      'hdlType' => 'std_logic',
1409 
      'width' => 1,
1410 
    },
1411 
    'sysgen_dut.to_register9_clr' => {
1412 
      'hdlType' => 'std_logic',
1413 
      'width' => 1,
1414 
    },
1415 
    'sysgen_dut.to_register9_data_in' => {
1416 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1417 
      'width' => 32,
1418 
    },
1419 
    'sysgen_dut.to_register9_en' => {
1420 
      'hdlType' => 'std_logic',
1421 
      'width' => 1,
1422 
    },
1423 
    'to_register1.dout' => {
1424 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1425 
      'width' => 32,
1426 
    },
1427 
    'to_register10.dout' => {
1428 
      'hdlType' => 'std_logic',
1429 
      'width' => 1,
1430 
    },
1431 
    'to_register11.dout' => {
1432 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1433 
      'width' => 32,
1434 
    },
1435 
    'to_register12.dout' => {
1436 
      'hdlType' => 'std_logic',
1437 
      'width' => 1,
1438 
    },
1439 
    'to_register13.dout' => {
1440 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1441 
      'width' => 32,
1442 
    },
1443 
    'to_register14.dout' => {
1444 
      'hdlType' => 'std_logic',
1445 
      'width' => 1,
1446 
    },
1447 
    'to_register15.dout' => {
1448 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1449 
      'width' => 32,
1450 
    },
1451 
    'to_register16.dout' => {
1452 
      'hdlType' => 'std_logic',
1453 
      'width' => 1,
1454 
    },
1455 
    'to_register17.dout' => {
1456 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1457 
      'width' => 32,
1458 
    },
1459 
    'to_register18.dout' => {
1460 
      'hdlType' => 'std_logic',
1461 
      'width' => 1,
1462 
    },
1463 
    'to_register19.dout' => {
1464 
      'hdlType' => 'std_logic',
1465 
      'width' => 1,
1466 
    },
1467 
    'to_register2.dout' => {
1468 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1469 
      'width' => 32,
1470 
    },
1471 
    'to_register20.dout' => {
1472 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1473 
      'width' => 32,
1474 
    },
1475 
    'to_register21.dout' => {
1476 
      'hdlType' => 'std_logic',
1477 
      'width' => 1,
1478 
    },
1479 
    'to_register22.dout' => {
1480 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1481 
      'width' => 32,
1482 
    },
1483 
    'to_register23.dout' => {
1484 
      'hdlType' => 'std_logic',
1485 
      'width' => 1,
1486 
    },
1487 
    'to_register24.dout' => {
1488 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1489 
      'width' => 32,
1490 
    },
1491 
    'to_register25.dout' => {
1492 
      'hdlType' => 'std_logic',
1493 
      'width' => 1,
1494 
    },
1495 
    'to_register26.dout' => {
1496 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1497 
      'width' => 32,
1498 
    },
1499 
    'to_register27.dout' => {
1500 
      'hdlType' => 'std_logic',
1501 
      'width' => 1,
1502 
    },
1503 
    'to_register28.dout' => {
1504 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1505 
      'width' => 32,
1506 
    },
1507 
    'to_register29.dout' => {
1508 
      'hdlType' => 'std_logic',
1509 
      'width' => 1,
1510 
    },
1511 
    'to_register3.dout' => {
1512 
      'hdlType' => 'std_logic',
1513 
      'width' => 1,
1514 
    },
1515 
    'to_register30.dout' => {
1516 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1517 
      'width' => 32,
1518 
    },
1519 
    'to_register31.dout' => {
1520 
      'hdlType' => 'std_logic',
1521 
      'width' => 1,
1522 
    },
1523 
    'to_register32.dout' => {
1524 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1525 
      'width' => 32,
1526 
    },
1527 
    'to_register33.dout' => {
1528 
      'hdlType' => 'std_logic',
1529 
      'width' => 1,
1530 
    },
1531 
    'to_register34.dout' => {
1532 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1533 
      'width' => 32,
1534 
    },
1535 
    'to_register4.dout' => {
1536 
      'hdlType' => 'std_logic',
1537 
      'width' => 1,
1538 
    },
1539 
    'to_register5.dout' => {
1540 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1541 
      'width' => 32,
1542 
    },
1543 
    'to_register6.dout' => {
1544 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1545 
      'width' => 32,
1546 
    },
1547 
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              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
5016 
              'timingConstraint' => 'none',
5017 
              'type' => 'UFix_32_0',
5018 
            },
5019 
            'direction' => 'in',
5020 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5021 
            'width' => 32,
5022 
          },
5023 
        },
5024 
      },
5025 
      'entityName' => 'reg13_rd',
5026 
    },
5027 
    'reg13_rv' => {
5028 
      'connections' => {
5029 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5030 
      },
5031 
      'entity' => {
5032 
        'attributes' => {
5033 
          'entityAlreadyNetlisted' => 1,
5034 
          'isGateway' => 1,
5035 
          'is_floating_block' => 1,
5036 
        },
5037 
        'entityName' => 'reg13_rv',
5038 
        'ports' => {
5039 
          'reg13_rv' => {
5040 
            'attributes' => {
5041 
              'bin_pt' => 0,
5042 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
5043 
              'is_floating_block' => 1,
5044 
              'is_gateway_port' => 1,
5045 
              'must_be_hdl_vector' => 1,
5046 
              'period' => 1,
5047 
              'port_id' => 0,
5048 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
5049 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
5050 
              'timingConstraint' => 'none',
5051 
              'type' => 'UFix_1_0',
5052 
            },
5053 
            'direction' => 'in',
5054 
            'hdlType' => 'std_logic',
5055 
            'width' => 1,
5056 
          },
5057 
        },
5058 
      },
5059 
      'entityName' => 'reg13_rv',
5060 
    },
5061 
    'reg13_td' => {
5062 
      'connections' => {
5063 
        'reg13_td' => '.reg13_td',
5064 
      },
5065 
      'entity' => {
5066 
        'attributes' => {
5067 
          'entityAlreadyNetlisted' => 1,
5068 
          'isGateway' => 1,
5069 
          'is_floating_block' => 1,
5070 
        },
5071 
        'entityName' => 'reg13_td',
5072 
        'ports' => {
5073 
          'reg13_td' => {
5074 
            'attributes' => {
5075 
              'bin_pt' => 0,
5076 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5077 
              'is_floating_block' => 1,
5078 
              'is_gateway_port' => 1,
5079 
              'must_be_hdl_vector' => 1,
5080 
              'period' => 1,
5081 
              'port_id' => 0,
5082 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
5083 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
5084 
              'timingConstraint' => 'none',
5085 
              'type' => 'UFix_32_0',
5086 
            },
5087 
            'direction' => 'out',
5088 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5089 
            'width' => 32,
5090 
          },
5091 
        },
5092 
      },
5093 
      'entityName' => 'reg13_td',
5094 
    },
5095 
    'reg13_tv' => {
5096 
      'connections' => {
5097 
        'reg13_tv' => '.reg13_tv',
5098 
      },
5099 
      'entity' => {
5100 
        'attributes' => {
5101 
          'entityAlreadyNetlisted' => 1,
5102 
          'isGateway' => 1,
5103 
          'is_floating_block' => 1,
5104 
        },
5105 
        'entityName' => 'reg13_tv',
5106 
        'ports' => {
5107 
          'reg13_tv' => {
5108 
            'attributes' => {
5109 
              'bin_pt' => 0,
5110 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
5111 
              'is_floating_block' => 1,
5112 
              'is_gateway_port' => 1,
5113 
              'must_be_hdl_vector' => 1,
5114 
              'period' => 1,
5115 
              'port_id' => 0,
5116 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
5117 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
5118 
              'timingConstraint' => 'none',
5119 
              'type' => 'Bool',
5120 
            },
5121 
            'direction' => 'out',
5122 
            'hdlType' => 'std_logic',
5123 
            'width' => 1,
5124 
          },
5125 
        },
5126 
      },
5127 
      'entityName' => 'reg13_tv',
5128 
    },
5129 
    'reg14_rd' => {
5130 
      'connections' => {
5131 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5132 
      },
5133 
      'entity' => {
5134 
        'attributes' => {
5135 
          'entityAlreadyNetlisted' => 1,
5136 
          'isGateway' => 1,
5137 
          'is_floating_block' => 1,
5138 
        },
5139 
        'entityName' => 'reg14_rd',
5140 
        'ports' => {
5141 
          'reg14_rd' => {
5142 
            'attributes' => {
5143 
              'bin_pt' => 0,
5144 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
5145 
              'is_floating_block' => 1,
5146 
              'is_gateway_port' => 1,
5147 
              'must_be_hdl_vector' => 1,
5148 
              'period' => 1,
5149 
              'port_id' => 0,
5150 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
5151 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
5152 
              'timingConstraint' => 'none',
5153 
              'type' => 'UFix_32_0',
5154 
            },
5155 
            'direction' => 'in',
5156 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5157 
            'width' => 32,
5158 
          },
5159 
        },
5160 
      },
5161 
      'entityName' => 'reg14_rd',
5162 
    },
5163 
    'reg14_rv' => {
5164 
      'connections' => {
5165 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5166 
      },
5167 
      'entity' => {
5168 
        'attributes' => {
5169 
          'entityAlreadyNetlisted' => 1,
5170 
          'isGateway' => 1,
5171 
          'is_floating_block' => 1,
5172 
        },
5173 
        'entityName' => 'reg14_rv',
5174 
        'ports' => {
5175 
          'reg14_rv' => {
5176 
            'attributes' => {
5177 
              'bin_pt' => 0,
5178 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
5179 
              'is_floating_block' => 1,
5180 
              'is_gateway_port' => 1,
5181 
              'must_be_hdl_vector' => 1,
5182 
              'period' => 1,
5183 
              'port_id' => 0,
5184 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
5185 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
5186 
              'timingConstraint' => 'none',
5187 
              'type' => 'UFix_1_0',
5188 
            },
5189 
            'direction' => 'in',
5190 
            'hdlType' => 'std_logic',
5191 
            'width' => 1,
5192 
          },
5193 
        },
5194 
      },
5195 
      'entityName' => 'reg14_rv',
5196 
    },
5197 
    'reg14_td' => {
5198 
      'connections' => {
5199 
        'reg14_td' => '.reg14_td',
5200 
      },
5201 
      'entity' => {
5202 
        'attributes' => {
5203 
          'entityAlreadyNetlisted' => 1,
5204 
          'isGateway' => 1,
5205 
          'is_floating_block' => 1,
5206 
        },
5207 
        'entityName' => 'reg14_td',
5208 
        'ports' => {
5209 
          'reg14_td' => {
5210 
            'attributes' => {
5211 
              'bin_pt' => 0,
5212 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
5213 
              'is_floating_block' => 1,
5214 
              'is_gateway_port' => 1,
5215 
              'must_be_hdl_vector' => 1,
5216 
              'period' => 1,
5217 
              'port_id' => 0,
5218 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
5219 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
5220 
              'timingConstraint' => 'none',
5221 
              'type' => 'UFix_32_0',
5222 
            },
5223 
            'direction' => 'out',
5224 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5225 
            'width' => 32,
5226 
          },
5227 
        },
5228 
      },
5229 
      'entityName' => 'reg14_td',
5230 
    },
5231 
    'reg14_tv' => {
5232 
      'connections' => {
5233 
        'reg14_tv' => '.reg14_tv',
5234 
      },
5235 
      'entity' => {
5236 
        'attributes' => {
5237 
          'entityAlreadyNetlisted' => 1,
5238 
          'isGateway' => 1,
5239 
          'is_floating_block' => 1,
5240 
        },
5241 
        'entityName' => 'reg14_tv',
5242 
        'ports' => {
5243 
          'reg14_tv' => {
5244 
            'attributes' => {
5245 
              'bin_pt' => 0,
5246 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5247 
              'is_floating_block' => 1,
5248 
              'is_gateway_port' => 1,
5249 
              'must_be_hdl_vector' => 1,
5250 
              'period' => 1,
5251 
              'port_id' => 0,
5252 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5253 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5254 
              'timingConstraint' => 'none',
5255 
              'type' => 'Bool',
5256 
            },
5257 
            'direction' => 'out',
5258 
            'hdlType' => 'std_logic',
5259 
            'width' => 1,
5260 
          },
5261 
        },
5262 
      },
5263 
      'entityName' => 'reg14_tv',
5264 
    },
5265 
    'sysgen_dut' => {
5266 
      'connections' => {
5267 
        'clk' => '.clk',
5268 
        'debug_in_1i' => '.debug_in_1i',
5269 
        'debug_in_2i' => '.debug_in_2i',
5270 
        'debug_in_3i' => '.debug_in_3i',
5271 
        'debug_in_4i' => '.debug_in_4i',
5272 
        'dma_host2board_busy' => '.dma_host2board_busy',
5273 
        'dma_host2board_done' => '.dma_host2board_done',
5274 
        'from_register10_data_out' => 'from_register10.data_out',
5275 
        'from_register11_data_out' => 'from_register11.data_out',
5276 
        'from_register12_data_out' => 'from_register12.data_out',
5277 
        'from_register13_data_out' => 'from_register13.data_out',
5278 
        'from_register14_data_out' => 'from_register14.data_out',
5279 
        'from_register15_data_out' => 'from_register15.data_out',
5280 
        'from_register16_data_out' => 'from_register16.data_out',
5281 
        'from_register17_data_out' => 'from_register17.data_out',
5282 
        'from_register18_data_out' => 'from_register18.data_out',
5283 
        'from_register19_data_out' => 'from_register19.data_out',
5284 
        'from_register1_data_out' => 'from_register1.data_out',
5285 
        'from_register20_data_out' => 'from_register20.data_out',
5286 
        'from_register21_data_out' => 'from_register21.data_out',
5287 
        'from_register22_data_out' => 'from_register22.data_out',
5288 
        'from_register23_data_out' => 'from_register23.data_out',
5289 
        'from_register24_data_out' => 'from_register24.data_out',
5290 
        'from_register25_data_out' => 'from_register25.data_out',
5291 
        'from_register26_data_out' => 'from_register26.data_out',
5292 
        'from_register27_data_out' => 'from_register27.data_out',
5293 
        'from_register28_data_out' => 'from_register28.data_out',
5294 
        'from_register2_data_out' => 'from_register2.data_out',
5295 
        'from_register3_data_out' => 'from_register3.data_out',
5296 
        'from_register4_data_out' => 'from_register4.data_out',
5297 
        'from_register5_data_out' => 'from_register5.data_out',
5298 
        'from_register6_data_out' => 'from_register6.data_out',
5299 
        'from_register7_data_out' => 'from_register7.data_out',
5300 
        'from_register8_data_out' => 'from_register8.data_out',
5301 
        'from_register9_data_out' => 'from_register9.data_out',
5302 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5303 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5304 
        'reg01_td' => '.reg01_td',
5305 
        'reg01_tv' => '.reg01_tv',
5306 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5307 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5308 
        'reg02_td' => '.reg02_td',
5309 
        'reg02_tv' => '.reg02_tv',
5310 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5311 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5312 
        'reg03_td' => '.reg03_td',
5313 
        'reg03_tv' => '.reg03_tv',
5314 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5315 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5316 
        'reg04_td' => '.reg04_td',
5317 
        'reg04_tv' => '.reg04_tv',
5318 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5319 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5320 
        'reg05_td' => '.reg05_td',
5321 
        'reg05_tv' => '.reg05_tv',
5322 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5323 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5324 
        'reg06_td' => '.reg06_td',
5325 
        'reg06_tv' => '.reg06_tv',
5326 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5327 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5328 
        'reg07_td' => '.reg07_td',
5329 
        'reg07_tv' => '.reg07_tv',
5330 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5331 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5332 
        'reg08_td' => '.reg08_td',
5333 
        'reg08_tv' => '.reg08_tv',
5334 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5335 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5336 
        'reg09_td' => '.reg09_td',
5337 
        'reg09_tv' => '.reg09_tv',
5338 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5339 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5340 
        'reg10_td' => '.reg10_td',
5341 
        'reg10_tv' => '.reg10_tv',
5342 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5343 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5344 
        'reg11_td' => '.reg11_td',
5345 
        'reg11_tv' => '.reg11_tv',
5346 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5347 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5348 
        'reg12_td' => '.reg12_td',
5349 
        'reg12_tv' => '.reg12_tv',
5350 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5351 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5352 
        'reg13_td' => '.reg13_td',
5353 
        'reg13_tv' => '.reg13_tv',
5354 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5355 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5356 
        'reg14_td' => '.reg14_td',
5357 
        'reg14_tv' => '.reg14_tv',
5358 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5359 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5360 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5361 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5362 
        'to_register10_dout' => 'to_register10.dout',
5363 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5364 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5365 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5366 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5367 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5368 
        'to_register11_dout' => 'to_register11.dout',
5369 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5370 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5371 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5372 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5373 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5374 
        'to_register12_dout' => 'to_register12.dout',
5375 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5376 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5377 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5378 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5379 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5380 
        'to_register13_dout' => 'to_register13.dout',
5381 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5382 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5383 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5384 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5385 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5386 
        'to_register14_dout' => 'to_register14.dout',
5387 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5388 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5389 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5390 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5391 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5392 
        'to_register15_dout' => 'to_register15.dout',
5393 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5394 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5395 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5396 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5397 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5398 
        'to_register16_dout' => 'to_register16.dout',
5399 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5400 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5401 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5402 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5403 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5404 
        'to_register17_dout' => 'to_register17.dout',
5405 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5406 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5407 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5408 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5409 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5410 
        'to_register18_dout' => 'to_register18.dout',
5411 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5412 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5413 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5414 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5415 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5416 
        'to_register19_dout' => 'to_register19.dout',
5417 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5418 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5419 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5420 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5421 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5422 
        'to_register1_dout' => 'to_register1.dout',
5423 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5424 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5425 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5426 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5427 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5428 
        'to_register20_dout' => 'to_register20.dout',
5429 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5430 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5431 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5432 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5433 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5434 
        'to_register21_dout' => 'to_register21.dout',
5435 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5436 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5437 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5438 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5439 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5440 
        'to_register22_dout' => 'to_register22.dout',
5441 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5442 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5443 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5444 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5445 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5446 
        'to_register23_dout' => 'to_register23.dout',
5447 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5448 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5449 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5450 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5451 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5452 
        'to_register24_dout' => 'to_register24.dout',
5453 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5454 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5455 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5456 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5457 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5458 
        'to_register25_dout' => 'to_register25.dout',
5459 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5460 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5461 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5462 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5463 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5464 
        'to_register26_dout' => 'to_register26.dout',
5465 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5466 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5467 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5468 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5469 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5470 
        'to_register27_dout' => 'to_register27.dout',
5471 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5472 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5473 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5474 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5475 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5476 
        'to_register28_dout' => 'to_register28.dout',
5477 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5478 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5479 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5480 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5481 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5482 
        'to_register29_dout' => 'to_register29.dout',
5483 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5484 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5485 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5486 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5487 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5488 
        'to_register2_dout' => 'to_register2.dout',
5489 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5490 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5491 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5492 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5493 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5494 
        'to_register30_dout' => 'to_register30.dout',
5495 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5496 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5497 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5498 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5499 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5500 
        'to_register31_dout' => 'to_register31.dout',
5501 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5502 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5503 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5504 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5505 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5506 
        'to_register32_dout' => 'to_register32.dout',
5507 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5508 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5509 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5510 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5511 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5512 
        'to_register33_dout' => 'to_register33.dout',
5513 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5514 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5515 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5516 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5517 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5518 
        'to_register34_dout' => 'to_register34.dout',
5519 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5520 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5521 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5522 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5523 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5524 
        'to_register3_dout' => 'to_register3.dout',
5525 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5526 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5527 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5528 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5529 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5530 
        'to_register4_dout' => 'to_register4.dout',
5531 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5532 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5533 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5534 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5535 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5536 
        'to_register5_dout' => 'to_register5.dout',
5537 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5538 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5539 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5540 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5541 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5542 
        'to_register6_dout' => 'to_register6.dout',
5543 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5544 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5545 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5546 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5547 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5548 
        'to_register7_dout' => 'to_register7.dout',
5549 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5550 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5551 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5552 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5553 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5554 
        'to_register8_dout' => 'to_register8.dout',
5555 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5556 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5557 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5558 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5559 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5560 
        'to_register9_dout' => 'to_register9.dout',
5561 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5562 
      },
5563 
      'entity' => {
5564 
        'attributes' => {
5565 
          'entityAlreadyNetlisted' => 1,
5566 
          'hdlArchAttributes' => [
5567 
          ],
5568 
          'hdlEntityAttributes' => [
5569 
          ],
5570 
          'isClkWrapper' => 1,
5571 
        },
5572 
        'connections' => {
5573 
          'clk' => 'clkNet',
5574 
          'debug_in_1i' => 'debug_in_1i_net',
5575 
          'debug_in_2i' => 'debug_in_2i_net',
5576 
          'debug_in_3i' => 'debug_in_3i_net',
5577 
          'debug_in_4i' => 'debug_in_4i_net',
5578 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5579 
          'dma_host2board_done' => 'dma_host2board_done_net',
5580 
          'from_register10_data_out' => 'from_register10_data_out_net',
5581 
          'from_register11_data_out' => 'from_register11_data_out_net',
5582 
          'from_register12_data_out' => 'from_register12_data_out_net',
5583 
          'from_register13_data_out' => 'from_register13_data_out_net',
5584 
          'from_register14_data_out' => 'from_register14_data_out_net',
5585 
          'from_register15_data_out' => 'from_register15_data_out_net',
5586 
          'from_register16_data_out' => 'from_register16_data_out_net',
5587 
          'from_register17_data_out' => 'from_register17_data_out_net',
5588 
          'from_register18_data_out' => 'from_register18_data_out_net',
5589 
          'from_register19_data_out' => 'from_register19_data_out_net',
5590 
          'from_register1_data_out' => 'from_register1_data_out_net',
5591 
          'from_register20_data_out' => 'from_register20_data_out_net',
5592 
          'from_register21_data_out' => 'from_register21_data_out_net',
5593 
          'from_register22_data_out' => 'from_register22_data_out_net',
5594 
          'from_register23_data_out' => 'from_register23_data_out_net',
5595 
          'from_register24_data_out' => 'from_register24_data_out_net',
5596 
          'from_register25_data_out' => 'from_register25_data_out_net',
5597 
          'from_register26_data_out' => 'from_register26_data_out_net',
5598 
          'from_register27_data_out' => 'from_register27_data_out_net',
5599 
          'from_register28_data_out' => 'from_register28_data_out_net',
5600 
          'from_register2_data_out' => 'from_register2_data_out_net',
5601 
          'from_register3_data_out' => 'from_register3_data_out_net',
5602 
          'from_register4_data_out' => 'from_register4_data_out_net',
5603 
          'from_register5_data_out' => 'from_register5_data_out_net',
5604 
          'from_register6_data_out' => 'from_register6_data_out_net',
5605 
          'from_register7_data_out' => 'from_register7_data_out_net',
5606 
          'from_register8_data_out' => 'from_register8_data_out_net',
5607 
          'from_register9_data_out' => 'from_register9_data_out_net',
5608 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5609 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5610 
          'reg01_td' => 'reg01_td_net',
5611 
          'reg01_tv' => 'reg01_tv_net',
5612 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5613 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5614 
          'reg02_td' => 'reg02_td_net',
5615 
          'reg02_tv' => 'reg02_tv_net',
5616 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5617 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5618 
          'reg03_td' => 'reg03_td_net',
5619 
          'reg03_tv' => 'reg03_tv_net',
5620 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5621 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5622 
          'reg04_td' => 'reg04_td_net',
5623 
          'reg04_tv' => 'reg04_tv_net',
5624 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5625 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5626 
          'reg05_td' => 'reg05_td_net',
5627 
          'reg05_tv' => 'reg05_tv_net',
5628 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5629 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5630 
          'reg06_td' => 'reg06_td_net',
5631 
          'reg06_tv' => 'reg06_tv_net',
5632 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5633 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5634 
          'reg07_td' => 'reg07_td_net',
5635 
          'reg07_tv' => 'reg07_tv_net',
5636 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5637 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5638 
          'reg08_td' => 'reg08_td_net',
5639 
          'reg08_tv' => 'reg08_tv_net',
5640 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5641 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5642 
          'reg09_td' => 'reg09_td_net',
5643 
          'reg09_tv' => 'reg09_tv_net',
5644 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5645 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5646 
          'reg10_td' => 'reg10_td_net',
5647 
          'reg10_tv' => 'reg10_tv_net',
5648 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5649 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5650 
          'reg11_td' => 'reg11_td_net',
5651 
          'reg11_tv' => 'reg11_tv_net',
5652 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5653 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5654 
          'reg12_td' => 'reg12_td_net',
5655 
          'reg12_tv' => 'reg12_tv_net',
5656 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5657 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5658 
          'reg13_td' => 'reg13_td_net',
5659 
          'reg13_tv' => 'reg13_tv_net',
5660 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5661 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5662 
          'reg14_td' => 'reg14_td_net',
5663 
          'reg14_tv' => 'reg14_tv_net',
5664 
          'to_register10_ce' => 'ce_1_sg',
5665 
          'to_register10_clk' => 'clk_1_sg',
5666 
          'to_register10_clr' => [
5667 
            'constant',
5668 
            '\'0\'',
5669 
          ],
5670 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5671 
          'to_register10_dout' => 'to_register10_dout_net',
5672 
          'to_register10_en' => 'constant5_op_net_x1',
5673 
          'to_register11_ce' => 'ce_1_sg',
5674 
          'to_register11_clk' => 'clk_1_sg',
5675 
          'to_register11_clr' => [
5676 
            'constant',
5677 
            '\'0\'',
5678 
          ],
5679 
          'to_register11_data_in' => 'reg04_td_net_x0',
5680 
          'to_register11_dout' => 'to_register11_dout_net',
5681 
          'to_register11_en' => 'constant5_op_net_x2',
5682 
          'to_register12_ce' => 'ce_1_sg',
5683 
          'to_register12_clk' => 'clk_1_sg',
5684 
          'to_register12_clr' => [
5685 
            'constant',
5686 
            '\'0\'',
5687 
          ],
5688 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5689 
          'to_register12_dout' => 'to_register12_dout_net',
5690 
          'to_register12_en' => 'constant5_op_net_x3',
5691 
          'to_register13_ce' => 'ce_1_sg',
5692 
          'to_register13_clk' => 'clk_1_sg',
5693 
          'to_register13_clr' => [
5694 
            'constant',
5695 
            '\'0\'',
5696 
          ],
5697 
          'to_register13_data_in' => 'reg05_td_net_x0',
5698 
          'to_register13_dout' => 'to_register13_dout_net',
5699 
          'to_register13_en' => 'constant5_op_net_x4',
5700 
          'to_register14_ce' => 'ce_1_sg',
5701 
          'to_register14_clk' => 'clk_1_sg',
5702 
          'to_register14_clr' => [
5703 
            'constant',
5704 
            '\'0\'',
5705 
          ],
5706 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5707 
          'to_register14_dout' => 'to_register14_dout_net',
5708 
          'to_register14_en' => 'constant5_op_net_x5',
5709 
          'to_register15_ce' => 'ce_1_sg',
5710 
          'to_register15_clk' => 'clk_1_sg',
5711 
          'to_register15_clr' => [
5712 
            'constant',
5713 
            '\'0\'',
5714 
          ],
5715 
          'to_register15_data_in' => 'reg06_td_net_x0',
5716 
          'to_register15_dout' => 'to_register15_dout_net',
5717 
          'to_register15_en' => 'constant5_op_net_x6',
5718 
          'to_register16_ce' => 'ce_1_sg',
5719 
          'to_register16_clk' => 'clk_1_sg',
5720 
          'to_register16_clr' => [
5721 
            'constant',
5722 
            '\'0\'',
5723 
          ],
5724 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5725 
          'to_register16_dout' => 'to_register16_dout_net',
5726 
          'to_register16_en' => 'constant5_op_net_x7',
5727 
          'to_register17_ce' => 'ce_1_sg',
5728 
          'to_register17_clk' => 'clk_1_sg',
5729 
          'to_register17_clr' => [
5730 
            'constant',
5731 
            '\'0\'',
5732 
          ],
5733 
          'to_register17_data_in' => 'reg07_td_net_x0',
5734 
          'to_register17_dout' => 'to_register17_dout_net',
5735 
          'to_register17_en' => 'constant5_op_net_x8',
5736 
          'to_register18_ce' => 'ce_1_sg',
5737 
          'to_register18_clk' => 'clk_1_sg',
5738 
          'to_register18_clr' => [
5739 
            'constant',
5740 
            '\'0\'',
5741 
          ],
5742 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5743 
          'to_register18_dout' => 'to_register18_dout_net',
5744 
          'to_register18_en' => 'constant5_op_net_x9',
5745 
          'to_register19_ce' => 'ce_1_sg',
5746 
          'to_register19_clk' => 'clk_1_sg',
5747 
          'to_register19_clr' => [
5748 
            'constant',
5749 
            '\'0\'',
5750 
          ],
5751 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5752 
          'to_register19_dout' => 'to_register19_dout_net',
5753 
          'to_register19_en' => 'constant5_op_net_x10',
5754 
          'to_register1_ce' => 'ce_1_sg',
5755 
          'to_register1_clk' => 'clk_1_sg',
5756 
          'to_register1_clr' => [
5757 
            'constant',
5758 
            '\'0\'',
5759 
          ],
5760 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5761 
          'to_register1_dout' => 'to_register1_dout_net',
5762 
          'to_register1_en' => 'constant5_op_net_x0',
5763 
          'to_register20_ce' => 'ce_1_sg',
5764 
          'to_register20_clk' => 'clk_1_sg',
5765 
          'to_register20_clr' => [
5766 
            'constant',
5767 
            '\'0\'',
5768 
          ],
5769 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5770 
          'to_register20_dout' => 'to_register20_dout_net',
5771 
          'to_register20_en' => 'constant5_op_net_x12',
5772 
          'to_register21_ce' => 'ce_1_sg',
5773 
          'to_register21_clk' => 'clk_1_sg',
5774 
          'to_register21_clr' => [
5775 
            'constant',
5776 
            '\'0\'',
5777 
          ],
5778 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5779 
          'to_register21_dout' => 'to_register21_dout_net',
5780 
          'to_register21_en' => 'constant1_op_net_x0',
5781 
          'to_register22_ce' => 'ce_1_sg',
5782 
          'to_register22_clk' => 'clk_1_sg',
5783 
          'to_register22_clr' => [
5784 
            'constant',
5785 
            '\'0\'',
5786 
          ],
5787 
          'to_register22_data_in' => 'reg09_td_net_x0',
5788 
          'to_register22_dout' => 'to_register22_dout_net',
5789 
          'to_register22_en' => 'constant1_op_net_x1',
5790 
          'to_register23_ce' => 'ce_1_sg',
5791 
          'to_register23_clk' => 'clk_1_sg',
5792 
          'to_register23_clr' => [
5793 
            'constant',
5794 
            '\'0\'',
5795 
          ],
5796 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5797 
          'to_register23_dout' => 'to_register23_dout_net',
5798 
          'to_register23_en' => 'constant1_op_net_x2',
5799 
          'to_register24_ce' => 'ce_1_sg',
5800 
          'to_register24_clk' => 'clk_1_sg',
5801 
          'to_register24_clr' => [
5802 
            'constant',
5803 
            '\'0\'',
5804 
          ],
5805 
          'to_register24_data_in' => 'reg10_td_net_x0',
5806 
          'to_register24_dout' => 'to_register24_dout_net',
5807 
          'to_register24_en' => 'constant1_op_net_x3',
5808 
          'to_register25_ce' => 'ce_1_sg',
5809 
          'to_register25_clk' => 'clk_1_sg',
5810 
          'to_register25_clr' => [
5811 
            'constant',
5812 
            '\'0\'',
5813 
          ],
5814 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5815 
          'to_register25_dout' => 'to_register25_dout_net',
5816 
          'to_register25_en' => 'constant1_op_net_x4',
5817 
          'to_register26_ce' => 'ce_1_sg',
5818 
          'to_register26_clk' => 'clk_1_sg',
5819 
          'to_register26_clr' => [
5820 
            'constant',
5821 
            '\'0\'',
5822 
          ],
5823 
          'to_register26_data_in' => 'reg08_td_net_x0',
5824 
          'to_register26_dout' => 'to_register26_dout_net',
5825 
          'to_register26_en' => 'constant1_op_net_x5',
5826 
          'to_register27_ce' => 'ce_1_sg',
5827 
          'to_register27_clk' => 'clk_1_sg',
5828 
          'to_register27_clr' => [
5829 
            'constant',
5830 
            '\'0\'',
5831 
          ],
5832 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5833 
          'to_register27_dout' => 'to_register27_dout_net',
5834 
          'to_register27_en' => 'constant1_op_net_x6',
5835 
          'to_register28_ce' => 'ce_1_sg',
5836 
          'to_register28_clk' => 'clk_1_sg',
5837 
          'to_register28_clr' => [
5838 
            'constant',
5839 
            '\'0\'',
5840 
          ],
5841 
          'to_register28_data_in' => 'reg11_td_net_x0',
5842 
          'to_register28_dout' => 'to_register28_dout_net',
5843 
          'to_register28_en' => 'constant1_op_net_x7',
5844 
          'to_register29_ce' => 'ce_1_sg',
5845 
          'to_register29_clk' => 'clk_1_sg',
5846 
          'to_register29_clr' => [
5847 
            'constant',
5848 
            '\'0\'',
5849 
          ],
5850 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5851 
          'to_register29_dout' => 'to_register29_dout_net',
5852 
          'to_register29_en' => 'constant1_op_net_x8',
5853 
          'to_register2_ce' => 'ce_1_sg',
5854 
          'to_register2_clk' => 'clk_1_sg',
5855 
          'to_register2_clr' => [
5856 
            'constant',
5857 
            '\'0\'',
5858 
          ],
5859 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5860 
          'to_register2_dout' => 'to_register2_dout_net',
5861 
          'to_register2_en' => 'constant5_op_net_x11',
5862 
          'to_register30_ce' => 'ce_1_sg',
5863 
          'to_register30_clk' => 'clk_1_sg',
5864 
          'to_register30_clr' => [
5865 
            'constant',
5866 
            '\'0\'',
5867 
          ],
5868 
          'to_register30_data_in' => 'reg12_td_net_x0',
5869 
          'to_register30_dout' => 'to_register30_dout_net',
5870 
          'to_register30_en' => 'constant1_op_net_x9',
5871 
          'to_register31_ce' => 'ce_1_sg',
5872 
          'to_register31_clk' => 'clk_1_sg',
5873 
          'to_register31_clr' => [
5874 
            'constant',
5875 
            '\'0\'',
5876 
          ],
5877 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5878 
          'to_register31_dout' => 'to_register31_dout_net',
5879 
          'to_register31_en' => 'constant1_op_net_x10',
5880 
          'to_register32_ce' => 'ce_1_sg',
5881 
          'to_register32_clk' => 'clk_1_sg',
5882 
          'to_register32_clr' => [
5883 
            'constant',
5884 
            '\'0\'',
5885 
          ],
5886 
          'to_register32_data_in' => 'reg13_td_net_x0',
5887 
          'to_register32_dout' => 'to_register32_dout_net',
5888 
          'to_register32_en' => 'constant1_op_net_x11',
5889 
          'to_register33_ce' => 'ce_1_sg',
5890 
          'to_register33_clk' => 'clk_1_sg',
5891 
          'to_register33_clr' => [
5892 
            'constant',
5893 
            '\'0\'',
5894 
          ],
5895 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5896 
          'to_register33_dout' => 'to_register33_dout_net',
5897 
          'to_register33_en' => 'constant1_op_net_x12',
5898 
          'to_register34_ce' => 'ce_1_sg',
5899 
          'to_register34_clk' => 'clk_1_sg',
5900 
          'to_register34_clr' => [
5901 
            'constant',
5902 
            '\'0\'',
5903 
          ],
5904 
          'to_register34_data_in' => 'reg14_td_net_x0',
5905 
          'to_register34_dout' => 'to_register34_dout_net',
5906 
          'to_register34_en' => 'constant1_op_net_x13',
5907 
          'to_register3_ce' => 'ce_1_sg',
5908 
          'to_register3_clk' => 'clk_1_sg',
5909 
          'to_register3_clr' => [
5910 
            'constant',
5911 
            '\'0\'',
5912 
          ],
5913 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5914 
          'to_register3_dout' => 'to_register3_dout_net',
5915 
          'to_register3_en' => 'constant5_op_net_x13',
5916 
          'to_register4_ce' => 'ce_1_sg',
5917 
          'to_register4_clk' => 'clk_1_sg',
5918 
          'to_register4_clr' => [
5919 
            'constant',
5920 
            '\'0\'',
5921 
          ],
5922 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5923 
          'to_register4_dout' => 'to_register4_dout_net',
5924 
          'to_register4_en' => 'constant5_op_net_x14',
5925 
          'to_register5_ce' => 'ce_1_sg',
5926 
          'to_register5_clk' => 'clk_1_sg',
5927 
          'to_register5_clr' => [
5928 
            'constant',
5929 
            '\'0\'',
5930 
          ],
5931 
          'to_register5_data_in' => 'reg02_td_net_x0',
5932 
          'to_register5_dout' => 'to_register5_dout_net',
5933 
          'to_register5_en' => 'constant5_op_net_x15',
5934 
          'to_register6_ce' => 'ce_1_sg',
5935 
          'to_register6_clk' => 'clk_1_sg',
5936 
          'to_register6_clr' => [
5937 
            'constant',
5938 
            '\'0\'',
5939 
          ],
5940 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5941 
          'to_register6_dout' => 'to_register6_dout_net',
5942 
          'to_register6_en' => 'constant5_op_net_x16',
5943 
          'to_register7_ce' => 'ce_1_sg',
5944 
          'to_register7_clk' => 'clk_1_sg',
5945 
          'to_register7_clr' => [
5946 
            'constant',
5947 
            '\'0\'',
5948 
          ],
5949 
          'to_register7_data_in' => 'reg01_td_net_x0',
5950 
          'to_register7_dout' => 'to_register7_dout_net',
5951 
          'to_register7_en' => 'constant5_op_net_x17',
5952 
          'to_register8_ce' => 'ce_1_sg',
5953 
          'to_register8_clk' => 'clk_1_sg',
5954 
          'to_register8_clr' => [
5955 
            'constant',
5956 
            '\'0\'',
5957 
          ],
5958 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5959 
          'to_register8_dout' => 'to_register8_dout_net',
5960 
          'to_register8_en' => 'constant5_op_net_x18',
5961 
          'to_register9_ce' => 'ce_1_sg',
5962 
          'to_register9_clk' => 'clk_1_sg',
5963 
          'to_register9_clr' => [
5964 
            'constant',
5965 
            '\'0\'',
5966 
          ],
5967 
          'to_register9_data_in' => 'reg03_td_net_x0',
5968 
          'to_register9_dout' => 'to_register9_dout_net',
5969 
          'to_register9_en' => 'constant5_op_net_x19',
5970 
        },
5971 
        'entityName' => 'inout_logic_cw',
5972 
        'nets' => {
5973 
          'ce_1_sg' => {
5974 
            'attributes' => {
5975 
              'hdlNetAttributes' => [
5976 
                [
5977 
                  'MAX_FANOUT',
5978 
                  'string',
5979 
                  '"REDUCE"',
5980 
                ],
5981 
              ],
5982 
            },
5983 
            'hdlType' => 'std_logic',
5984 
            'width' => 1,
5985 
          },
5986 
          'clkNet' => {
5987 
            'attributes' => {
5988 
              'hdlNetAttributes' => [
5989 
              ],
5990 
            },
5991 
            'hdlType' => 'std_logic',
5992 
            'width' => 1,
5993 
          },
5994 
          'clk_1_sg' => {
5995 
            'attributes' => {
5996 
              'hdlNetAttributes' => [
5997 
              ],
5998 
            },
5999 
            'hdlType' => 'std_logic',
6000 
            'width' => 1,
6001 
          },
6002 
          'constant1_op_net_x0' => {
6003 
            'attributes' => {
6004 
              'hdlNetAttributes' => [
6005 
              ],
6006 
            },
6007 
            'hdlType' => 'std_logic',
6008 
            'width' => 1,
6009 
          },
6010 
          'constant1_op_net_x1' => {
6011 
            'attributes' => {
6012 
              'hdlNetAttributes' => [
6013 
              ],
6014 
            },
6015 
            'hdlType' => 'std_logic',
6016 
            'width' => 1,
6017 
          },
6018 
          'constant1_op_net_x10' => {
6019 
            'attributes' => {
6020 
              'hdlNetAttributes' => [
6021 
              ],
6022 
            },
6023 
            'hdlType' => 'std_logic',
6024 
            'width' => 1,
6025 
          },
6026 
          'constant1_op_net_x11' => {
6027 
            'attributes' => {
6028 
              'hdlNetAttributes' => [
6029 
              ],
6030 
            },
6031 
            'hdlType' => 'std_logic',
6032 
            'width' => 1,
6033 
          },
6034 
          'constant1_op_net_x12' => {
6035 
            'attributes' => {
6036 
              'hdlNetAttributes' => [
6037 
              ],
6038 
            },
6039 
            'hdlType' => 'std_logic',
6040 
            'width' => 1,
6041 
          },
6042 
          'constant1_op_net_x13' => {
6043 
            'attributes' => {
6044 
              'hdlNetAttributes' => [
6045 
              ],
6046 
            },
6047 
            'hdlType' => 'std_logic',
6048 
            'width' => 1,
6049 
          },
6050 
          'constant1_op_net_x2' => {
6051 
            'attributes' => {
6052 
              'hdlNetAttributes' => [
6053 
              ],
6054 
            },
6055 
            'hdlType' => 'std_logic',
6056 
            'width' => 1,
6057 
          },
6058 
          'constant1_op_net_x3' => {
6059 
            'attributes' => {
6060 
              'hdlNetAttributes' => [
6061 
              ],
6062 
            },
6063 
            'hdlType' => 'std_logic',
6064 
            'width' => 1,
6065 
          },
6066 
          'constant1_op_net_x4' => {
6067 
            'attributes' => {
6068 
              'hdlNetAttributes' => [
6069 
              ],
6070 
            },
6071 
            'hdlType' => 'std_logic',
6072 
            'width' => 1,
6073 
          },
6074 
          'constant1_op_net_x5' => {
6075 
            'attributes' => {
6076 
              'hdlNetAttributes' => [
6077 
              ],
6078 
            },
6079 
            'hdlType' => 'std_logic',
6080 
            'width' => 1,
6081 
          },
6082 
          'constant1_op_net_x6' => {
6083 
            'attributes' => {
6084 
              'hdlNetAttributes' => [
6085 
              ],
6086 
            },
6087 
            'hdlType' => 'std_logic',
6088 
            'width' => 1,
6089 
          },
6090 
          'constant1_op_net_x7' => {
6091 
            'attributes' => {
6092 
              'hdlNetAttributes' => [
6093 
              ],
6094 
            },
6095 
            'hdlType' => 'std_logic',
6096 
            'width' => 1,
6097 
          },
6098 
          'constant1_op_net_x8' => {
6099 
            'attributes' => {
6100 
              'hdlNetAttributes' => [
6101 
              ],
6102 
            },
6103 
            'hdlType' => 'std_logic',
6104 
            'width' => 1,
6105 
          },
6106 
          'constant1_op_net_x9' => {
6107 
            'attributes' => {
6108 
              'hdlNetAttributes' => [
6109 
              ],
6110 
            },
6111 
            'hdlType' => 'std_logic',
6112 
            'width' => 1,
6113 
          },
6114 
          'constant5_op_net_x0' => {
6115 
            'attributes' => {
6116 
              'hdlNetAttributes' => [
6117 
              ],
6118 
            },
6119 
            'hdlType' => 'std_logic',
6120 
            'width' => 1,
6121 
          },
6122 
          'constant5_op_net_x1' => {
6123 
            'attributes' => {
6124 
              'hdlNetAttributes' => [
6125 
              ],
6126 
            },
6127 
            'hdlType' => 'std_logic',
6128 
            'width' => 1,
6129 
          },
6130 
          'constant5_op_net_x10' => {
6131 
            'attributes' => {
6132 
              'hdlNetAttributes' => [
6133 
              ],
6134 
            },
6135 
            'hdlType' => 'std_logic',
6136 
            'width' => 1,
6137 
          },
6138 
          'constant5_op_net_x11' => {
6139 
            'attributes' => {
6140 
              'hdlNetAttributes' => [
6141 
              ],
6142 
            },
6143 
            'hdlType' => 'std_logic',
6144 
            'width' => 1,
6145 
          },
6146 
          'constant5_op_net_x12' => {
6147 
            'attributes' => {
6148 
              'hdlNetAttributes' => [
6149 
              ],
6150 
            },
6151 
            'hdlType' => 'std_logic',
6152 
            'width' => 1,
6153 
          },
6154 
          'constant5_op_net_x13' => {
6155 
            'attributes' => {
6156 
              'hdlNetAttributes' => [
6157 
              ],
6158 
            },
6159 
            'hdlType' => 'std_logic',
6160 
            'width' => 1,
6161 
          },
6162 
          'constant5_op_net_x14' => {
6163 
            'attributes' => {
6164 
              'hdlNetAttributes' => [
6165 
              ],
6166 
            },
6167 
            'hdlType' => 'std_logic',
6168 
            'width' => 1,
6169 
          },
6170 
          'constant5_op_net_x15' => {
6171 
            'attributes' => {
6172 
              'hdlNetAttributes' => [
6173 
              ],
6174 
            },
6175 
            'hdlType' => 'std_logic',
6176 
            'width' => 1,
6177 
          },
6178 
          'constant5_op_net_x16' => {
6179 
            'attributes' => {
6180 
              'hdlNetAttributes' => [
6181 
              ],
6182 
            },
6183 
            'hdlType' => 'std_logic',
6184 
            'width' => 1,
6185 
          },
6186 
          'constant5_op_net_x17' => {
6187 
            'attributes' => {
6188 
              'hdlNetAttributes' => [
6189 
              ],
6190 
            },
6191 
            'hdlType' => 'std_logic',
6192 
            'width' => 1,
6193 
          },
6194 
          'constant5_op_net_x18' => {
6195 
            'attributes' => {
6196 
              'hdlNetAttributes' => [
6197 
              ],
6198 
            },
6199 
            'hdlType' => 'std_logic',
6200 
            'width' => 1,
6201 
          },
6202 
          'constant5_op_net_x19' => {
6203 
            'attributes' => {
6204 
              'hdlNetAttributes' => [
6205 
              ],
6206 
            },
6207 
            'hdlType' => 'std_logic',
6208 
            'width' => 1,
6209 
          },
6210 
          'constant5_op_net_x2' => {
6211 
            'attributes' => {
6212 
              'hdlNetAttributes' => [
6213 
              ],
6214 
            },
6215 
            'hdlType' => 'std_logic',
6216 
            'width' => 1,
6217 
          },
6218 
          'constant5_op_net_x3' => {
6219 
            'attributes' => {
6220 
              'hdlNetAttributes' => [
6221 
              ],
6222 
            },
6223 
            'hdlType' => 'std_logic',
6224 
            'width' => 1,
6225 
          },
6226 
          'constant5_op_net_x4' => {
6227 
            'attributes' => {
6228 
              'hdlNetAttributes' => [
6229 
              ],
6230 
            },
6231 
            'hdlType' => 'std_logic',
6232 
            'width' => 1,
6233 
          },
6234 
          'constant5_op_net_x5' => {
6235 
            'attributes' => {
6236 
              'hdlNetAttributes' => [
6237 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
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10517 
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10525 
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10530 
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10531 
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10532 
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10550 
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10560 
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10564 
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10565 
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10573 
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10575 
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10580 
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10586 
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10589 
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10590 
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10595 
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10599 
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10601 
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10607 
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10610 
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10611 
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10612 
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10613 
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10614 
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10615 
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10618 
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10621 
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10627 
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10628 
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10629 
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10632 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
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10640 
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10655 
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10660 
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10675 
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10680 
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10705 
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10750 
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10775 
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10790 
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10805 
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10811 
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10819 
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10820 
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10832 
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10836 
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10837 
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10839 
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10844 
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10845 
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10846 
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10849 
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10850 
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10873 
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10875 
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10885 
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10886 
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10887 
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10890 
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10895 
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10899 
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10900 
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10901 
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10902 
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10928 
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10967 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
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11350 
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11364 
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11419 
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11432 
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11460 
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11467 
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11475 
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11477 
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11488 
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11490 
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11495 
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11499 
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11501 
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11502 
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11509 
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11510 
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11511 
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11513 
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11514 
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11515 
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11516 
              'is_floating_block' => 1,
11517 
              'must_be_hdl_vector' => 1,
11518 
              'period' => 1,
11519 
              'port_id' => 0,
11520 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11521 
              'type' => 'UFix_32_0',
11522 
            },
11523 
            'direction' => 'out',
11524 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11525 
            'width' => 32,
11526 
          },
11527 
          'to_register5_dout' => {
11528 
            'attributes' => {
11529 
              'bin_pt' => 0,
11530 
              'is_floating_block' => 1,
11531 
              'must_be_hdl_vector' => 1,
11532 
              'period' => 1,
11533 
              'port_id' => 0,
11534 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11535 
              'type' => 'UFix_32_0',
11536 
            },
11537 
            'direction' => 'in',
11538 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11539 
            'width' => 32,
11540 
          },
11541 
          'to_register5_en' => {
11542 
            'attributes' => {
11543 
              'bin_pt' => 0,
11544 
              'is_floating_block' => 1,
11545 
              'must_be_hdl_vector' => 1,
11546 
              'period' => 1,
11547 
              'port_id' => 1,
11548 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11549 
              'type' => 'Bool',
11550 
            },
11551 
            'direction' => 'out',
11552 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11553 
            'width' => 1,
11554 
          },
11555 
          'to_register6_ce' => {
11556 
            'attributes' => {
11557 
              'domain' => '',
11558 
              'group' => 1,
11559 
              'isCe' => 1,
11560 
              'is_floating_block' => 1,
11561 
              'period' => 1,
11562 
              'type' => 'logic',
11563 
            },
11564 
            'direction' => 'out',
11565 
            'hdlType' => 'std_logic',
11566 
            'width' => 1,
11567 
          },
11568 
          'to_register6_clk' => {
11569 
            'attributes' => {
11570 
              'domain' => '',
11571 
              'group' => 1,
11572 
              'isClk' => 1,
11573 
              'is_floating_block' => 1,
11574 
              'period' => 1,
11575 
              'type' => 'logic',
11576 
            },
11577 
            'direction' => 'out',
11578 
            'hdlType' => 'std_logic',
11579 
            'width' => 1,
11580 
          },
11581 
          'to_register6_clr' => {
11582 
            'attributes' => {
11583 
              'domain' => '',
11584 
              'group' => 1,
11585 
              'isClr' => 1,
11586 
              'is_floating_block' => 1,
11587 
              'period' => 1,
11588 
              'type' => 'logic',
11589 
              'valid_bit_used' => 0,
11590 
            },
11591 
            'direction' => 'out',
11592 
            'hdlType' => 'std_logic',
11593 
            'width' => 1,
11594 
          },
11595 
          'to_register6_data_in' => {
11596 
            'attributes' => {
11597 
              'bin_pt' => 0,
11598 
              'is_floating_block' => 1,
11599 
              'must_be_hdl_vector' => 1,
11600 
              'period' => 1,
11601 
              'port_id' => 0,
11602 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11603 
              'type' => 'UFix_32_0',
11604 
            },
11605 
            'direction' => 'out',
11606 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11607 
            'width' => 32,
11608 
          },
11609 
          'to_register6_dout' => {
11610 
            'attributes' => {
11611 
              'bin_pt' => 0,
11612 
              'is_floating_block' => 1,
11613 
              'must_be_hdl_vector' => 1,
11614 
              'period' => 1,
11615 
              'port_id' => 0,
11616 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11617 
              'type' => 'UFix_32_0',
11618 
            },
11619 
            'direction' => 'in',
11620 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11621 
            'width' => 32,
11622 
          },
11623 
          'to_register6_en' => {
11624 
            'attributes' => {
11625 
              'bin_pt' => 0,
11626 
              'is_floating_block' => 1,
11627 
              'must_be_hdl_vector' => 1,
11628 
              'period' => 1,
11629 
              'port_id' => 1,
11630 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11631 
              'type' => 'Bool',
11632 
            },
11633 
            'direction' => 'out',
11634 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11635 
            'width' => 1,
11636 
          },
11637 
          'to_register7_ce' => {
11638 
            'attributes' => {
11639 
              'domain' => '',
11640 
              'group' => 1,
11641 
              'isCe' => 1,
11642 
              'is_floating_block' => 1,
11643 
              'period' => 1,
11644 
              'type' => 'logic',
11645 
            },
11646 
            'direction' => 'out',
11647 
            'hdlType' => 'std_logic',
11648 
            'width' => 1,
11649 
          },
11650 
          'to_register7_clk' => {
11651 
            'attributes' => {
11652 
              'domain' => '',
11653 
              'group' => 1,
11654 
              'isClk' => 1,
11655 
              'is_floating_block' => 1,
11656 
              'period' => 1,
11657 
              'type' => 'logic',
11658 
            },
11659 
            'direction' => 'out',
11660 
            'hdlType' => 'std_logic',
11661 
            'width' => 1,
11662 
          },
11663 
          'to_register7_clr' => {
11664 
            'attributes' => {
11665 
              'domain' => '',
11666 
              'group' => 1,
11667 
              'isClr' => 1,
11668 
              'is_floating_block' => 1,
11669 
              'period' => 1,
11670 
              'type' => 'logic',
11671 
              'valid_bit_used' => 0,
11672 
            },
11673 
            'direction' => 'out',
11674 
            'hdlType' => 'std_logic',
11675 
            'width' => 1,
11676 
          },
11677 
          'to_register7_data_in' => {
11678 
            'attributes' => {
11679 
              'bin_pt' => 0,
11680 
              'is_floating_block' => 1,
11681 
              'must_be_hdl_vector' => 1,
11682 
              'period' => 1,
11683 
              'port_id' => 0,
11684 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11685 
              'type' => 'UFix_32_0',
11686 
            },
11687 
            'direction' => 'out',
11688 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11689 
            'width' => 32,
11690 
          },
11691 
          'to_register7_dout' => {
11692 
            'attributes' => {
11693 
              'bin_pt' => 0,
11694 
              'is_floating_block' => 1,
11695 
              'must_be_hdl_vector' => 1,
11696 
              'period' => 1,
11697 
              'port_id' => 0,
11698 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11699 
              'type' => 'UFix_32_0',
11700 
            },
11701 
            'direction' => 'in',
11702 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11703 
            'width' => 32,
11704 
          },
11705 
          'to_register7_en' => {
11706 
            'attributes' => {
11707 
              'bin_pt' => 0,
11708 
              'is_floating_block' => 1,
11709 
              'must_be_hdl_vector' => 1,
11710 
              'period' => 1,
11711 
              'port_id' => 1,
11712 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11713 
              'type' => 'Bool',
11714 
            },
11715 
            'direction' => 'out',
11716 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11717 
            'width' => 1,
11718 
          },
11719 
          'to_register8_ce' => {
11720 
            'attributes' => {
11721 
              'domain' => '',
11722 
              'group' => 1,
11723 
              'isCe' => 1,
11724 
              'is_floating_block' => 1,
11725 
              'period' => 1,
11726 
              'type' => 'logic',
11727 
            },
11728 
            'direction' => 'out',
11729 
            'hdlType' => 'std_logic',
11730 
            'width' => 1,
11731 
          },
11732 
          'to_register8_clk' => {
11733 
            'attributes' => {
11734 
              'domain' => '',
11735 
              'group' => 1,
11736 
              'isClk' => 1,
11737 
              'is_floating_block' => 1,
11738 
              'period' => 1,
11739 
              'type' => 'logic',
11740 
            },
11741 
            'direction' => 'out',
11742 
            'hdlType' => 'std_logic',
11743 
            'width' => 1,
11744 
          },
11745 
          'to_register8_clr' => {
11746 
            'attributes' => {
11747 
              'domain' => '',
11748 
              'group' => 1,
11749 
              'isClr' => 1,
11750 
              'is_floating_block' => 1,
11751 
              'period' => 1,
11752 
              'type' => 'logic',
11753 
              'valid_bit_used' => 0,
11754 
            },
11755 
            'direction' => 'out',
11756 
            'hdlType' => 'std_logic',
11757 
            'width' => 1,
11758 
          },
11759 
          'to_register8_data_in' => {
11760 
            'attributes' => {
11761 
              'bin_pt' => 0,
11762 
              'is_floating_block' => 1,
11763 
              'must_be_hdl_vector' => 1,
11764 
              'period' => 1,
11765 
              'port_id' => 0,
11766 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11767 
              'type' => 'Bool',
11768 
            },
11769 
            'direction' => 'out',
11770 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11771 
            'width' => 1,
11772 
          },
11773 
          'to_register8_dout' => {
11774 
            'attributes' => {
11775 
              'bin_pt' => 0,
11776 
              'is_floating_block' => 1,
11777 
              'must_be_hdl_vector' => 1,
11778 
              'period' => 1,
11779 
              'port_id' => 0,
11780 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11781 
              'type' => 'Bool',
11782 
            },
11783 
            'direction' => 'in',
11784 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11785 
            'width' => 1,
11786 
          },
11787 
          'to_register8_en' => {
11788 
            'attributes' => {
11789 
              'bin_pt' => 0,
11790 
              'is_floating_block' => 1,
11791 
              'must_be_hdl_vector' => 1,
11792 
              'period' => 1,
11793 
              'port_id' => 1,
11794 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11795 
              'type' => 'Bool',
11796 
            },
11797 
            'direction' => 'out',
11798 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11799 
            'width' => 1,
11800 
          },
11801 
          'to_register9_ce' => {
11802 
            'attributes' => {
11803 
              'domain' => '',
11804 
              'group' => 1,
11805 
              'isCe' => 1,
11806 
              'is_floating_block' => 1,
11807 
              'period' => 1,
11808 
              'type' => 'logic',
11809 
            },
11810 
            'direction' => 'out',
11811 
            'hdlType' => 'std_logic',
11812 
            'width' => 1,
11813 
          },
11814 
          'to_register9_clk' => {
11815 
            'attributes' => {
11816 
              'domain' => '',
11817 
              'group' => 1,
11818 
              'isClk' => 1,
11819 
              'is_floating_block' => 1,
11820 
              'period' => 1,
11821 
              'type' => 'logic',
11822 
            },
11823 
            'direction' => 'out',
11824 
            'hdlType' => 'std_logic',
11825 
            'width' => 1,
11826 
          },
11827 
          'to_register9_clr' => {
11828 
            'attributes' => {
11829 
              'domain' => '',
11830 
              'group' => 1,
11831 
              'isClr' => 1,
11832 
              'is_floating_block' => 1,
11833 
              'period' => 1,
11834 
              'type' => 'logic',
11835 
              'valid_bit_used' => 0,
11836 
            },
11837 
            'direction' => 'out',
11838 
            'hdlType' => 'std_logic',
11839 
            'width' => 1,
11840 
          },
11841 
          'to_register9_data_in' => {
11842 
            'attributes' => {
11843 
              'bin_pt' => 0,
11844 
              'is_floating_block' => 1,
11845 
              'must_be_hdl_vector' => 1,
11846 
              'period' => 1,
11847 
              'port_id' => 0,
11848 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11849 
              'type' => 'UFix_32_0',
11850 
            },
11851 
            'direction' => 'out',
11852 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11853 
            'width' => 32,
11854 
          },
11855 
          'to_register9_dout' => {
11856 
            'attributes' => {
11857 
              'bin_pt' => 0,
11858 
              'is_floating_block' => 1,
11859 
              'must_be_hdl_vector' => 1,
11860 
              'period' => 1,
11861 
              'port_id' => 0,
11862 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11863 
              'type' => 'UFix_32_0',
11864 
            },
11865 
            'direction' => 'in',
11866 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11867 
            'width' => 32,
11868 
          },
11869 
          'to_register9_en' => {
11870 
            'attributes' => {
11871 
              'bin_pt' => 0,
11872 
              'is_floating_block' => 1,
11873 
              'must_be_hdl_vector' => 1,
11874 
              'period' => 1,
11875 
              'port_id' => 1,
11876 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11877 
              'type' => 'Bool',
11878 
            },
11879 
            'direction' => 'out',
11880 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11881 
            'width' => 1,
11882 
          },
11883 
        },
11884 
        'subblocks' => {
11885 
          'default_clock_driver_x0' => {
11886 
            'connections' => {
11887 
              'ce_1' => 'ce_1_sg',
11888 
              'clk_1' => 'clk_1_sg',
11889 
              'sysce' => [
11890 
                'constant',
11891 
                '\'1\'',
11892 
              ],
11893 
              'sysce_clr' => [
11894 
                'constant',
11895 
                '\'0\'',
11896 
              ],
11897 
              'sysclk' => 'clkNet',
11898 
            },
11899 
            'entity' => {
11900 
              'attributes' => {
11901 
                'domain' => 'default',
11902 
                'hdlArchAttributes' => [
11903 
                  [
11904 
                    'syn_noprune',
11905 
                    'boolean',
11906 
                    'true',
11907 
                  ],
11908 
                  [
11909 
                    'optimize_primitives',
11910 
                    'boolean',
11911 
                    'false',
11912 
                  ],
11913 
                  [
11914 
                    'dont_touch',
11915 
                    'boolean',
11916 
                    'true',
11917 
                  ],
11918 
                ],
11919 
                'hdlEntityAttributes' => [
11920 
                ],
11921 
                'isClkDriver' => 1,
11922 
              },
11923 
              'entityName' => 'default_clock_driver',
11924 
              'ports' => {
11925 
                'ce_1' => {
11926 
                  'attributes' => {
11927 
                    'domain' => 'default',
11928 
                    'group' => 1,
11929 
                    'isCe' => 1,
11930 
                    'period' => 1,
11931 
                    'type' => 'logic',
11932 
                  },
11933 
                  'direction' => 'out',
11934 
                  'hdlType' => 'std_logic',
11935 
                  'width' => 1,
11936 
                },
11937 
                'clk_1' => {
11938 
                  'attributes' => {
11939 
                    'domain' => 'default',
11940 
                    'group' => 1,
11941 
                    'isClk' => 1,
11942 
                    'period' => 1,
11943 
                    'type' => 'logic',
11944 
                  },
11945 
                  'direction' => 'out',
11946 
                  'hdlType' => 'std_logic',
11947 
                  'width' => 1,
11948 
                },
11949 
                'sysce' => {
11950 
                  'attributes' => {
11951 
                    'group' => 4,
11952 
                    'isCe' => 1,
11953 
                    'period' => 1,
11954 
                  },
11955 
                  'direction' => 'in',
11956 
                  'hdlType' => 'std_logic',
11957 
                  'width' => 1,
11958 
                },
11959 
                'sysce_clr' => {
11960 
                  'attributes' => {
11961 
                    'group' => 4,
11962 
                    'isClr' => 1,
11963 
                    'period' => 1,
11964 
                  },
11965 
                  'direction' => 'in',
11966 
                  'hdlType' => 'std_logic',
11967 
                  'width' => 1,
11968 
                },
11969 
                'sysclk' => {
11970 
                  'attributes' => {
11971 
                    'group' => 4,
11972 
                    'isClk' => 1,
11973 
                    'period' => 1,
11974 
                  },
11975 
                  'direction' => 'in',
11976 
                  'hdlType' => 'std_logic',
11977 
                  'width' => 1,
11978 
                },
11979 
              },
11980 
            },
11981 
            'entityName' => 'default_clock_driver',
11982 
          },
11983 
          'inout_logic_x0' => {
11984 
            'connections' => {
11985 
              'data_in' => 'debug_in_2i_net_x0',
11986 
              'data_in_x0' => 'reg04_tv_net_x0',
11987 
              'data_in_x1' => 'reg04_td_net_x0',
11988 
              'data_in_x10' => 'debug_in_3i_net_x0',
11989 
              'data_in_x11' => 'debug_in_4i_net_x0',
11990 
              'data_in_x12' => 'reg09_tv_net_x0',
11991 
              'data_in_x13' => 'reg09_td_net_x0',
11992 
              'data_in_x14' => 'reg10_tv_net_x0',
11993 
              'data_in_x15' => 'reg10_td_net_x0',
11994 
              'data_in_x16' => 'reg08_tv_net_x0',
11995 
              'data_in_x17' => 'reg08_td_net_x0',
11996 
              'data_in_x18' => 'reg11_tv_net_x0',
11997 
              'data_in_x19' => 'reg11_td_net_x0',
11998 
              'data_in_x2' => 'reg05_tv_net_x0',
11999 
              'data_in_x20' => 'reg12_tv_net_x0',
12000 
              'data_in_x21' => 'reg01_tv_net_x0',
12001 
              'data_in_x22' => 'reg12_td_net_x0',
12002 
              'data_in_x23' => 'reg13_tv_net_x0',
12003 
              'data_in_x24' => 'reg13_td_net_x0',
12004 
              'data_in_x25' => 'reg14_tv_net_x0',
12005 
              'data_in_x26' => 'reg14_td_net_x0',
12006 
              'data_in_x27' => 'reg02_tv_net_x0',
12007 
              'data_in_x28' => 'reg02_td_net_x0',
12008 
              'data_in_x29' => 'debug_in_1i_net_x0',
12009 
              'data_in_x3' => 'reg05_td_net_x0',
12010 
              'data_in_x30' => 'reg01_td_net_x0',
12011 
              'data_in_x31' => 'reg03_tv_net_x0',
12012 
              'data_in_x32' => 'reg03_td_net_x0',
12013 
              'data_in_x4' => 'reg06_tv_net_x0',
12014 
              'data_in_x5' => 'reg06_td_net_x0',
12015 
              'data_in_x6' => 'reg07_tv_net_x0',
12016 
              'data_in_x7' => 'reg07_td_net_x0',
12017 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
12018 
              'data_in_x9' => 'dma_host2board_done_net_x0',
12019 
              'data_out' => 'from_register1_data_out_net',
12020 
              'data_out_x0' => 'from_register10_data_out_net',
12021 
              'data_out_x1' => 'from_register11_data_out_net',
12022 
              'data_out_x10' => 'from_register2_data_out_net',
12023 
              'data_out_x11' => 'from_register20_data_out_net',
12024 
              'data_out_x12' => 'from_register21_data_out_net',
12025 
              'data_out_x13' => 'from_register22_data_out_net',
12026 
              'data_out_x14' => 'from_register23_data_out_net',
12027 
              'data_out_x15' => 'from_register24_data_out_net',
12028 
              'data_out_x16' => 'from_register25_data_out_net',
12029 
              'data_out_x17' => 'from_register26_data_out_net',
12030 
              'data_out_x18' => 'from_register27_data_out_net',
12031 
              'data_out_x19' => 'from_register28_data_out_net',
12032 
              'data_out_x2' => 'from_register12_data_out_net',
12033 
              'data_out_x20' => 'from_register3_data_out_net',
12034 
              'data_out_x21' => 'from_register4_data_out_net',
12035 
              'data_out_x22' => 'from_register5_data_out_net',
12036 
              'data_out_x23' => 'from_register6_data_out_net',
12037 
              'data_out_x24' => 'from_register7_data_out_net',
12038 
              'data_out_x25' => 'from_register8_data_out_net',
12039 
              'data_out_x26' => 'from_register9_data_out_net',
12040 
              'data_out_x3' => 'from_register13_data_out_net',
12041 
              'data_out_x4' => 'from_register14_data_out_net',
12042 
              'data_out_x5' => 'from_register15_data_out_net',
12043 
              'data_out_x6' => 'from_register16_data_out_net',
12044 
              'data_out_x7' => 'from_register17_data_out_net',
12045 
              'data_out_x8' => 'from_register18_data_out_net',
12046 
              'data_out_x9' => 'from_register19_data_out_net',
12047 
              'debug_in_1i' => 'debug_in_1i_net',
12048 
              'debug_in_2i' => 'debug_in_2i_net',
12049 
              'debug_in_3i' => 'debug_in_3i_net',
12050 
              'debug_in_4i' => 'debug_in_4i_net',
12051 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
12052 
              'dma_host2board_done' => 'dma_host2board_done_net',
12053 
              'en' => 'constant5_op_net_x0',
12054 
              'en_x0' => 'constant5_op_net_x1',
12055 
              'en_x1' => 'constant5_op_net_x2',
12056 
              'en_x10' => 'constant5_op_net_x11',
12057 
              'en_x11' => 'constant5_op_net_x12',
12058 
              'en_x12' => 'constant1_op_net_x0',
12059 
              'en_x13' => 'constant1_op_net_x1',
12060 
              'en_x14' => 'constant1_op_net_x2',
12061 
              'en_x15' => 'constant1_op_net_x3',
12062 
              'en_x16' => 'constant1_op_net_x4',
12063 
              'en_x17' => 'constant1_op_net_x5',
12064 
              'en_x18' => 'constant1_op_net_x6',
12065 
              'en_x19' => 'constant1_op_net_x7',
12066 
              'en_x2' => 'constant5_op_net_x3',
12067 
              'en_x20' => 'constant1_op_net_x8',
12068 
              'en_x21' => 'constant5_op_net_x13',
12069 
              'en_x22' => 'constant1_op_net_x9',
12070 
              'en_x23' => 'constant1_op_net_x10',
12071 
              'en_x24' => 'constant1_op_net_x11',
12072 
              'en_x25' => 'constant1_op_net_x12',
12073 
              'en_x26' => 'constant1_op_net_x13',
12074 
              'en_x27' => 'constant5_op_net_x14',
12075 
              'en_x28' => 'constant5_op_net_x15',
12076 
              'en_x29' => 'constant5_op_net_x16',
12077 
              'en_x3' => 'constant5_op_net_x4',
12078 
              'en_x30' => 'constant5_op_net_x17',
12079 
              'en_x31' => 'constant5_op_net_x18',
12080 
              'en_x32' => 'constant5_op_net_x19',
12081 
              'en_x4' => 'constant5_op_net_x5',
12082 
              'en_x5' => 'constant5_op_net_x6',
12083 
              'en_x6' => 'constant5_op_net_x7',
12084 
              'en_x7' => 'constant5_op_net_x8',
12085 
              'en_x8' => 'constant5_op_net_x9',
12086 
              'en_x9' => 'constant5_op_net_x10',
12087 
              'reg01_rd' => 'from_register3_data_out_net_x0',
12088 
              'reg01_rv' => 'from_register1_data_out_net_x0',
12089 
              'reg01_td' => 'reg01_td_net',
12090 
              'reg01_tv' => 'reg01_tv_net',
12091 
              'reg02_rd' => 'from_register5_data_out_net_x0',
12092 
              'reg02_rv' => 'from_register2_data_out_net_x0',
12093 
              'reg02_td' => 'reg02_td_net',
12094 
              'reg02_tv' => 'reg02_tv_net',
12095 
              'reg03_rd' => 'from_register7_data_out_net_x0',
12096 
              'reg03_rv' => 'from_register6_data_out_net_x0',
12097 
              'reg03_td' => 'reg03_td_net',
12098 
              'reg03_tv' => 'reg03_tv_net',
12099 
              'reg04_rd' => 'from_register8_data_out_net_x0',
12100 
              'reg04_rv' => 'from_register4_data_out_net_x0',
12101 
              'reg04_td' => 'reg04_td_net',
12102 
              'reg04_tv' => 'reg04_tv_net',
12103 
              'reg05_rd' => 'from_register10_data_out_net_x0',
12104 
              'reg05_rv' => 'from_register9_data_out_net_x0',
12105 
              'reg05_td' => 'reg05_td_net',
12106 
              'reg05_tv' => 'reg05_tv_net',
12107 
              'reg06_rd' => 'from_register11_data_out_net_x0',
12108 
              'reg06_rv' => 'from_register12_data_out_net_x0',
12109 
              'reg06_td' => 'reg06_td_net',
12110 
              'reg06_tv' => 'reg06_tv_net',
12111 
              'reg07_rd' => 'from_register13_data_out_net_x0',
12112 
              'reg07_rv' => 'from_register14_data_out_net_x0',
12113 
              'reg07_td' => 'reg07_td_net',
12114 
              'reg07_tv' => 'reg07_tv_net',
12115 
              'reg08_rd' => 'from_register15_data_out_net_x0',
12116 
              'reg08_rv' => 'from_register16_data_out_net_x0',
12117 
              'reg08_td' => 'reg08_td_net',
12118 
              'reg08_tv' => 'reg08_tv_net',
12119 
              'reg09_rd' => 'from_register17_data_out_net_x0',
12120 
              'reg09_rv' => 'from_register18_data_out_net_x0',
12121 
              'reg09_td' => 'reg09_td_net',
12122 
              'reg09_tv' => 'reg09_tv_net',
12123 
              'reg10_rd' => 'from_register19_data_out_net_x0',
12124 
              'reg10_rv' => 'from_register20_data_out_net_x0',
12125 
              'reg10_td' => 'reg10_td_net',
12126 
              'reg10_tv' => 'reg10_tv_net',
12127 
              'reg11_rd' => 'from_register21_data_out_net_x0',
12128 
              'reg11_rv' => 'from_register22_data_out_net_x0',
12129 
              'reg11_td' => 'reg11_td_net',
12130 
              'reg11_tv' => 'reg11_tv_net',
12131 
              'reg12_rd' => 'from_register23_data_out_net_x0',
12132 
              'reg12_rv' => 'from_register24_data_out_net_x0',
12133 
              'reg12_td' => 'reg12_td_net',
12134 
              'reg12_tv' => 'reg12_tv_net',
12135 
              'reg13_rd' => 'from_register25_data_out_net_x0',
12136 
              'reg13_rv' => 'from_register26_data_out_net_x0',
12137 
              'reg13_td' => 'reg13_td_net',
12138 
              'reg13_tv' => 'reg13_tv_net',
12139 
              'reg14_rd' => 'from_register27_data_out_net_x0',
12140 
              'reg14_rv' => 'from_register28_data_out_net_x0',
12141 
              'reg14_td' => 'reg14_td_net',
12142 
              'reg14_tv' => 'reg14_tv_net',
12143 
            },
12144 
            'entity' => {
12145 
              'attributes' => {
12146 
                'entityAlreadyNetlisted' => 1,
12147 
                'hdlKind' => 'vhdl',
12148 
                'isDesign' => 1,
12149 
                'simulinkName' => 'INOUT_LOGIC',
12150 
              },
12151 
              'entityName' => 'inout_logic',
12152 
              'ports' => {
12153 
                'data_in' => {
12154 
                  'attributes' => {
12155 
                    'bin_pt' => 0,
12156 
                    'is_floating_block' => 1,
12157 
                    'must_be_hdl_vector' => 1,
12158 
                    'period' => 1,
12159 
                    'port_id' => 0,
12160 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12161 
                    'type' => 'UFix_32_0',
12162 
                  },
12163 
                  'direction' => 'out',
12164 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12165 
                  'width' => 32,
12166 
                },
12167 
                'data_in_x0' => {
12168 
                  'attributes' => {
12169 
                    'bin_pt' => 0,
12170 
                    'is_floating_block' => 1,
12171 
                    'must_be_hdl_vector' => 1,
12172 
                    'period' => 1,
12173 
                    'port_id' => 0,
12174 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12175 
                    'type' => 'Bool',
12176 
                  },
12177 
                  'direction' => 'out',
12178 
                  'hdlType' => 'std_logic',
12179 
                  'width' => 1,
12180 
                },
12181 
                'data_in_x1' => {
12182 
                  'attributes' => {
12183 
                    'bin_pt' => 0,
12184 
                    'is_floating_block' => 1,
12185 
                    'must_be_hdl_vector' => 1,
12186 
                    'period' => 1,
12187 
                    'port_id' => 0,
12188 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12189 
                    'type' => 'UFix_32_0',
12190 
                  },
12191 
                  'direction' => 'out',
12192 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12193 
                  'width' => 32,
12194 
                },
12195 
                'data_in_x10' => {
12196 
                  'attributes' => {
12197 
                    'bin_pt' => 0,
12198 
                    'is_floating_block' => 1,
12199 
                    'must_be_hdl_vector' => 1,
12200 
                    'period' => 1,
12201 
                    'port_id' => 0,
12202 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12203 
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12204 
                  },
12205 
                  'direction' => 'out',
12206 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12207 
                  'width' => 32,
12208 
                },
12209 
                'data_in_x11' => {
12210 
                  'attributes' => {
12211 
                    'bin_pt' => 0,
12212 
                    'is_floating_block' => 1,
12213 
                    'must_be_hdl_vector' => 1,
12214 
                    'period' => 1,
12215 
                    'port_id' => 0,
12216 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12217 
                    'type' => 'UFix_32_0',
12218 
                  },
12219 
                  'direction' => 'out',
12220 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12221 
                  'width' => 32,
12222 
                },
12223 
                'data_in_x12' => {
12224 
                  'attributes' => {
12225 
                    'bin_pt' => 0,
12226 
                    'is_floating_block' => 1,
12227 
                    'must_be_hdl_vector' => 1,
12228 
                    'period' => 1,
12229 
                    'port_id' => 0,
12230 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12231 
                    'type' => 'Bool',
12232 
                  },
12233 
                  'direction' => 'out',
12234 
                  'hdlType' => 'std_logic',
12235 
                  'width' => 1,
12236 
                },
12237 
                'data_in_x13' => {
12238 
                  'attributes' => {
12239 
                    'bin_pt' => 0,
12240 
                    'is_floating_block' => 1,
12241 
                    'must_be_hdl_vector' => 1,
12242 
                    'period' => 1,
12243 
                    'port_id' => 0,
12244 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12245 
                    'type' => 'UFix_32_0',
12246 
                  },
12247 
                  'direction' => 'out',
12248 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12249 
                  'width' => 32,
12250 
                },
12251 
                'data_in_x14' => {
12252 
                  'attributes' => {
12253 
                    'bin_pt' => 0,
12254 
                    'is_floating_block' => 1,
12255 
                    'must_be_hdl_vector' => 1,
12256 
                    'period' => 1,
12257 
                    'port_id' => 0,
12258 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12259 
                    'type' => 'Bool',
12260 
                  },
12261 
                  'direction' => 'out',
12262 
                  'hdlType' => 'std_logic',
12263 
                  'width' => 1,
12264 
                },
12265 
                'data_in_x15' => {
12266 
                  'attributes' => {
12267 
                    'bin_pt' => 0,
12268 
                    'is_floating_block' => 1,
12269 
                    'must_be_hdl_vector' => 1,
12270 
                    'period' => 1,
12271 
                    'port_id' => 0,
12272 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12273 
                    'type' => 'UFix_32_0',
12274 
                  },
12275 
                  'direction' => 'out',
12276 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12277 
                  'width' => 32,
12278 
                },
12279 
                'data_in_x16' => {
12280 
                  'attributes' => {
12281 
                    'bin_pt' => 0,
12282 
                    'is_floating_block' => 1,
12283 
                    'must_be_hdl_vector' => 1,
12284 
                    'period' => 1,
12285 
                    'port_id' => 0,
12286 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12287 
                    'type' => 'Bool',
12288 
                  },
12289 
                  'direction' => 'out',
12290 
                  'hdlType' => 'std_logic',
12291 
                  'width' => 1,
12292 
                },
12293 
                'data_in_x17' => {
12294 
                  'attributes' => {
12295 
                    'bin_pt' => 0,
12296 
                    'is_floating_block' => 1,
12297 
                    'must_be_hdl_vector' => 1,
12298 
                    'period' => 1,
12299 
                    'port_id' => 0,
12300 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12301 
                    'type' => 'UFix_32_0',
12302 
                  },
12303 
                  'direction' => 'out',
12304 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12305 
                  'width' => 32,
12306 
                },
12307 
                'data_in_x18' => {
12308 
                  'attributes' => {
12309 
                    'bin_pt' => 0,
12310 
                    'is_floating_block' => 1,
12311 
                    'must_be_hdl_vector' => 1,
12312 
                    'period' => 1,
12313 
                    'port_id' => 0,
12314 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12315 
                    'type' => 'Bool',
12316 
                  },
12317 
                  'direction' => 'out',
12318 
                  'hdlType' => 'std_logic',
12319 
                  'width' => 1,
12320 
                },
12321 
                'data_in_x19' => {
12322 
                  'attributes' => {
12323 
                    'bin_pt' => 0,
12324 
                    'is_floating_block' => 1,
12325 
                    'must_be_hdl_vector' => 1,
12326 
                    'period' => 1,
12327 
                    'port_id' => 0,
12328 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12329 
                    'type' => 'UFix_32_0',
12330 
                  },
12331 
                  'direction' => 'out',
12332 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12333 
                  'width' => 32,
12334 
                },
12335 
                'data_in_x2' => {
12336 
                  'attributes' => {
12337 
                    'bin_pt' => 0,
12338 
                    'is_floating_block' => 1,
12339 
                    'must_be_hdl_vector' => 1,
12340 
                    'period' => 1,
12341 
                    'port_id' => 0,
12342 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12343 
                    'type' => 'Bool',
12344 
                  },
12345 
                  'direction' => 'out',
12346 
                  'hdlType' => 'std_logic',
12347 
                  'width' => 1,
12348 
                },
12349 
                'data_in_x20' => {
12350 
                  'attributes' => {
12351 
                    'bin_pt' => 0,
12352 
                    'is_floating_block' => 1,
12353 
                    'must_be_hdl_vector' => 1,
12354 
                    'period' => 1,
12355 
                    'port_id' => 0,
12356 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12357 
                    'type' => 'Bool',
12358 
                  },
12359 
                  'direction' => 'out',
12360 
                  'hdlType' => 'std_logic',
12361 
                  'width' => 1,
12362 
                },
12363 
                'data_in_x21' => {
12364 
                  'attributes' => {
12365 
                    'bin_pt' => 0,
12366 
                    'is_floating_block' => 1,
12367 
                    'must_be_hdl_vector' => 1,
12368 
                    'period' => 1,
12369 
                    'port_id' => 0,
12370 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12371 
                    'type' => 'Bool',
12372 
                  },
12373 
                  'direction' => 'out',
12374 
                  'hdlType' => 'std_logic',
12375 
                  'width' => 1,
12376 
                },
12377 
                'data_in_x22' => {
12378 
                  'attributes' => {
12379 
                    'bin_pt' => 0,
12380 
                    'is_floating_block' => 1,
12381 
                    'must_be_hdl_vector' => 1,
12382 
                    'period' => 1,
12383 
                    'port_id' => 0,
12384 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12385 
                    'type' => 'UFix_32_0',
12386 
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12387 
                  'direction' => 'out',
12388 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12389 
                  'width' => 32,
12390 
                },
12391 
                'data_in_x23' => {
12392 
                  'attributes' => {
12393 
                    'bin_pt' => 0,
12394 
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12395 
                    'must_be_hdl_vector' => 1,
12396 
                    'period' => 1,
12397 
                    'port_id' => 0,
12398 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12399 
                    'type' => 'Bool',
12400 
                  },
12401 
                  'direction' => 'out',
12402 
                  'hdlType' => 'std_logic',
12403 
                  'width' => 1,
12404 
                },
12405 
                'data_in_x24' => {
12406 
                  'attributes' => {
12407 
                    'bin_pt' => 0,
12408 
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12409 
                    'must_be_hdl_vector' => 1,
12410 
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12411 
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12412 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12413 
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12414 
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12415 
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12416 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12417 
                  'width' => 32,
12418 
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12419 
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12420 
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12421 
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12422 
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12423 
                    'must_be_hdl_vector' => 1,
12424 
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12425 
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12426 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12427 
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12428 
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12429 
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12430 
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12431 
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12432 
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12433 
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12434 
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12435 
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12436 
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12437 
                    'must_be_hdl_vector' => 1,
12438 
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12439 
                    'port_id' => 0,
12440 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12441 
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12442 
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12443 
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12444 
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12445 
                  'width' => 32,
12446 
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12447 
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12448 
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12449 
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12450 
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12451 
                    'must_be_hdl_vector' => 1,
12452 
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12453 
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12454 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12455 
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12456 
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12457 
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12458 
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12459 
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12460 
                },
12461 
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12462 
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12463 
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12464 
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12465 
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12466 
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12467 
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12468 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12469 
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12470 
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12471 
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12472 
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12473 
                  'width' => 32,
12474 
                },
12475 
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12476 
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12477 
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12478 
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12479 
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12480 
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12481 
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12482 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12483 
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12484 
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12485 
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