OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.ClockWrapper] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
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    'Impl_file' => 'ISE Defaults',
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    'Impl_file_sgadvanced' => '',
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    'Synth_file' => 'XST Defaults',
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    'Synth_file_sgadvanced' => '',
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    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5,
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    'base_system_period_simulink' => '8e-009',
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    'block_icon_display' => 'Default',
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    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0,
19 
    'clkWrapper' => 'inout_logic_cw',
20 
    'clkWrapperFile' => 'inout_logic_cw.vhd',
21 
    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
23 
    'clock_wrapper_sgadvanced' => '',
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    'compilation' => 'NGC Netlist',
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    'compilation_lut' => {
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      'keys' => [
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        'HDL Netlist',
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        'Bitstream',
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        'NGC Netlist',
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      ],
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      'values' => [
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        'target1',
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        'target2',
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        'target3',
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      ],
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    },
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    'compilation_target' => 'NGC Netlist',
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    'core_generation' => 1,
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    'core_generation_sgadvanced' => '',
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    'core_is_deployed' => 0,
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    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c46e83d2645affbd5',
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    'coregen_part_family' => 'virtex6',
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    'createTestbench' => 0,
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    'create_interface_document' => 'off',
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    'dbl_ovrd' => -1,
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    'dbl_ovrd_sgadvanced' => '',
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    'dcm_info' => {},
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    'dcm_input_clock_period' => 5,
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    'deprecated_control' => 'off',
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    'deprecated_control_sgadvanced' => '',
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    'design' => 'inout_logic',
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    'designFile' => 'inout_logic.vhd',
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    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
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    'device_speed' => -1,
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    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
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    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
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    'entityNamingInstrs' => {
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      'nameMap' => undef,
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      'namesAlreadyUsed' => {
61 
        'default_clock_driver' => 1,
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        'inout_logic_cw' => 1,
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      },
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    },
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    'eval_field' => 0,
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    'fileAttributes' => {
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      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
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    },
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    'files' => [
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      'xlpersistentdff.ngc',
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      'synopsis',
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      'inout_logic.vhd',
73 
      'xlpersistentdff.ngc',
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      'inout_logic_cw.vhd',
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    ],
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    'generating_subsystem_handle' => 2084.00048828125,
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    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
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    'has_advanced_control' => 0,
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    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
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    'hdlKind' => 'vhdl',
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    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
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    'impl_file' => 'ISE Defaults*',
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    'incr_netlist' => 'off',
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    'incr_netlist_sgadvanced' => '',
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    'infoedit' => ' System Generator',
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    'isCombinatorial' => 1,
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    'isdeployed' => 0,
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    'ise_version' => '13.3i',
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    'master_sysgen_token_handle' => 2085.00048828125,
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    'matlab' => 'C:/Programmi/MATLAB/R2010b',
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    'matlab_fixedpoint' => 1,
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    'mdlHandle' => 2083.00048828125,
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    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
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    'modelDiagnostics' => [
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      {
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        'count' => 351,
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        'isMask' => 0,
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        'type' => 'PCIe_UserLogic_00 Total blocks',
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        'type' => 'DiscretePulseGenerator',
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        'isMask' => 1,
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        'count' => 44,
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        'isMask' => 1,
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        'type' => 'Xilinx Gateway In Block',
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        'count' => 39,
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        'isMask' => 1,
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        'type' => 'Xilinx Gateway Out Block',
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        'count' => 2,
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        'isMask' => 1,
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        'type' => 'Xilinx Inverter Block',
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        'count' => 1,
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        'type' => 'Xilinx Logical Block Block',
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        'type' => 'Xilinx Register Block',
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        'count' => 62,
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        'isMask' => 1,
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        'type' => 'Xilinx Shared Memory Based From Register Block',
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        'count' => 62,
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        'isMask' => 1,
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        'type' => 'Xilinx Shared Memory Based To Register Block',
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      {
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        'count' => 1,
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        'isMask' => 1,
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        'type' => 'Xilinx Subsystem Generator Block',
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      },
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      {
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        'count' => 2,
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        'isMask' => 1,
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        'type' => 'Xilinx System Generator Block',
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      },
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      {
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        'count' => 14,
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        'isMask' => 1,
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        'type' => 'Xilinx Type Converter Block',
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      },
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    ],
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    'model_globals_initialized' => 1,
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    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
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    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
192 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
193 
    'ngc_config' => {
194 
      'include_cf' => 1,
195 
      'include_clockwrapper' => 1,
196 
    },
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    'ngc_files' => [ 'xlpersistentdff.ngc', ],
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    'num_sim_cycles' => 1250000000,
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    'package' => 'ff1156',
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    'part' => 'xc6vlx240t',
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    'partFamily' => 'virtex6',
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    'port_data_types_enabled' => 1,
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    'postgeneration_fcn' => 'xlNGCPostGeneration',
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    'preserve_hierarchy' => 0,
205 
    'proj_type' => 'Project Navigator',
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    'proj_type_sgadvanced' => '',
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    'run_coregen' => 'off',
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    'run_coregen_sgadvanced' => '',
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    'sample_time_colors_enabled' => 1,
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    'sampletimecolors' => 1,
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    'settings_fcn' => 'xlngcsettings',
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    'sg_blockgui_xml' => '',
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    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
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    'sg_list_contents' => '',
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    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
216 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
217 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
218 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
221 
fprintf(\'\',\'COMMENT: end icon graphics\');
222 
fprintf(\'\',\'COMMENT: begin icon text\');
223 
fprintf(\'\',\'COMMENT: end icon text\');',
224 
    'sg_version' => '',
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    'sggui_pos' => '-1,-1,-1,-1',
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    'simulation_island_subsystem_handle' => 2084.00048828125,
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    'simulinkName' => 'parking_lot',
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    'simulink_accelerator_running' => 0,
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    'simulink_debugger_running' => 0,
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    'simulink_period' => '8e-009',
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    'speed' => -1,
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    'synth_file' => 'XST Defaults*',
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    'synthesisTool' => 'XST',
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    'synthesis_language' => 'vhdl',
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    'synthesis_tool' => 'XST',
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    'synthesis_tool_sgadvanced' => '',
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    'sysclk_period' => 5,
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    'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
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    'sysgenRoot' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
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    'sysgenTokenSettings' => {
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      'Impl_file' => 'ISE Defaults',
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      'Impl_file_sgadvanced' => '',
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      'Synth_file' => 'XST Defaults',
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      'Synth_file_sgadvanced' => '',
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      'base_system_period_hardware' => 5,
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      'base_system_period_simulink' => '8e-009',
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      'block_icon_display' => 'Default',
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      'block_type' => 'sysgen',
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      'block_version' => '',
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      'ce_clr' => 0,
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      'clock_wrapper_sgadvanced' => '',
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257 
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          'target3',
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285 
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
306 
fprintf(\'\',\'COMMENT: end icon graphics\');
307 
fprintf(\'\',\'COMMENT: begin icon text\');
308 
fprintf(\'\',\'COMMENT: end icon text\');',
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      'sggui_pos' => '-1,-1,-1,-1',
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      'synthesis_tool' => 'XST',
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      'sysclk_period' => 5,
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      'testbench_sgadvanced' => '',
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      'trim_vbits' => 1,
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      'trim_vbits_sgadvanced' => '',
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      'xilinx_device' => 'xc6vlx240t-1ff1156',
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      'xilinxfamily' => 'virtex6',
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    },
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350 
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    'xilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
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  'nets' => {
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477 
    },
478 
    '.reg12_td' => {
479 
      'hdlType' => 'std_logic_vector(31 downto 0)',
480 
      'width' => 32,
481 
    },
482 
    '.reg12_tv' => {
483 
      'hdlType' => 'std_logic',
484 
      'width' => 1,
485 
    },
486 
    '.reg13_td' => {
487 
      'hdlType' => 'std_logic_vector(31 downto 0)',
488 
      'width' => 32,
489 
    },
490 
    '.reg13_tv' => {
491 
      'hdlType' => 'std_logic',
492 
      'width' => 1,
493 
    },
494 
    '.reg14_td' => {
495 
      'hdlType' => 'std_logic_vector(31 downto 0)',
496 
      'width' => 32,
497 
    },
498 
    '.reg14_tv' => {
499 
      'hdlType' => 'std_logic',
500 
      'width' => 1,
501 
    },
502 
    'from_register1.data_out' => {
503 
      'hdlType' => 'std_logic',
504 
      'width' => 1,
505 
    },
506 
    'from_register10.data_out' => {
507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
508 
      'width' => 32,
509 
    },
510 
    'from_register11.data_out' => {
511 
      'hdlType' => 'std_logic_vector(31 downto 0)',
512 
      'width' => 32,
513 
    },
514 
    'from_register12.data_out' => {
515 
      'hdlType' => 'std_logic',
516 
      'width' => 1,
517 
    },
518 
    'from_register13.data_out' => {
519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
520 
      'width' => 32,
521 
    },
522 
    'from_register14.data_out' => {
523 
      'hdlType' => 'std_logic',
524 
      'width' => 1,
525 
    },
526 
    'from_register15.data_out' => {
527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
528 
      'width' => 32,
529 
    },
530 
    'from_register16.data_out' => {
531 
      'hdlType' => 'std_logic',
532 
      'width' => 1,
533 
    },
534 
    'from_register17.data_out' => {
535 
      'hdlType' => 'std_logic_vector(31 downto 0)',
536 
      'width' => 32,
537 
    },
538 
    'from_register18.data_out' => {
539 
      'hdlType' => 'std_logic',
540 
      'width' => 1,
541 
    },
542 
    'from_register19.data_out' => {
543 
      'hdlType' => 'std_logic_vector(31 downto 0)',
544 
      'width' => 32,
545 
    },
546 
    'from_register2.data_out' => {
547 
      'hdlType' => 'std_logic',
548 
      'width' => 1,
549 
    },
550 
    'from_register20.data_out' => {
551 
      'hdlType' => 'std_logic',
552 
      'width' => 1,
553 
    },
554 
    'from_register21.data_out' => {
555 
      'hdlType' => 'std_logic_vector(31 downto 0)',
556 
      'width' => 32,
557 
    },
558 
    'from_register22.data_out' => {
559 
      'hdlType' => 'std_logic',
560 
      'width' => 1,
561 
    },
562 
    'from_register23.data_out' => {
563 
      'hdlType' => 'std_logic_vector(31 downto 0)',
564 
      'width' => 32,
565 
    },
566 
    'from_register24.data_out' => {
567 
      'hdlType' => 'std_logic',
568 
      'width' => 1,
569 
    },
570 
    'from_register25.data_out' => {
571 
      'hdlType' => 'std_logic_vector(31 downto 0)',
572 
      'width' => 32,
573 
    },
574 
    'from_register26.data_out' => {
575 
      'hdlType' => 'std_logic',
576 
      'width' => 1,
577 
    },
578 
    'from_register27.data_out' => {
579 
      'hdlType' => 'std_logic_vector(31 downto 0)',
580 
      'width' => 32,
581 
    },
582 
    'from_register28.data_out' => {
583 
      'hdlType' => 'std_logic',
584 
      'width' => 1,
585 
    },
586 
    'from_register3.data_out' => {
587 
      'hdlType' => 'std_logic_vector(31 downto 0)',
588 
      'width' => 32,
589 
    },
590 
    'from_register4.data_out' => {
591 
      'hdlType' => 'std_logic',
592 
      'width' => 1,
593 
    },
594 
    'from_register5.data_out' => {
595 
      'hdlType' => 'std_logic_vector(31 downto 0)',
596 
      'width' => 32,
597 
    },
598 
    'from_register6.data_out' => {
599 
      'hdlType' => 'std_logic',
600 
      'width' => 1,
601 
    },
602 
    'from_register7.data_out' => {
603 
      'hdlType' => 'std_logic_vector(31 downto 0)',
604 
      'width' => 32,
605 
    },
606 
    'from_register8.data_out' => {
607 
      'hdlType' => 'std_logic_vector(31 downto 0)',
608 
      'width' => 32,
609 
    },
610 
    'from_register9.data_out' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'sysgen_dut.reg01_rd' => {
615 
      'hdlType' => 'std_logic_vector(31 downto 0)',
616 
      'width' => 32,
617 
    },
618 
    'sysgen_dut.reg01_rv' => {
619 
      'hdlType' => 'std_logic',
620 
      'width' => 1,
621 
    },
622 
    'sysgen_dut.reg02_rd' => {
623 
      'hdlType' => 'std_logic_vector(31 downto 0)',
624 
      'width' => 32,
625 
    },
626 
    'sysgen_dut.reg02_rv' => {
627 
      'hdlType' => 'std_logic',
628 
      'width' => 1,
629 
    },
630 
    'sysgen_dut.reg03_rd' => {
631 
      'hdlType' => 'std_logic_vector(31 downto 0)',
632 
      'width' => 32,
633 
    },
634 
    'sysgen_dut.reg03_rv' => {
635 
      'hdlType' => 'std_logic',
636 
      'width' => 1,
637 
    },
638 
    'sysgen_dut.reg04_rd' => {
639 
      'hdlType' => 'std_logic_vector(31 downto 0)',
640 
      'width' => 32,
641 
    },
642 
    'sysgen_dut.reg04_rv' => {
643 
      'hdlType' => 'std_logic',
644 
      'width' => 1,
645 
    },
646 
    'sysgen_dut.reg05_rd' => {
647 
      'hdlType' => 'std_logic_vector(31 downto 0)',
648 
      'width' => 32,
649 
    },
650 
    'sysgen_dut.reg05_rv' => {
651 
      'hdlType' => 'std_logic',
652 
      'width' => 1,
653 
    },
654 
    'sysgen_dut.reg06_rd' => {
655 
      'hdlType' => 'std_logic_vector(31 downto 0)',
656 
      'width' => 32,
657 
    },
658 
    'sysgen_dut.reg06_rv' => {
659 
      'hdlType' => 'std_logic',
660 
      'width' => 1,
661 
    },
662 
    'sysgen_dut.reg07_rd' => {
663 
      'hdlType' => 'std_logic_vector(31 downto 0)',
664 
      'width' => 32,
665 
    },
666 
    'sysgen_dut.reg07_rv' => {
667 
      'hdlType' => 'std_logic',
668 
      'width' => 1,
669 
    },
670 
    'sysgen_dut.reg08_rd' => {
671 
      'hdlType' => 'std_logic_vector(31 downto 0)',
672 
      'width' => 32,
673 
    },
674 
    'sysgen_dut.reg08_rv' => {
675 
      'hdlType' => 'std_logic',
676 
      'width' => 1,
677 
    },
678 
    'sysgen_dut.reg09_rd' => {
679 
      'hdlType' => 'std_logic_vector(31 downto 0)',
680 
      'width' => 32,
681 
    },
682 
    'sysgen_dut.reg09_rv' => {
683 
      'hdlType' => 'std_logic',
684 
      'width' => 1,
685 
    },
686 
    'sysgen_dut.reg10_rd' => {
687 
      'hdlType' => 'std_logic_vector(31 downto 0)',
688 
      'width' => 32,
689 
    },
690 
    'sysgen_dut.reg10_rv' => {
691 
      'hdlType' => 'std_logic',
692 
      'width' => 1,
693 
    },
694 
    'sysgen_dut.reg11_rd' => {
695 
      'hdlType' => 'std_logic_vector(31 downto 0)',
696 
      'width' => 32,
697 
    },
698 
    'sysgen_dut.reg11_rv' => {
699 
      'hdlType' => 'std_logic',
700 
      'width' => 1,
701 
    },
702 
    'sysgen_dut.reg12_rd' => {
703 
      'hdlType' => 'std_logic_vector(31 downto 0)',
704 
      'width' => 32,
705 
    },
706 
    'sysgen_dut.reg12_rv' => {
707 
      'hdlType' => 'std_logic',
708 
      'width' => 1,
709 
    },
710 
    'sysgen_dut.reg13_rd' => {
711 
      'hdlType' => 'std_logic_vector(31 downto 0)',
712 
      'width' => 32,
713 
    },
714 
    'sysgen_dut.reg13_rv' => {
715 
      'hdlType' => 'std_logic',
716 
      'width' => 1,
717 
    },
718 
    'sysgen_dut.reg14_rd' => {
719 
      'hdlType' => 'std_logic_vector(31 downto 0)',
720 
      'width' => 32,
721 
    },
722 
    'sysgen_dut.reg14_rv' => {
723 
      'hdlType' => 'std_logic',
724 
      'width' => 1,
725 
    },
726 
    'sysgen_dut.to_register10_ce' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'sysgen_dut.to_register10_clk' => {
731 
      'hdlType' => 'std_logic',
732 
      'width' => 1,
733 
    },
734 
    'sysgen_dut.to_register10_clr' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'sysgen_dut.to_register10_data_in' => {
739 
      'hdlType' => 'std_logic',
740 
      'width' => 1,
741 
    },
742 
    'sysgen_dut.to_register10_en' => {
743 
      'hdlType' => 'std_logic',
744 
      'width' => 1,
745 
    },
746 
    'sysgen_dut.to_register11_ce' => {
747 
      'hdlType' => 'std_logic',
748 
      'width' => 1,
749 
    },
750 
    'sysgen_dut.to_register11_clk' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'sysgen_dut.to_register11_clr' => {
755 
      'hdlType' => 'std_logic',
756 
      'width' => 1,
757 
    },
758 
    'sysgen_dut.to_register11_data_in' => {
759 
      'hdlType' => 'std_logic_vector(31 downto 0)',
760 
      'width' => 32,
761 
    },
762 
    'sysgen_dut.to_register11_en' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'sysgen_dut.to_register12_ce' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'sysgen_dut.to_register12_clk' => {
771 
      'hdlType' => 'std_logic',
772 
      'width' => 1,
773 
    },
774 
    'sysgen_dut.to_register12_clr' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'sysgen_dut.to_register12_data_in' => {
779 
      'hdlType' => 'std_logic',
780 
      'width' => 1,
781 
    },
782 
    'sysgen_dut.to_register12_en' => {
783 
      'hdlType' => 'std_logic',
784 
      'width' => 1,
785 
    },
786 
    'sysgen_dut.to_register13_ce' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'sysgen_dut.to_register13_clk' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'sysgen_dut.to_register13_clr' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'sysgen_dut.to_register13_data_in' => {
799 
      'hdlType' => 'std_logic_vector(31 downto 0)',
800 
      'width' => 32,
801 
    },
802 
    'sysgen_dut.to_register13_en' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'sysgen_dut.to_register14_ce' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'sysgen_dut.to_register14_clk' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'sysgen_dut.to_register14_clr' => {
815 
      'hdlType' => 'std_logic',
816 
      'width' => 1,
817 
    },
818 
    'sysgen_dut.to_register14_data_in' => {
819 
      'hdlType' => 'std_logic',
820 
      'width' => 1,
821 
    },
822 
    'sysgen_dut.to_register14_en' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'sysgen_dut.to_register15_ce' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'sysgen_dut.to_register15_clk' => {
831 
      'hdlType' => 'std_logic',
832 
      'width' => 1,
833 
    },
834 
    'sysgen_dut.to_register15_clr' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'sysgen_dut.to_register15_data_in' => {
839 
      'hdlType' => 'std_logic_vector(31 downto 0)',
840 
      'width' => 32,
841 
    },
842 
    'sysgen_dut.to_register15_en' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'sysgen_dut.to_register16_ce' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'sysgen_dut.to_register16_clk' => {
851 
      'hdlType' => 'std_logic',
852 
      'width' => 1,
853 
    },
854 
    'sysgen_dut.to_register16_clr' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'sysgen_dut.to_register16_data_in' => {
859 
      'hdlType' => 'std_logic',
860 
      'width' => 1,
861 
    },
862 
    'sysgen_dut.to_register16_en' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'sysgen_dut.to_register17_ce' => {
867 
      'hdlType' => 'std_logic',
868 
      'width' => 1,
869 
    },
870 
    'sysgen_dut.to_register17_clk' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'sysgen_dut.to_register17_clr' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'sysgen_dut.to_register17_data_in' => {
879 
      'hdlType' => 'std_logic_vector(31 downto 0)',
880 
      'width' => 32,
881 
    },
882 
    'sysgen_dut.to_register17_en' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'sysgen_dut.to_register18_ce' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'sysgen_dut.to_register18_clk' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'sysgen_dut.to_register18_clr' => {
895 
      'hdlType' => 'std_logic',
896 
      'width' => 1,
897 
    },
898 
    'sysgen_dut.to_register18_data_in' => {
899 
      'hdlType' => 'std_logic',
900 
      'width' => 1,
901 
    },
902 
    'sysgen_dut.to_register18_en' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'sysgen_dut.to_register19_ce' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'sysgen_dut.to_register19_clk' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'sysgen_dut.to_register19_clr' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
    'sysgen_dut.to_register19_data_in' => {
919 
      'hdlType' => 'std_logic',
920 
      'width' => 1,
921 
    },
922 
    'sysgen_dut.to_register19_en' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'sysgen_dut.to_register1_ce' => {
927 
      'hdlType' => 'std_logic',
928 
      'width' => 1,
929 
    },
930 
    'sysgen_dut.to_register1_clk' => {
931 
      'hdlType' => 'std_logic',
932 
      'width' => 1,
933 
    },
934 
    'sysgen_dut.to_register1_clr' => {
935 
      'hdlType' => 'std_logic',
936 
      'width' => 1,
937 
    },
938 
    'sysgen_dut.to_register1_data_in' => {
939 
      'hdlType' => 'std_logic_vector(31 downto 0)',
940 
      'width' => 32,
941 
    },
942 
    'sysgen_dut.to_register1_en' => {
943 
      'hdlType' => 'std_logic',
944 
      'width' => 1,
945 
    },
946 
    'sysgen_dut.to_register20_ce' => {
947 
      'hdlType' => 'std_logic',
948 
      'width' => 1,
949 
    },
950 
    'sysgen_dut.to_register20_clk' => {
951 
      'hdlType' => 'std_logic',
952 
      'width' => 1,
953 
    },
954 
    'sysgen_dut.to_register20_clr' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'sysgen_dut.to_register20_data_in' => {
959 
      'hdlType' => 'std_logic_vector(31 downto 0)',
960 
      'width' => 32,
961 
    },
962 
    'sysgen_dut.to_register20_en' => {
963 
      'hdlType' => 'std_logic',
964 
      'width' => 1,
965 
    },
966 
    'sysgen_dut.to_register21_ce' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'sysgen_dut.to_register21_clk' => {
971 
      'hdlType' => 'std_logic',
972 
      'width' => 1,
973 
    },
974 
    'sysgen_dut.to_register21_clr' => {
975 
      'hdlType' => 'std_logic',
976 
      'width' => 1,
977 
    },
978 
    'sysgen_dut.to_register21_data_in' => {
979 
      'hdlType' => 'std_logic',
980 
      'width' => 1,
981 
    },
982 
    'sysgen_dut.to_register21_en' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'sysgen_dut.to_register22_ce' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'sysgen_dut.to_register22_clk' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'sysgen_dut.to_register22_clr' => {
995 
      'hdlType' => 'std_logic',
996 
      'width' => 1,
997 
    },
998 
    'sysgen_dut.to_register22_data_in' => {
999 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1000 
      'width' => 32,
1001 
    },
1002 
    'sysgen_dut.to_register22_en' => {
1003 
      'hdlType' => 'std_logic',
1004 
      'width' => 1,
1005 
    },
1006 
    'sysgen_dut.to_register23_ce' => {
1007 
      'hdlType' => 'std_logic',
1008 
      'width' => 1,
1009 
    },
1010 
    'sysgen_dut.to_register23_clk' => {
1011 
      'hdlType' => 'std_logic',
1012 
      'width' => 1,
1013 
    },
1014 
    'sysgen_dut.to_register23_clr' => {
1015 
      'hdlType' => 'std_logic',
1016 
      'width' => 1,
1017 
    },
1018 
    'sysgen_dut.to_register23_data_in' => {
1019 
      'hdlType' => 'std_logic',
1020 
      'width' => 1,
1021 
    },
1022 
    'sysgen_dut.to_register23_en' => {
1023 
      'hdlType' => 'std_logic',
1024 
      'width' => 1,
1025 
    },
1026 
    'sysgen_dut.to_register24_ce' => {
1027 
      'hdlType' => 'std_logic',
1028 
      'width' => 1,
1029 
    },
1030 
    'sysgen_dut.to_register24_clk' => {
1031 
      'hdlType' => 'std_logic',
1032 
      'width' => 1,
1033 
    },
1034 
    'sysgen_dut.to_register24_clr' => {
1035 
      'hdlType' => 'std_logic',
1036 
      'width' => 1,
1037 
    },
1038 
    'sysgen_dut.to_register24_data_in' => {
1039 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1040 
      'width' => 32,
1041 
    },
1042 
    'sysgen_dut.to_register24_en' => {
1043 
      'hdlType' => 'std_logic',
1044 
      'width' => 1,
1045 
    },
1046 
    'sysgen_dut.to_register25_ce' => {
1047 
      'hdlType' => 'std_logic',
1048 
      'width' => 1,
1049 
    },
1050 
    'sysgen_dut.to_register25_clk' => {
1051 
      'hdlType' => 'std_logic',
1052 
      'width' => 1,
1053 
    },
1054 
    'sysgen_dut.to_register25_clr' => {
1055 
      'hdlType' => 'std_logic',
1056 
      'width' => 1,
1057 
    },
1058 
    'sysgen_dut.to_register25_data_in' => {
1059 
      'hdlType' => 'std_logic',
1060 
      'width' => 1,
1061 
    },
1062 
    'sysgen_dut.to_register25_en' => {
1063 
      'hdlType' => 'std_logic',
1064 
      'width' => 1,
1065 
    },
1066 
    'sysgen_dut.to_register26_ce' => {
1067 
      'hdlType' => 'std_logic',
1068 
      'width' => 1,
1069 
    },
1070 
    'sysgen_dut.to_register26_clk' => {
1071 
      'hdlType' => 'std_logic',
1072 
      'width' => 1,
1073 
    },
1074 
    'sysgen_dut.to_register26_clr' => {
1075 
      'hdlType' => 'std_logic',
1076 
      'width' => 1,
1077 
    },
1078 
    'sysgen_dut.to_register26_data_in' => {
1079 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1080 
      'width' => 32,
1081 
    },
1082 
    'sysgen_dut.to_register26_en' => {
1083 
      'hdlType' => 'std_logic',
1084 
      'width' => 1,
1085 
    },
1086 
    'sysgen_dut.to_register27_ce' => {
1087 
      'hdlType' => 'std_logic',
1088 
      'width' => 1,
1089 
    },
1090 
    'sysgen_dut.to_register27_clk' => {
1091 
      'hdlType' => 'std_logic',
1092 
      'width' => 1,
1093 
    },
1094 
    'sysgen_dut.to_register27_clr' => {
1095 
      'hdlType' => 'std_logic',
1096 
      'width' => 1,
1097 
    },
1098 
    'sysgen_dut.to_register27_data_in' => {
1099 
      'hdlType' => 'std_logic',
1100 
      'width' => 1,
1101 
    },
1102 
    'sysgen_dut.to_register27_en' => {
1103 
      'hdlType' => 'std_logic',
1104 
      'width' => 1,
1105 
    },
1106 
    'sysgen_dut.to_register28_ce' => {
1107 
      'hdlType' => 'std_logic',
1108 
      'width' => 1,
1109 
    },
1110 
    'sysgen_dut.to_register28_clk' => {
1111 
      'hdlType' => 'std_logic',
1112 
      'width' => 1,
1113 
    },
1114 
    'sysgen_dut.to_register28_clr' => {
1115 
      'hdlType' => 'std_logic',
1116 
      'width' => 1,
1117 
    },
1118 
    'sysgen_dut.to_register28_data_in' => {
1119 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1120 
      'width' => 32,
1121 
    },
1122 
    'sysgen_dut.to_register28_en' => {
1123 
      'hdlType' => 'std_logic',
1124 
      'width' => 1,
1125 
    },
1126 
    'sysgen_dut.to_register29_ce' => {
1127 
      'hdlType' => 'std_logic',
1128 
      'width' => 1,
1129 
    },
1130 
    'sysgen_dut.to_register29_clk' => {
1131 
      'hdlType' => 'std_logic',
1132 
      'width' => 1,
1133 
    },
1134 
    'sysgen_dut.to_register29_clr' => {
1135 
      'hdlType' => 'std_logic',
1136 
      'width' => 1,
1137 
    },
1138 
    'sysgen_dut.to_register29_data_in' => {
1139 
      'hdlType' => 'std_logic',
1140 
      'width' => 1,
1141 
    },
1142 
    'sysgen_dut.to_register29_en' => {
1143 
      'hdlType' => 'std_logic',
1144 
      'width' => 1,
1145 
    },
1146 
    'sysgen_dut.to_register2_ce' => {
1147 
      'hdlType' => 'std_logic',
1148 
      'width' => 1,
1149 
    },
1150 
    'sysgen_dut.to_register2_clk' => {
1151 
      'hdlType' => 'std_logic',
1152 
      'width' => 1,
1153 
    },
1154 
    'sysgen_dut.to_register2_clr' => {
1155 
      'hdlType' => 'std_logic',
1156 
      'width' => 1,
1157 
    },
1158 
    'sysgen_dut.to_register2_data_in' => {
1159 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1160 
      'width' => 32,
1161 
    },
1162 
    'sysgen_dut.to_register2_en' => {
1163 
      'hdlType' => 'std_logic',
1164 
      'width' => 1,
1165 
    },
1166 
    'sysgen_dut.to_register30_ce' => {
1167 
      'hdlType' => 'std_logic',
1168 
      'width' => 1,
1169 
    },
1170 
    'sysgen_dut.to_register30_clk' => {
1171 
      'hdlType' => 'std_logic',
1172 
      'width' => 1,
1173 
    },
1174 
    'sysgen_dut.to_register30_clr' => {
1175 
      'hdlType' => 'std_logic',
1176 
      'width' => 1,
1177 
    },
1178 
    'sysgen_dut.to_register30_data_in' => {
1179 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1180 
      'width' => 32,
1181 
    },
1182 
    'sysgen_dut.to_register30_en' => {
1183 
      'hdlType' => 'std_logic',
1184 
      'width' => 1,
1185 
    },
1186 
    'sysgen_dut.to_register31_ce' => {
1187 
      'hdlType' => 'std_logic',
1188 
      'width' => 1,
1189 
    },
1190 
    'sysgen_dut.to_register31_clk' => {
1191 
      'hdlType' => 'std_logic',
1192 
      'width' => 1,
1193 
    },
1194 
    'sysgen_dut.to_register31_clr' => {
1195 
      'hdlType' => 'std_logic',
1196 
      'width' => 1,
1197 
    },
1198 
    'sysgen_dut.to_register31_data_in' => {
1199 
      'hdlType' => 'std_logic',
1200 
      'width' => 1,
1201 
    },
1202 
    'sysgen_dut.to_register31_en' => {
1203 
      'hdlType' => 'std_logic',
1204 
      'width' => 1,
1205 
    },
1206 
    'sysgen_dut.to_register32_ce' => {
1207 
      'hdlType' => 'std_logic',
1208 
      'width' => 1,
1209 
    },
1210 
    'sysgen_dut.to_register32_clk' => {
1211 
      'hdlType' => 'std_logic',
1212 
      'width' => 1,
1213 
    },
1214 
    'sysgen_dut.to_register32_clr' => {
1215 
      'hdlType' => 'std_logic',
1216 
      'width' => 1,
1217 
    },
1218 
    'sysgen_dut.to_register32_data_in' => {
1219 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1220 
      'width' => 32,
1221 
    },
1222 
    'sysgen_dut.to_register32_en' => {
1223 
      'hdlType' => 'std_logic',
1224 
      'width' => 1,
1225 
    },
1226 
    'sysgen_dut.to_register33_ce' => {
1227 
      'hdlType' => 'std_logic',
1228 
      'width' => 1,
1229 
    },
1230 
    'sysgen_dut.to_register33_clk' => {
1231 
      'hdlType' => 'std_logic',
1232 
      'width' => 1,
1233 
    },
1234 
    'sysgen_dut.to_register33_clr' => {
1235 
      'hdlType' => 'std_logic',
1236 
      'width' => 1,
1237 
    },
1238 
    'sysgen_dut.to_register33_data_in' => {
1239 
      'hdlType' => 'std_logic',
1240 
      'width' => 1,
1241 
    },
1242 
    'sysgen_dut.to_register33_en' => {
1243 
      'hdlType' => 'std_logic',
1244 
      'width' => 1,
1245 
    },
1246 
    'sysgen_dut.to_register34_ce' => {
1247 
      'hdlType' => 'std_logic',
1248 
      'width' => 1,
1249 
    },
1250 
    'sysgen_dut.to_register34_clk' => {
1251 
      'hdlType' => 'std_logic',
1252 
      'width' => 1,
1253 
    },
1254 
    'sysgen_dut.to_register34_clr' => {
1255 
      'hdlType' => 'std_logic',
1256 
      'width' => 1,
1257 
    },
1258 
    'sysgen_dut.to_register34_data_in' => {
1259 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1260 
      'width' => 32,
1261 
    },
1262 
    'sysgen_dut.to_register34_en' => {
1263 
      'hdlType' => 'std_logic',
1264 
      'width' => 1,
1265 
    },
1266 
    'sysgen_dut.to_register3_ce' => {
1267 
      'hdlType' => 'std_logic',
1268 
      'width' => 1,
1269 
    },
1270 
    'sysgen_dut.to_register3_clk' => {
1271 
      'hdlType' => 'std_logic',
1272 
      'width' => 1,
1273 
    },
1274 
    'sysgen_dut.to_register3_clr' => {
1275 
      'hdlType' => 'std_logic',
1276 
      'width' => 1,
1277 
    },
1278 
    'sysgen_dut.to_register3_data_in' => {
1279 
      'hdlType' => 'std_logic',
1280 
      'width' => 1,
1281 
    },
1282 
    'sysgen_dut.to_register3_en' => {
1283 
      'hdlType' => 'std_logic',
1284 
      'width' => 1,
1285 
    },
1286 
    'sysgen_dut.to_register4_ce' => {
1287 
      'hdlType' => 'std_logic',
1288 
      'width' => 1,
1289 
    },
1290 
    'sysgen_dut.to_register4_clk' => {
1291 
      'hdlType' => 'std_logic',
1292 
      'width' => 1,
1293 
    },
1294 
    'sysgen_dut.to_register4_clr' => {
1295 
      'hdlType' => 'std_logic',
1296 
      'width' => 1,
1297 
    },
1298 
    'sysgen_dut.to_register4_data_in' => {
1299 
      'hdlType' => 'std_logic',
1300 
      'width' => 1,
1301 
    },
1302 
    'sysgen_dut.to_register4_en' => {
1303 
      'hdlType' => 'std_logic',
1304 
      'width' => 1,
1305 
    },
1306 
    'sysgen_dut.to_register5_ce' => {
1307 
      'hdlType' => 'std_logic',
1308 
      'width' => 1,
1309 
    },
1310 
    'sysgen_dut.to_register5_clk' => {
1311 
      'hdlType' => 'std_logic',
1312 
      'width' => 1,
1313 
    },
1314 
    'sysgen_dut.to_register5_clr' => {
1315 
      'hdlType' => 'std_logic',
1316 
      'width' => 1,
1317 
    },
1318 
    'sysgen_dut.to_register5_data_in' => {
1319 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1320 
      'width' => 32,
1321 
    },
1322 
    'sysgen_dut.to_register5_en' => {
1323 
      'hdlType' => 'std_logic',
1324 
      'width' => 1,
1325 
    },
1326 
    'sysgen_dut.to_register6_ce' => {
1327 
      'hdlType' => 'std_logic',
1328 
      'width' => 1,
1329 
    },
1330 
    'sysgen_dut.to_register6_clk' => {
1331 
      'hdlType' => 'std_logic',
1332 
      'width' => 1,
1333 
    },
1334 
    'sysgen_dut.to_register6_clr' => {
1335 
      'hdlType' => 'std_logic',
1336 
      'width' => 1,
1337 
    },
1338 
    'sysgen_dut.to_register6_data_in' => {
1339 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1340 
      'width' => 32,
1341 
    },
1342 
    'sysgen_dut.to_register6_en' => {
1343 
      'hdlType' => 'std_logic',
1344 
      'width' => 1,
1345 
    },
1346 
    'sysgen_dut.to_register7_ce' => {
1347 
      'hdlType' => 'std_logic',
1348 
      'width' => 1,
1349 
    },
1350 
    'sysgen_dut.to_register7_clk' => {
1351 
      'hdlType' => 'std_logic',
1352 
      'width' => 1,
1353 
    },
1354 
    'sysgen_dut.to_register7_clr' => {
1355 
      'hdlType' => 'std_logic',
1356 
      'width' => 1,
1357 
    },
1358 
    'sysgen_dut.to_register7_data_in' => {
1359 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1360 
      'width' => 32,
1361 
    },
1362 
    'sysgen_dut.to_register7_en' => {
1363 
      'hdlType' => 'std_logic',
1364 
      'width' => 1,
1365 
    },
1366 
    'sysgen_dut.to_register8_ce' => {
1367 
      'hdlType' => 'std_logic',
1368 
      'width' => 1,
1369 
    },
1370 
    'sysgen_dut.to_register8_clk' => {
1371 
      'hdlType' => 'std_logic',
1372 
      'width' => 1,
1373 
    },
1374 
    'sysgen_dut.to_register8_clr' => {
1375 
      'hdlType' => 'std_logic',
1376 
      'width' => 1,
1377 
    },
1378 
    'sysgen_dut.to_register8_data_in' => {
1379 
      'hdlType' => 'std_logic',
1380 
      'width' => 1,
1381 
    },
1382 
    'sysgen_dut.to_register8_en' => {
1383 
      'hdlType' => 'std_logic',
1384 
      'width' => 1,
1385 
    },
1386 
    'sysgen_dut.to_register9_ce' => {
1387 
      'hdlType' => 'std_logic',
1388 
      'width' => 1,
1389 
    },
1390 
    'sysgen_dut.to_register9_clk' => {
1391 
      'hdlType' => 'std_logic',
1392 
      'width' => 1,
1393 
    },
1394 
    'sysgen_dut.to_register9_clr' => {
1395 
      'hdlType' => 'std_logic',
1396 
      'width' => 1,
1397 
    },
1398 
    'sysgen_dut.to_register9_data_in' => {
1399 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1400 
      'width' => 32,
1401 
    },
1402 
    'sysgen_dut.to_register9_en' => {
1403 
      'hdlType' => 'std_logic',
1404 
      'width' => 1,
1405 
    },
1406 
    'to_register1.dout' => {
1407 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1408 
      'width' => 32,
1409 
    },
1410 
    'to_register10.dout' => {
1411 
      'hdlType' => 'std_logic',
1412 
      'width' => 1,
1413 
    },
1414 
    'to_register11.dout' => {
1415 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1416 
      'width' => 32,
1417 
    },
1418 
    'to_register12.dout' => {
1419 
      'hdlType' => 'std_logic',
1420 
      'width' => 1,
1421 
    },
1422 
    'to_register13.dout' => {
1423 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1424 
      'width' => 32,
1425 
    },
1426 
    'to_register14.dout' => {
1427 
      'hdlType' => 'std_logic',
1428 
      'width' => 1,
1429 
    },
1430 
    'to_register15.dout' => {
1431 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1432 
      'width' => 32,
1433 
    },
1434 
    'to_register16.dout' => {
1435 
      'hdlType' => 'std_logic',
1436 
      'width' => 1,
1437 
    },
1438 
    'to_register17.dout' => {
1439 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1440 
      'width' => 32,
1441 
    },
1442 
    'to_register18.dout' => {
1443 
      'hdlType' => 'std_logic',
1444 
      'width' => 1,
1445 
    },
1446 
    'to_register19.dout' => {
1447 
      'hdlType' => 'std_logic',
1448 
      'width' => 1,
1449 
    },
1450 
    'to_register2.dout' => {
1451 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1452 
      'width' => 32,
1453 
    },
1454 
    'to_register20.dout' => {
1455 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1456 
      'width' => 32,
1457 
    },
1458 
    'to_register21.dout' => {
1459 
      'hdlType' => 'std_logic',
1460 
      'width' => 1,
1461 
    },
1462 
    'to_register22.dout' => {
1463 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1464 
      'width' => 32,
1465 
    },
1466 
    'to_register23.dout' => {
1467 
      'hdlType' => 'std_logic',
1468 
      'width' => 1,
1469 
    },
1470 
    'to_register24.dout' => {
1471 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1472 
      'width' => 32,
1473 
    },
1474 
    'to_register25.dout' => {
1475 
      'hdlType' => 'std_logic',
1476 
      'width' => 1,
1477 
    },
1478 
    'to_register26.dout' => {
1479 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1480 
      'width' => 32,
1481 
    },
1482 
    'to_register27.dout' => {
1483 
      'hdlType' => 'std_logic',
1484 
      'width' => 1,
1485 
    },
1486 
    'to_register28.dout' => {
1487 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1488 
      'width' => 32,
1489 
    },
1490 
    'to_register29.dout' => {
1491 
      'hdlType' => 'std_logic',
1492 
      'width' => 1,
1493 
    },
1494 
    'to_register3.dout' => {
1495 
      'hdlType' => 'std_logic',
1496 
      'width' => 1,
1497 
    },
1498 
    'to_register30.dout' => {
1499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1500 
      'width' => 32,
1501 
    },
1502 
    'to_register31.dout' => {
1503 
      'hdlType' => 'std_logic',
1504 
      'width' => 1,
1505 
    },
1506 
    'to_register32.dout' => {
1507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1508 
      'width' => 32,
1509 
    },
1510 
    'to_register33.dout' => {
1511 
      'hdlType' => 'std_logic',
1512 
      'width' => 1,
1513 
    },
1514 
    'to_register34.dout' => {
1515 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1516 
      'width' => 32,
1517 
    },
1518 
    'to_register4.dout' => {
1519 
      'hdlType' => 'std_logic',
1520 
      'width' => 1,
1521 
    },
1522 
    'to_register5.dout' => {
1523 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1524 
      'width' => 32,
1525 
    },
1526 
    'to_register6.dout' => {
1527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1528 
      'width' => 32,
1529 
    },
1530 
    'to_register7.dout' => {
1531 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1532 
      'width' => 32,
1533 
    },
1534 
    'to_register8.dout' => {
1535 
      'hdlType' => 'std_logic',
1536 
      'width' => 1,
1537 
    },
1538 
    'to_register9.dout' => {
1539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1540 
      'width' => 32,
1541 
    },
1542 
  },
1543 
  'subblocks' => {
1544 
    'debug_in_1i' => {
1545 
      'connections' => { 'debug_in_1i' => '.debug_in_1i', },
1546 
      'entity' => {
1547 
        'attributes' => {
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4911 
    },
4912 
    'reg14_rd' => {
4913 
      'connections' => { 'reg14_rd' => 'sysgen_dut.reg14_rd', },
4914 
      'entity' => {
4915 
        'attributes' => {
4916 
          'entityAlreadyNetlisted' => 1,
4917 
          'isGateway' => 1,
4918 
          'is_floating_block' => 1,
4919 
        },
4920 
        'entityName' => 'reg14_rd',
4921 
        'ports' => {
4922 
          'reg14_rd' => {
4923 
            'attributes' => {
4924 
              'bin_pt' => 0,
4925 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
4926 
              'is_floating_block' => 1,
4927 
              'is_gateway_port' => 1,
4928 
              'must_be_hdl_vector' => 1,
4929 
              'period' => 1,
4930 
              'port_id' => 0,
4931 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
4932 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
4933 
              'timingConstraint' => 'none',
4934 
              'type' => 'UFix_32_0',
4935 
            },
4936 
            'direction' => 'in',
4937 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4938 
            'width' => 32,
4939 
          },
4940 
        },
4941 
      },
4942 
      'entityName' => 'reg14_rd',
4943 
    },
4944 
    'reg14_rv' => {
4945 
      'connections' => { 'reg14_rv' => 'sysgen_dut.reg14_rv', },
4946 
      'entity' => {
4947 
        'attributes' => {
4948 
          'entityAlreadyNetlisted' => 1,
4949 
          'isGateway' => 1,
4950 
          'is_floating_block' => 1,
4951 
        },
4952 
        'entityName' => 'reg14_rv',
4953 
        'ports' => {
4954 
          'reg14_rv' => {
4955 
            'attributes' => {
4956 
              'bin_pt' => 0,
4957 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
4958 
              'is_floating_block' => 1,
4959 
              'is_gateway_port' => 1,
4960 
              'must_be_hdl_vector' => 1,
4961 
              'period' => 1,
4962 
              'port_id' => 0,
4963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
4964 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
4965 
              'timingConstraint' => 'none',
4966 
              'type' => 'UFix_1_0',
4967 
            },
4968 
            'direction' => 'in',
4969 
            'hdlType' => 'std_logic',
4970 
            'width' => 1,
4971 
          },
4972 
        },
4973 
      },
4974 
      'entityName' => 'reg14_rv',
4975 
    },
4976 
    'reg14_td' => {
4977 
      'connections' => { 'reg14_td' => '.reg14_td', },
4978 
      'entity' => {
4979 
        'attributes' => {
4980 
          'entityAlreadyNetlisted' => 1,
4981 
          'isGateway' => 1,
4982 
          'is_floating_block' => 1,
4983 
        },
4984 
        'entityName' => 'reg14_td',
4985 
        'ports' => {
4986 
          'reg14_td' => {
4987 
            'attributes' => {
4988 
              'bin_pt' => 0,
4989 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
4990 
              'is_floating_block' => 1,
4991 
              'is_gateway_port' => 1,
4992 
              'must_be_hdl_vector' => 1,
4993 
              'period' => 1,
4994 
              'port_id' => 0,
4995 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
4996 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
4997 
              'timingConstraint' => 'none',
4998 
              'type' => 'UFix_32_0',
4999 
            },
5000 
            'direction' => 'out',
5001 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5002 
            'width' => 32,
5003 
          },
5004 
        },
5005 
      },
5006 
      'entityName' => 'reg14_td',
5007 
    },
5008 
    'reg14_tv' => {
5009 
      'connections' => { 'reg14_tv' => '.reg14_tv', },
5010 
      'entity' => {
5011 
        'attributes' => {
5012 
          'entityAlreadyNetlisted' => 1,
5013 
          'isGateway' => 1,
5014 
          'is_floating_block' => 1,
5015 
        },
5016 
        'entityName' => 'reg14_tv',
5017 
        'ports' => {
5018 
          'reg14_tv' => {
5019 
            'attributes' => {
5020 
              'bin_pt' => 0,
5021 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5022 
              'is_floating_block' => 1,
5023 
              'is_gateway_port' => 1,
5024 
              'must_be_hdl_vector' => 1,
5025 
              'period' => 1,
5026 
              'port_id' => 0,
5027 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5028 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5029 
              'timingConstraint' => 'none',
5030 
              'type' => 'Bool',
5031 
            },
5032 
            'direction' => 'out',
5033 
            'hdlType' => 'std_logic',
5034 
            'width' => 1,
5035 
          },
5036 
        },
5037 
      },
5038 
      'entityName' => 'reg14_tv',
5039 
    },
5040 
    'sysgen_dut' => {
5041 
      'connections' => {
5042 
        'clk' => '.clk',
5043 
        'debug_in_1i' => '.debug_in_1i',
5044 
        'debug_in_2i' => '.debug_in_2i',
5045 
        'debug_in_3i' => '.debug_in_3i',
5046 
        'debug_in_4i' => '.debug_in_4i',
5047 
        'dma_host2board_busy' => '.dma_host2board_busy',
5048 
        'dma_host2board_done' => '.dma_host2board_done',
5049 
        'from_register10_data_out' => 'from_register10.data_out',
5050 
        'from_register11_data_out' => 'from_register11.data_out',
5051 
        'from_register12_data_out' => 'from_register12.data_out',
5052 
        'from_register13_data_out' => 'from_register13.data_out',
5053 
        'from_register14_data_out' => 'from_register14.data_out',
5054 
        'from_register15_data_out' => 'from_register15.data_out',
5055 
        'from_register16_data_out' => 'from_register16.data_out',
5056 
        'from_register17_data_out' => 'from_register17.data_out',
5057 
        'from_register18_data_out' => 'from_register18.data_out',
5058 
        'from_register19_data_out' => 'from_register19.data_out',
5059 
        'from_register1_data_out' => 'from_register1.data_out',
5060 
        'from_register20_data_out' => 'from_register20.data_out',
5061 
        'from_register21_data_out' => 'from_register21.data_out',
5062 
        'from_register22_data_out' => 'from_register22.data_out',
5063 
        'from_register23_data_out' => 'from_register23.data_out',
5064 
        'from_register24_data_out' => 'from_register24.data_out',
5065 
        'from_register25_data_out' => 'from_register25.data_out',
5066 
        'from_register26_data_out' => 'from_register26.data_out',
5067 
        'from_register27_data_out' => 'from_register27.data_out',
5068 
        'from_register28_data_out' => 'from_register28.data_out',
5069 
        'from_register2_data_out' => 'from_register2.data_out',
5070 
        'from_register3_data_out' => 'from_register3.data_out',
5071 
        'from_register4_data_out' => 'from_register4.data_out',
5072 
        'from_register5_data_out' => 'from_register5.data_out',
5073 
        'from_register6_data_out' => 'from_register6.data_out',
5074 
        'from_register7_data_out' => 'from_register7.data_out',
5075 
        'from_register8_data_out' => 'from_register8.data_out',
5076 
        'from_register9_data_out' => 'from_register9.data_out',
5077 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5078 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5079 
        'reg01_td' => '.reg01_td',
5080 
        'reg01_tv' => '.reg01_tv',
5081 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5082 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5083 
        'reg02_td' => '.reg02_td',
5084 
        'reg02_tv' => '.reg02_tv',
5085 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5086 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5087 
        'reg03_td' => '.reg03_td',
5088 
        'reg03_tv' => '.reg03_tv',
5089 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5090 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5091 
        'reg04_td' => '.reg04_td',
5092 
        'reg04_tv' => '.reg04_tv',
5093 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5094 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5095 
        'reg05_td' => '.reg05_td',
5096 
        'reg05_tv' => '.reg05_tv',
5097 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5098 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5099 
        'reg06_td' => '.reg06_td',
5100 
        'reg06_tv' => '.reg06_tv',
5101 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5102 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5103 
        'reg07_td' => '.reg07_td',
5104 
        'reg07_tv' => '.reg07_tv',
5105 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5106 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5107 
        'reg08_td' => '.reg08_td',
5108 
        'reg08_tv' => '.reg08_tv',
5109 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5110 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5111 
        'reg09_td' => '.reg09_td',
5112 
        'reg09_tv' => '.reg09_tv',
5113 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5114 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5115 
        'reg10_td' => '.reg10_td',
5116 
        'reg10_tv' => '.reg10_tv',
5117 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5118 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5119 
        'reg11_td' => '.reg11_td',
5120 
        'reg11_tv' => '.reg11_tv',
5121 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5122 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5123 
        'reg12_td' => '.reg12_td',
5124 
        'reg12_tv' => '.reg12_tv',
5125 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5126 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5127 
        'reg13_td' => '.reg13_td',
5128 
        'reg13_tv' => '.reg13_tv',
5129 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5130 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5131 
        'reg14_td' => '.reg14_td',
5132 
        'reg14_tv' => '.reg14_tv',
5133 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5134 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5135 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5136 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5137 
        'to_register10_dout' => 'to_register10.dout',
5138 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5139 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5140 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5141 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5142 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5143 
        'to_register11_dout' => 'to_register11.dout',
5144 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5145 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5146 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5147 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5148 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5149 
        'to_register12_dout' => 'to_register12.dout',
5150 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5151 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5152 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5153 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5154 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5155 
        'to_register13_dout' => 'to_register13.dout',
5156 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5157 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5158 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5159 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5160 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5161 
        'to_register14_dout' => 'to_register14.dout',
5162 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5163 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5164 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5165 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5166 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5167 
        'to_register15_dout' => 'to_register15.dout',
5168 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5169 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5170 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5171 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5172 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5173 
        'to_register16_dout' => 'to_register16.dout',
5174 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5175 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5176 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5177 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5178 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5179 
        'to_register17_dout' => 'to_register17.dout',
5180 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5181 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5182 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5183 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5184 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5185 
        'to_register18_dout' => 'to_register18.dout',
5186 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5187 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5188 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5189 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5190 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5191 
        'to_register19_dout' => 'to_register19.dout',
5192 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5193 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5194 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5195 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5196 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5197 
        'to_register1_dout' => 'to_register1.dout',
5198 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5199 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5200 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5201 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5202 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5203 
        'to_register20_dout' => 'to_register20.dout',
5204 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5205 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5206 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5207 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5208 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5209 
        'to_register21_dout' => 'to_register21.dout',
5210 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5211 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5212 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5213 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5214 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5215 
        'to_register22_dout' => 'to_register22.dout',
5216 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5217 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5218 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5219 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5220 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5221 
        'to_register23_dout' => 'to_register23.dout',
5222 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5223 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5224 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5225 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5226 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5227 
        'to_register24_dout' => 'to_register24.dout',
5228 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5229 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5230 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5231 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5232 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5233 
        'to_register25_dout' => 'to_register25.dout',
5234 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5235 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5236 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5237 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5238 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5239 
        'to_register26_dout' => 'to_register26.dout',
5240 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5241 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5242 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5243 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5244 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5245 
        'to_register27_dout' => 'to_register27.dout',
5246 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5247 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5248 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5249 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5250 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5251 
        'to_register28_dout' => 'to_register28.dout',
5252 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5253 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5254 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5255 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5256 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5257 
        'to_register29_dout' => 'to_register29.dout',
5258 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5259 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5260 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5261 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5262 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5263 
        'to_register2_dout' => 'to_register2.dout',
5264 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5265 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5266 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5267 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5268 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5269 
        'to_register30_dout' => 'to_register30.dout',
5270 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5271 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5272 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5273 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5274 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5275 
        'to_register31_dout' => 'to_register31.dout',
5276 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5277 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5278 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5279 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5280 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5281 
        'to_register32_dout' => 'to_register32.dout',
5282 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5283 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5284 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5285 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5286 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5287 
        'to_register33_dout' => 'to_register33.dout',
5288 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5289 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5290 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5291 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5292 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5293 
        'to_register34_dout' => 'to_register34.dout',
5294 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5295 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5296 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5297 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5298 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5299 
        'to_register3_dout' => 'to_register3.dout',
5300 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5301 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5302 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5303 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5304 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5305 
        'to_register4_dout' => 'to_register4.dout',
5306 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5307 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5308 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5309 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5310 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5311 
        'to_register5_dout' => 'to_register5.dout',
5312 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5313 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5314 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5315 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5316 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5317 
        'to_register6_dout' => 'to_register6.dout',
5318 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5319 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5320 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5321 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5322 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5323 
        'to_register7_dout' => 'to_register7.dout',
5324 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5325 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5326 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5327 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5328 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5329 
        'to_register8_dout' => 'to_register8.dout',
5330 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5331 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5332 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5333 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5334 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5335 
        'to_register9_dout' => 'to_register9.dout',
5336 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5337 
      },
5338 
      'entity' => {
5339 
        'attributes' => {
5340 
          'entityAlreadyNetlisted' => 1,
5341 
          'hdlArchAttributes' => [],
5342 
          'hdlEntityAttributes' => [],
5343 
          'isClkWrapper' => 1,
5344 
        },
5345 
        'connections' => {
5346 
          'clk' => 'clkNet',
5347 
          'debug_in_1i' => 'debug_in_1i_net',
5348 
          'debug_in_2i' => 'debug_in_2i_net',
5349 
          'debug_in_3i' => 'debug_in_3i_net',
5350 
          'debug_in_4i' => 'debug_in_4i_net',
5351 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5352 
          'dma_host2board_done' => 'dma_host2board_done_net',
5353 
          'from_register10_data_out' => 'from_register10_data_out_net',
5354 
          'from_register11_data_out' => 'from_register11_data_out_net',
5355 
          'from_register12_data_out' => 'from_register12_data_out_net',
5356 
          'from_register13_data_out' => 'from_register13_data_out_net',
5357 
          'from_register14_data_out' => 'from_register14_data_out_net',
5358 
          'from_register15_data_out' => 'from_register15_data_out_net',
5359 
          'from_register16_data_out' => 'from_register16_data_out_net',
5360 
          'from_register17_data_out' => 'from_register17_data_out_net',
5361 
          'from_register18_data_out' => 'from_register18_data_out_net',
5362 
          'from_register19_data_out' => 'from_register19_data_out_net',
5363 
          'from_register1_data_out' => 'from_register1_data_out_net',
5364 
          'from_register20_data_out' => 'from_register20_data_out_net',
5365 
          'from_register21_data_out' => 'from_register21_data_out_net',
5366 
          'from_register22_data_out' => 'from_register22_data_out_net',
5367 
          'from_register23_data_out' => 'from_register23_data_out_net',
5368 
          'from_register24_data_out' => 'from_register24_data_out_net',
5369 
          'from_register25_data_out' => 'from_register25_data_out_net',
5370 
          'from_register26_data_out' => 'from_register26_data_out_net',
5371 
          'from_register27_data_out' => 'from_register27_data_out_net',
5372 
          'from_register28_data_out' => 'from_register28_data_out_net',
5373 
          'from_register2_data_out' => 'from_register2_data_out_net',
5374 
          'from_register3_data_out' => 'from_register3_data_out_net',
5375 
          'from_register4_data_out' => 'from_register4_data_out_net',
5376 
          'from_register5_data_out' => 'from_register5_data_out_net',
5377 
          'from_register6_data_out' => 'from_register6_data_out_net',
5378 
          'from_register7_data_out' => 'from_register7_data_out_net',
5379 
          'from_register8_data_out' => 'from_register8_data_out_net',
5380 
          'from_register9_data_out' => 'from_register9_data_out_net',
5381 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5382 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5383 
          'reg01_td' => 'reg01_td_net',
5384 
          'reg01_tv' => 'reg01_tv_net',
5385 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5386 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5387 
          'reg02_td' => 'reg02_td_net',
5388 
          'reg02_tv' => 'reg02_tv_net',
5389 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5390 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5391 
          'reg03_td' => 'reg03_td_net',
5392 
          'reg03_tv' => 'reg03_tv_net',
5393 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5394 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5395 
          'reg04_td' => 'reg04_td_net',
5396 
          'reg04_tv' => 'reg04_tv_net',
5397 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5398 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5399 
          'reg05_td' => 'reg05_td_net',
5400 
          'reg05_tv' => 'reg05_tv_net',
5401 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5402 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5403 
          'reg06_td' => 'reg06_td_net',
5404 
          'reg06_tv' => 'reg06_tv_net',
5405 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5406 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5407 
          'reg07_td' => 'reg07_td_net',
5408 
          'reg07_tv' => 'reg07_tv_net',
5409 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5410 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5411 
          'reg08_td' => 'reg08_td_net',
5412 
          'reg08_tv' => 'reg08_tv_net',
5413 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5414 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5415 
          'reg09_td' => 'reg09_td_net',
5416 
          'reg09_tv' => 'reg09_tv_net',
5417 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5418 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5419 
          'reg10_td' => 'reg10_td_net',
5420 
          'reg10_tv' => 'reg10_tv_net',
5421 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5422 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5423 
          'reg11_td' => 'reg11_td_net',
5424 
          'reg11_tv' => 'reg11_tv_net',
5425 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5426 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5427 
          'reg12_td' => 'reg12_td_net',
5428 
          'reg12_tv' => 'reg12_tv_net',
5429 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5430 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5431 
          'reg13_td' => 'reg13_td_net',
5432 
          'reg13_tv' => 'reg13_tv_net',
5433 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5434 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5435 
          'reg14_td' => 'reg14_td_net',
5436 
          'reg14_tv' => 'reg14_tv_net',
5437 
          'to_register10_ce' => 'ce_1_sg',
5438 
          'to_register10_clk' => 'clk_1_sg',
5439 
          'to_register10_clr' => [
5440 
            'constant',
5441 
            '\'0\'',
5442 
          ],
5443 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5444 
          'to_register10_dout' => 'to_register10_dout_net',
5445 
          'to_register10_en' => 'constant5_op_net_x1',
5446 
          'to_register11_ce' => 'ce_1_sg',
5447 
          'to_register11_clk' => 'clk_1_sg',
5448 
          'to_register11_clr' => [
5449 
            'constant',
5450 
            '\'0\'',
5451 
          ],
5452 
          'to_register11_data_in' => 'reg04_td_net_x0',
5453 
          'to_register11_dout' => 'to_register11_dout_net',
5454 
          'to_register11_en' => 'constant5_op_net_x2',
5455 
          'to_register12_ce' => 'ce_1_sg',
5456 
          'to_register12_clk' => 'clk_1_sg',
5457 
          'to_register12_clr' => [
5458 
            'constant',
5459 
            '\'0\'',
5460 
          ],
5461 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5462 
          'to_register12_dout' => 'to_register12_dout_net',
5463 
          'to_register12_en' => 'constant5_op_net_x3',
5464 
          'to_register13_ce' => 'ce_1_sg',
5465 
          'to_register13_clk' => 'clk_1_sg',
5466 
          'to_register13_clr' => [
5467 
            'constant',
5468 
            '\'0\'',
5469 
          ],
5470 
          'to_register13_data_in' => 'reg05_td_net_x0',
5471 
          'to_register13_dout' => 'to_register13_dout_net',
5472 
          'to_register13_en' => 'constant5_op_net_x4',
5473 
          'to_register14_ce' => 'ce_1_sg',
5474 
          'to_register14_clk' => 'clk_1_sg',
5475 
          'to_register14_clr' => [
5476 
            'constant',
5477 
            '\'0\'',
5478 
          ],
5479 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5480 
          'to_register14_dout' => 'to_register14_dout_net',
5481 
          'to_register14_en' => 'constant5_op_net_x5',
5482 
          'to_register15_ce' => 'ce_1_sg',
5483 
          'to_register15_clk' => 'clk_1_sg',
5484 
          'to_register15_clr' => [
5485 
            'constant',
5486 
            '\'0\'',
5487 
          ],
5488 
          'to_register15_data_in' => 'reg06_td_net_x0',
5489 
          'to_register15_dout' => 'to_register15_dout_net',
5490 
          'to_register15_en' => 'constant5_op_net_x6',
5491 
          'to_register16_ce' => 'ce_1_sg',
5492 
          'to_register16_clk' => 'clk_1_sg',
5493 
          'to_register16_clr' => [
5494 
            'constant',
5495 
            '\'0\'',
5496 
          ],
5497 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5498 
          'to_register16_dout' => 'to_register16_dout_net',
5499 
          'to_register16_en' => 'constant5_op_net_x7',
5500 
          'to_register17_ce' => 'ce_1_sg',
5501 
          'to_register17_clk' => 'clk_1_sg',
5502 
          'to_register17_clr' => [
5503 
            'constant',
5504 
            '\'0\'',
5505 
          ],
5506 
          'to_register17_data_in' => 'reg07_td_net_x0',
5507 
          'to_register17_dout' => 'to_register17_dout_net',
5508 
          'to_register17_en' => 'constant5_op_net_x8',
5509 
          'to_register18_ce' => 'ce_1_sg',
5510 
          'to_register18_clk' => 'clk_1_sg',
5511 
          'to_register18_clr' => [
5512 
            'constant',
5513 
            '\'0\'',
5514 
          ],
5515 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5516 
          'to_register18_dout' => 'to_register18_dout_net',
5517 
          'to_register18_en' => 'constant5_op_net_x9',
5518 
          'to_register19_ce' => 'ce_1_sg',
5519 
          'to_register19_clk' => 'clk_1_sg',
5520 
          'to_register19_clr' => [
5521 
            'constant',
5522 
            '\'0\'',
5523 
          ],
5524 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5525 
          'to_register19_dout' => 'to_register19_dout_net',
5526 
          'to_register19_en' => 'constant5_op_net_x10',
5527 
          'to_register1_ce' => 'ce_1_sg',
5528 
          'to_register1_clk' => 'clk_1_sg',
5529 
          'to_register1_clr' => [
5530 
            'constant',
5531 
            '\'0\'',
5532 
          ],
5533 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5534 
          'to_register1_dout' => 'to_register1_dout_net',
5535 
          'to_register1_en' => 'constant5_op_net_x0',
5536 
          'to_register20_ce' => 'ce_1_sg',
5537 
          'to_register20_clk' => 'clk_1_sg',
5538 
          'to_register20_clr' => [
5539 
            'constant',
5540 
            '\'0\'',
5541 
          ],
5542 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5543 
          'to_register20_dout' => 'to_register20_dout_net',
5544 
          'to_register20_en' => 'constant5_op_net_x12',
5545 
          'to_register21_ce' => 'ce_1_sg',
5546 
          'to_register21_clk' => 'clk_1_sg',
5547 
          'to_register21_clr' => [
5548 
            'constant',
5549 
            '\'0\'',
5550 
          ],
5551 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5552 
          'to_register21_dout' => 'to_register21_dout_net',
5553 
          'to_register21_en' => 'constant1_op_net_x0',
5554 
          'to_register22_ce' => 'ce_1_sg',
5555 
          'to_register22_clk' => 'clk_1_sg',
5556 
          'to_register22_clr' => [
5557 
            'constant',
5558 
            '\'0\'',
5559 
          ],
5560 
          'to_register22_data_in' => 'reg09_td_net_x0',
5561 
          'to_register22_dout' => 'to_register22_dout_net',
5562 
          'to_register22_en' => 'constant1_op_net_x1',
5563 
          'to_register23_ce' => 'ce_1_sg',
5564 
          'to_register23_clk' => 'clk_1_sg',
5565 
          'to_register23_clr' => [
5566 
            'constant',
5567 
            '\'0\'',
5568 
          ],
5569 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5570 
          'to_register23_dout' => 'to_register23_dout_net',
5571 
          'to_register23_en' => 'constant1_op_net_x2',
5572 
          'to_register24_ce' => 'ce_1_sg',
5573 
          'to_register24_clk' => 'clk_1_sg',
5574 
          'to_register24_clr' => [
5575 
            'constant',
5576 
            '\'0\'',
5577 
          ],
5578 
          'to_register24_data_in' => 'reg10_td_net_x0',
5579 
          'to_register24_dout' => 'to_register24_dout_net',
5580 
          'to_register24_en' => 'constant1_op_net_x3',
5581 
          'to_register25_ce' => 'ce_1_sg',
5582 
          'to_register25_clk' => 'clk_1_sg',
5583 
          'to_register25_clr' => [
5584 
            'constant',
5585 
            '\'0\'',
5586 
          ],
5587 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5588 
          'to_register25_dout' => 'to_register25_dout_net',
5589 
          'to_register25_en' => 'constant1_op_net_x4',
5590 
          'to_register26_ce' => 'ce_1_sg',
5591 
          'to_register26_clk' => 'clk_1_sg',
5592 
          'to_register26_clr' => [
5593 
            'constant',
5594 
            '\'0\'',
5595 
          ],
5596 
          'to_register26_data_in' => 'reg08_td_net_x0',
5597 
          'to_register26_dout' => 'to_register26_dout_net',
5598 
          'to_register26_en' => 'constant1_op_net_x5',
5599 
          'to_register27_ce' => 'ce_1_sg',
5600 
          'to_register27_clk' => 'clk_1_sg',
5601 
          'to_register27_clr' => [
5602 
            'constant',
5603 
            '\'0\'',
5604 
          ],
5605 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5606 
          'to_register27_dout' => 'to_register27_dout_net',
5607 
          'to_register27_en' => 'constant1_op_net_x6',
5608 
          'to_register28_ce' => 'ce_1_sg',
5609 
          'to_register28_clk' => 'clk_1_sg',
5610 
          'to_register28_clr' => [
5611 
            'constant',
5612 
            '\'0\'',
5613 
          ],
5614 
          'to_register28_data_in' => 'reg11_td_net_x0',
5615 
          'to_register28_dout' => 'to_register28_dout_net',
5616 
          'to_register28_en' => 'constant1_op_net_x7',
5617 
          'to_register29_ce' => 'ce_1_sg',
5618 
          'to_register29_clk' => 'clk_1_sg',
5619 
          'to_register29_clr' => [
5620 
            'constant',
5621 
            '\'0\'',
5622 
          ],
5623 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5624 
          'to_register29_dout' => 'to_register29_dout_net',
5625 
          'to_register29_en' => 'constant1_op_net_x8',
5626 
          'to_register2_ce' => 'ce_1_sg',
5627 
          'to_register2_clk' => 'clk_1_sg',
5628 
          'to_register2_clr' => [
5629 
            'constant',
5630 
            '\'0\'',
5631 
          ],
5632 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5633 
          'to_register2_dout' => 'to_register2_dout_net',
5634 
          'to_register2_en' => 'constant5_op_net_x11',
5635 
          'to_register30_ce' => 'ce_1_sg',
5636 
          'to_register30_clk' => 'clk_1_sg',
5637 
          'to_register30_clr' => [
5638 
            'constant',
5639 
            '\'0\'',
5640 
          ],
5641 
          'to_register30_data_in' => 'reg12_td_net_x0',
5642 
          'to_register30_dout' => 'to_register30_dout_net',
5643 
          'to_register30_en' => 'constant1_op_net_x9',
5644 
          'to_register31_ce' => 'ce_1_sg',
5645 
          'to_register31_clk' => 'clk_1_sg',
5646 
          'to_register31_clr' => [
5647 
            'constant',
5648 
            '\'0\'',
5649 
          ],
5650 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5651 
          'to_register31_dout' => 'to_register31_dout_net',
5652 
          'to_register31_en' => 'constant1_op_net_x10',
5653 
          'to_register32_ce' => 'ce_1_sg',
5654 
          'to_register32_clk' => 'clk_1_sg',
5655 
          'to_register32_clr' => [
5656 
            'constant',
5657 
            '\'0\'',
5658 
          ],
5659 
          'to_register32_data_in' => 'reg13_td_net_x0',
5660 
          'to_register32_dout' => 'to_register32_dout_net',
5661 
          'to_register32_en' => 'constant1_op_net_x11',
5662 
          'to_register33_ce' => 'ce_1_sg',
5663 
          'to_register33_clk' => 'clk_1_sg',
5664 
          'to_register33_clr' => [
5665 
            'constant',
5666 
            '\'0\'',
5667 
          ],
5668 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5669 
          'to_register33_dout' => 'to_register33_dout_net',
5670 
          'to_register33_en' => 'constant1_op_net_x12',
5671 
          'to_register34_ce' => 'ce_1_sg',
5672 
          'to_register34_clk' => 'clk_1_sg',
5673 
          'to_register34_clr' => [
5674 
            'constant',
5675 
            '\'0\'',
5676 
          ],
5677 
          'to_register34_data_in' => 'reg14_td_net_x0',
5678 
          'to_register34_dout' => 'to_register34_dout_net',
5679 
          'to_register34_en' => 'constant1_op_net_x13',
5680 
          'to_register3_ce' => 'ce_1_sg',
5681 
          'to_register3_clk' => 'clk_1_sg',
5682 
          'to_register3_clr' => [
5683 
            'constant',
5684 
            '\'0\'',
5685 
          ],
5686 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5687 
          'to_register3_dout' => 'to_register3_dout_net',
5688 
          'to_register3_en' => 'constant5_op_net_x13',
5689 
          'to_register4_ce' => 'ce_1_sg',
5690 
          'to_register4_clk' => 'clk_1_sg',
5691 
          'to_register4_clr' => [
5692 
            'constant',
5693 
            '\'0\'',
5694 
          ],
5695 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5696 
          'to_register4_dout' => 'to_register4_dout_net',
5697 
          'to_register4_en' => 'constant5_op_net_x14',
5698 
          'to_register5_ce' => 'ce_1_sg',
5699 
          'to_register5_clk' => 'clk_1_sg',
5700 
          'to_register5_clr' => [
5701 
            'constant',
5702 
            '\'0\'',
5703 
          ],
5704 
          'to_register5_data_in' => 'reg02_td_net_x0',
5705 
          'to_register5_dout' => 'to_register5_dout_net',
5706 
          'to_register5_en' => 'constant5_op_net_x15',
5707 
          'to_register6_ce' => 'ce_1_sg',
5708 
          'to_register6_clk' => 'clk_1_sg',
5709 
          'to_register6_clr' => [
5710 
            'constant',
5711 
            '\'0\'',
5712 
          ],
5713 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5714 
          'to_register6_dout' => 'to_register6_dout_net',
5715 
          'to_register6_en' => 'constant5_op_net_x16',
5716 
          'to_register7_ce' => 'ce_1_sg',
5717 
          'to_register7_clk' => 'clk_1_sg',
5718 
          'to_register7_clr' => [
5719 
            'constant',
5720 
            '\'0\'',
5721 
          ],
5722 
          'to_register7_data_in' => 'reg01_td_net_x0',
5723 
          'to_register7_dout' => 'to_register7_dout_net',
5724 
          'to_register7_en' => 'constant5_op_net_x17',
5725 
          'to_register8_ce' => 'ce_1_sg',
5726 
          'to_register8_clk' => 'clk_1_sg',
5727 
          'to_register8_clr' => [
5728 
            'constant',
5729 
            '\'0\'',
5730 
          ],
5731 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5732 
          'to_register8_dout' => 'to_register8_dout_net',
5733 
          'to_register8_en' => 'constant5_op_net_x18',
5734 
          'to_register9_ce' => 'ce_1_sg',
5735 
          'to_register9_clk' => 'clk_1_sg',
5736 
          'to_register9_clr' => [
5737 
            'constant',
5738 
            '\'0\'',
5739 
          ],
5740 
          'to_register9_data_in' => 'reg03_td_net_x0',
5741 
          'to_register9_dout' => 'to_register9_dout_net',
5742 
          'to_register9_en' => 'constant5_op_net_x19',
5743 
        },
5744 
        'entityName' => 'inout_logic_cw',
5745 
        'nets' => {
5746 
          'ce_1_sg' => {
5747 
            'attributes' => {
5748 
              'hdlNetAttributes' => [
5749 
                [
5750 
                  'MAX_FANOUT',
5751 
                  'string',
5752 
                  '"REDUCE"',
5753 
                ],
5754 
              ],
5755 
            },
5756 
            'hdlType' => 'std_logic',
5757 
            'width' => 1,
5758 
          },
5759 
          'clkNet' => {
5760 
            'attributes' => {
5761 
              'hdlNetAttributes' => [],
5762 
            },
5763 
            'hdlType' => 'std_logic',
5764 
            'width' => 1,
5765 
          },
5766 
          'clk_1_sg' => {
5767 
            'attributes' => {
5768 
              'hdlNetAttributes' => [],
5769 
            },
5770 
            'hdlType' => 'std_logic',
5771 
            'width' => 1,
5772 
          },
5773 
          'constant1_op_net_x0' => {
5774 
            'attributes' => {
5775 
              'hdlNetAttributes' => [],
5776 
            },
5777 
            'hdlType' => 'std_logic',
5778 
            'width' => 1,
5779 
          },
5780 
          'constant1_op_net_x1' => {
5781 
            'attributes' => {
5782 
              'hdlNetAttributes' => [],
5783 
            },
5784 
            'hdlType' => 'std_logic',
5785 
            'width' => 1,
5786 
          },
5787 
          'constant1_op_net_x10' => {
5788 
            'attributes' => {
5789 
              'hdlNetAttributes' => [],
5790 
            },
5791 
            'hdlType' => 'std_logic',
5792 
            'width' => 1,
5793 
          },
5794 
          'constant1_op_net_x11' => {
5795 
            'attributes' => {
5796 
              'hdlNetAttributes' => [],
5797 
            },
5798 
            'hdlType' => 'std_logic',
5799 
            'width' => 1,
5800 
          },
5801 
          'constant1_op_net_x12' => {
5802 
            'attributes' => {
5803 
              'hdlNetAttributes' => [],
5804 
            },
5805 
            'hdlType' => 'std_logic',
5806 
            'width' => 1,
5807 
          },
5808 
          'constant1_op_net_x13' => {
5809 
            'attributes' => {
5810 
              'hdlNetAttributes' => [],
5811 
            },
5812 
            'hdlType' => 'std_logic',
5813 
            'width' => 1,
5814 
          },
5815 
          'constant1_op_net_x2' => {
5816 
            'attributes' => {
5817 
              'hdlNetAttributes' => [],
5818 
            },
5819 
            'hdlType' => 'std_logic',
5820 
            'width' => 1,
5821 
          },
5822 
          'constant1_op_net_x3' => {
5823 
            'attributes' => {
5824 
              'hdlNetAttributes' => [],
5825 
            },
5826 
            'hdlType' => 'std_logic',
5827 
            'width' => 1,
5828 
          },
5829 
          'constant1_op_net_x4' => {
5830 
            'attributes' => {
5831 
              'hdlNetAttributes' => [],
5832 
            },
5833 
            'hdlType' => 'std_logic',
5834 
            'width' => 1,
5835 
          },
5836 
          'constant1_op_net_x5' => {
5837 
            'attributes' => {
5838 
              'hdlNetAttributes' => [],
5839 
            },
5840 
            'hdlType' => 'std_logic',
5841 
            'width' => 1,
5842 
          },
5843 
          'constant1_op_net_x6' => {
5844 
            'attributes' => {
5845 
              'hdlNetAttributes' => [],
5846 
            },
5847 
            'hdlType' => 'std_logic',
5848 
            'width' => 1,
5849 
          },
5850 
          'constant1_op_net_x7' => {
5851 
            'attributes' => {
5852 
              'hdlNetAttributes' => [],
5853 
            },
5854 
            'hdlType' => 'std_logic',
5855 
            'width' => 1,
5856 
          },
5857 
          'constant1_op_net_x8' => {
5858 
            'attributes' => {
5859 
              'hdlNetAttributes' => [],
5860 
            },
5861 
            'hdlType' => 'std_logic',
5862 
            'width' => 1,
5863 
          },
5864 
          'constant1_op_net_x9' => {
5865 
            'attributes' => {
5866 
              'hdlNetAttributes' => [],
5867 
            },
5868 
            'hdlType' => 'std_logic',
5869 
            'width' => 1,
5870 
          },
5871 
          'constant5_op_net_x0' => {
5872 
            'attributes' => {
5873 
              'hdlNetAttributes' => [],
5874 
            },
5875 
            'hdlType' => 'std_logic',
5876 
            'width' => 1,
5877 
          },
5878 
          'constant5_op_net_x1' => {
5879 
            'attributes' => {
5880 
              'hdlNetAttributes' => [],
5881 
            },
5882 
            'hdlType' => 'std_logic',
5883 
            'width' => 1,
5884 
          },
5885 
          'constant5_op_net_x10' => {
5886 
            'attributes' => {
5887 
              'hdlNetAttributes' => [],
5888 
            },
5889 
            'hdlType' => 'std_logic',
5890 
            'width' => 1,
5891 
          },
5892 
          'constant5_op_net_x11' => {
5893 
            'attributes' => {
5894 
              'hdlNetAttributes' => [],
5895 
            },
5896 
            'hdlType' => 'std_logic',
5897 
            'width' => 1,
5898 
          },
5899 
          'constant5_op_net_x12' => {
5900 
            'attributes' => {
5901 
              'hdlNetAttributes' => [],
5902 
            },
5903 
            'hdlType' => 'std_logic',
5904 
            'width' => 1,
5905 
          },
5906 
          'constant5_op_net_x13' => {
5907 
            'attributes' => {
5908 
              'hdlNetAttributes' => [],
5909 
            },
5910 
            'hdlType' => 'std_logic',
5911 
            'width' => 1,
5912 
          },
5913 
          'constant5_op_net_x14' => {
5914 
            'attributes' => {
5915 
              'hdlNetAttributes' => [],
5916 
            },
5917 
            'hdlType' => 'std_logic',
5918 
            'width' => 1,
5919 
          },
5920 
          'constant5_op_net_x15' => {
5921 
            'attributes' => {
5922 
              'hdlNetAttributes' => [],
5923 
            },
5924 
            'hdlType' => 'std_logic',
5925 
            'width' => 1,
5926 
          },
5927 
          'constant5_op_net_x16' => {
5928 
            'attributes' => {
5929 
              'hdlNetAttributes' => [],
5930 
            },
5931 
            'hdlType' => 'std_logic',
5932 
            'width' => 1,
5933 
          },
5934 
          'constant5_op_net_x17' => {
5935 
            'attributes' => {
5936 
              'hdlNetAttributes' => [],
5937 
            },
5938 
            'hdlType' => 'std_logic',
5939 
            'width' => 1,
5940 
          },
5941 
          'constant5_op_net_x18' => {
5942 
            'attributes' => {
5943 
              'hdlNetAttributes' => [],
5944 
            },
5945 
            'hdlType' => 'std_logic',
5946 
            'width' => 1,
5947 
          },
5948 
          'constant5_op_net_x19' => {
5949 
            'attributes' => {
5950 
              'hdlNetAttributes' => [],
5951 
            },
5952 
            'hdlType' => 'std_logic',
5953 
            'width' => 1,
5954 
          },
5955 
          'constant5_op_net_x2' => {
5956 
            'attributes' => {
5957 
              'hdlNetAttributes' => [],
5958 
            },
5959 
            'hdlType' => 'std_logic',
5960 
            'width' => 1,
5961 
          },
5962 
          'constant5_op_net_x3' => {
5963 
            'attributes' => {
5964 
              'hdlNetAttributes' => [],
5965 
            },
5966 
            'hdlType' => 'std_logic',
5967 
            'width' => 1,
5968 
          },
5969 
          'constant5_op_net_x4' => {
5970 
            'attributes' => {
5971 
              'hdlNetAttributes' => [],
5972 
            },
5973 
            'hdlType' => 'std_logic',
5974 
            'width' => 1,
5975 
          },
5976 
          'constant5_op_net_x5' => {
5977 
            'attributes' => {
5978 
              'hdlNetAttributes' => [],
5979 
            },
5980 
            'hdlType' => 'std_logic',
5981 
            'width' => 1,
5982 
          },
5983 
          'constant5_op_net_x6' => {
5984 
            'attributes' => {
5985 
              'hdlNetAttributes' => [],
5986 
            },
5987 
            'hdlType' => 'std_logic',
5988 
            'width' => 1,
5989 
          },
5990 
          'constant5_op_net_x7' => {
5991 
            'attributes' => {
5992 
              'hdlNetAttributes' => [],
5993 
            },
5994 
            'hdlType' => 'std_logic',
5995 
            'width' => 1,
5996 
          },
5997 
          'constant5_op_net_x8' => {
5998 
            'attributes' => {
5999 
              'hdlNetAttributes' => [],
6000 
            },
6001 
            'hdlType' => 'std_logic',
6002 
            'width' => 1,
6003 
          },
6004 
          'constant5_op_net_x9' => {
6005 
            'attributes' => {
6006 
              'hdlNetAttributes' => [],
6007 
            },
6008 
            'hdlType' => 'std_logic',
6009 
            'width' => 1,
6010 
          },
6011 
          'debug_in_1i_net' => {
6012 
            'attributes' => {
6013 
              'hdlNetAttributes' => [],
6014 
            },
6015 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6016 
            'width' => 32,
6017 
          },
6018 
          'debug_in_1i_net_x0' => {
6019 
            'attributes' => {
6020 
              'hdlNetAttributes' => [],
6021 
            },
6022 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6023 
            'width' => 32,
6024 
          },
6025 
          'debug_in_2i_net' => {
6026 
            'attributes' => {
6027 
              'hdlNetAttributes' => [],
6028 
            },
6029 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6030 
            'width' => 32,
6031 
          },
6032 
          'debug_in_2i_net_x0' => {
6033 
            'attributes' => {
6034 
              'hdlNetAttributes' => [],
6035 
            },
6036 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6037 
            'width' => 32,
6038 
          },
6039 
          'debug_in_3i_net' => {
6040 
            'attributes' => {
6041 
              'hdlNetAttributes' => [],
6042 
            },
6043 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6044 
            'width' => 32,
6045 
          },
6046 
          'debug_in_3i_net_x0' => {
6047 
            'attributes' => {
6048 
              'hdlNetAttributes' => [],
6049 
            },
6050 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6051 
            'width' => 32,
6052 
          },
6053 
          'debug_in_4i_net' => {
6054 
            'attributes' => {
6055 
              'hdlNetAttributes' => [],
6056 
            },
6057 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6058 
            'width' => 32,
6059 
          },
6060 
          'debug_in_4i_net_x0' => {
6061 
            'attributes' => {
6062 
              'hdlNetAttributes' => [],
6063 
            },
6064 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6065 
            'width' => 32,
6066 
          },
6067 
          'dma_host2board_busy_net' => {
6068 
            'attributes' => {
6069 
              'hdlNetAttributes' => [],
6070 
            },
6071 
            'hdlType' => 'std_logic',
6072 
            'width' => 1,
6073 
          },
6074 
          'dma_host2board_busy_net_x0' => {
6075 
            'attributes' => {
6076 
              'hdlNetAttributes' => [],
6077 
            },
6078 
            'hdlType' => 'std_logic',
6079 
            'width' => 1,
6080 
          },
6081 
          'dma_host2board_done_net' => {
6082 
            'attributes' => {
6083 
              'hdlNetAttributes' => [],
6084 
            },
6085 
            'hdlType' => 'std_logic',
6086 
            'width' => 1,
6087 
          },
6088 
          'dma_host2board_done_net_x0' => {
6089 
            'attributes' => {
6090 
              'hdlNetAttributes' => [],
6091 
            },
6092 
            'hdlType' => 'std_logic',
6093 
            'width' => 1,
6094 
          },
6095 
          'from_register10_data_out_net' => {
6096 
            'attributes' => {
6097 
              'hdlNetAttributes' => [],
6098 
            },
6099 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6100 
            'width' => 32,
6101 
          },
6102 
          'from_register10_data_out_net_x0' => {
6103 
            'attributes' => {
6104 
              'hdlNetAttributes' => [],
6105 
            },
6106 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6107 
            'width' => 32,
6108 
          },
6109 
          'from_register11_data_out_net' => {
6110 
            'attributes' => {
6111 
              'hdlNetAttributes' => [],
6112 
            },
6113 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6114 
            'width' => 32,
6115 
          },
6116 
          'from_register11_data_out_net_x0' => {
6117 
            'attributes' => {
6118 
              'hdlNetAttributes' => [],
6119 
            },
6120 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6121 
            'width' => 32,
6122 
          },
6123 
          'from_register12_data_out_net' => {
6124 
            'attributes' => {
6125 
              'hdlNetAttributes' => [],
6126 
            },
6127 
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10795 
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10848 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
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10890 
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10915 
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10916 
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10924 
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10929 
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10930 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
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10949 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
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10957 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
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10989 
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10998 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
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11020 
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11024 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
11032 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
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11054 
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11055 
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11057 
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11058 
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11059 
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11060 
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11063 
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11065 
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11066 
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11067 
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11070 
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11071 
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11072 
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11079 
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11080 
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11084 
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11088 
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11090 
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11091 
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11092 
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11093 
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11094 
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11095 
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11096 
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11097 
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11104 
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11106 
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11107 
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11108 
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11110 
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11112 
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11113 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
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11116 
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11118 
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11119 
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11121 
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11122 
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11127 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11128 
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11136 
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11143 
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11149 
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11153 
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11154 
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11156 
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11158 
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11160 
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11161 
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11162 
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11163 
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11165 
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11166 
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11167 
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11170 
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11171 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
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11184 
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11185 
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11188 
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11189 
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11190 
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11200 
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11202 
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11203 
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11204 
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11210 
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11217 
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11218 
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11225 
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11231 
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11235 
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11244 
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11252 
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11253 
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11254 
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11255 
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11256 
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11257 
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11258 
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11259 
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11260 
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11261 
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11263 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
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11265 
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11266 
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11267 
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11268 
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11269 
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11270 
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11271 
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11272 
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11273 
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11274 
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11275 
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11277 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
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11284 
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11285 
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11286 
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11288 
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11289 
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11290 
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11291 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11292 
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11293 
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11294 
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11295 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11296 
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11297 
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11298 
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11299 
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11300 
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11301 
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11307 
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11310 
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11311 
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11312 
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11313 
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11314 
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11315 
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11316 
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11317 
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11318 
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11319 
            },
11320 
            'direction' => 'out',
11321 
            'hdlType' => 'std_logic',
11322 
            'width' => 1,
11323 
          },
11324 
          'to_register8_clr' => {
11325 
            'attributes' => {
11326 
              'domain' => '',
11327 
              'group' => 1,
11328 
              'isClr' => 1,
11329 
              'is_floating_block' => 1,
11330 
              'period' => 1,
11331 
              'type' => 'logic',
11332 
              'valid_bit_used' => 0,
11333 
            },
11334 
            'direction' => 'out',
11335 
            'hdlType' => 'std_logic',
11336 
            'width' => 1,
11337 
          },
11338 
          'to_register8_data_in' => {
11339 
            'attributes' => {
11340 
              'bin_pt' => 0,
11341 
              'is_floating_block' => 1,
11342 
              'must_be_hdl_vector' => 1,
11343 
              'period' => 1,
11344 
              'port_id' => 0,
11345 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11346 
              'type' => 'Bool',
11347 
            },
11348 
            'direction' => 'out',
11349 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11350 
            'width' => 1,
11351 
          },
11352 
          'to_register8_dout' => {
11353 
            'attributes' => {
11354 
              'bin_pt' => 0,
11355 
              'is_floating_block' => 1,
11356 
              'must_be_hdl_vector' => 1,
11357 
              'period' => 1,
11358 
              'port_id' => 0,
11359 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11360 
              'type' => 'Bool',
11361 
            },
11362 
            'direction' => 'in',
11363 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11364 
            'width' => 1,
11365 
          },
11366 
          'to_register8_en' => {
11367 
            'attributes' => {
11368 
              'bin_pt' => 0,
11369 
              'is_floating_block' => 1,
11370 
              'must_be_hdl_vector' => 1,
11371 
              'period' => 1,
11372 
              'port_id' => 1,
11373 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11374 
              'type' => 'Bool',
11375 
            },
11376 
            'direction' => 'out',
11377 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11378 
            'width' => 1,
11379 
          },
11380 
          'to_register9_ce' => {
11381 
            'attributes' => {
11382 
              'domain' => '',
11383 
              'group' => 1,
11384 
              'isCe' => 1,
11385 
              'is_floating_block' => 1,
11386 
              'period' => 1,
11387 
              'type' => 'logic',
11388 
            },
11389 
            'direction' => 'out',
11390 
            'hdlType' => 'std_logic',
11391 
            'width' => 1,
11392 
          },
11393 
          'to_register9_clk' => {
11394 
            'attributes' => {
11395 
              'domain' => '',
11396 
              'group' => 1,
11397 
              'isClk' => 1,
11398 
              'is_floating_block' => 1,
11399 
              'period' => 1,
11400 
              'type' => 'logic',
11401 
            },
11402 
            'direction' => 'out',
11403 
            'hdlType' => 'std_logic',
11404 
            'width' => 1,
11405 
          },
11406 
          'to_register9_clr' => {
11407 
            'attributes' => {
11408 
              'domain' => '',
11409 
              'group' => 1,
11410 
              'isClr' => 1,
11411 
              'is_floating_block' => 1,
11412 
              'period' => 1,
11413 
              'type' => 'logic',
11414 
              'valid_bit_used' => 0,
11415 
            },
11416 
            'direction' => 'out',
11417 
            'hdlType' => 'std_logic',
11418 
            'width' => 1,
11419 
          },
11420 
          'to_register9_data_in' => {
11421 
            'attributes' => {
11422 
              'bin_pt' => 0,
11423 
              'is_floating_block' => 1,
11424 
              'must_be_hdl_vector' => 1,
11425 
              'period' => 1,
11426 
              'port_id' => 0,
11427 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11428 
              'type' => 'UFix_32_0',
11429 
            },
11430 
            'direction' => 'out',
11431 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11432 
            'width' => 32,
11433 
          },
11434 
          'to_register9_dout' => {
11435 
            'attributes' => {
11436 
              'bin_pt' => 0,
11437 
              'is_floating_block' => 1,
11438 
              'must_be_hdl_vector' => 1,
11439 
              'period' => 1,
11440 
              'port_id' => 0,
11441 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11442 
              'type' => 'UFix_32_0',
11443 
            },
11444 
            'direction' => 'in',
11445 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11446 
            'width' => 32,
11447 
          },
11448 
          'to_register9_en' => {
11449 
            'attributes' => {
11450 
              'bin_pt' => 0,
11451 
              'is_floating_block' => 1,
11452 
              'must_be_hdl_vector' => 1,
11453 
              'period' => 1,
11454 
              'port_id' => 1,
11455 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11456 
              'type' => 'Bool',
11457 
            },
11458 
            'direction' => 'out',
11459 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11460 
            'width' => 1,
11461 
          },
11462 
        },
11463 
        'subblocks' => {
11464 
          'default_clock_driver_x0' => {
11465 
            'connections' => {
11466 
              'ce_1' => 'ce_1_sg',
11467 
              'clk_1' => 'clk_1_sg',
11468 
              'sysce' => [
11469 
                'constant',
11470 
                '\'1\'',
11471 
              ],
11472 
              'sysce_clr' => [
11473 
                'constant',
11474 
                '\'0\'',
11475 
              ],
11476 
              'sysclk' => 'clkNet',
11477 
            },
11478 
            'entity' => {
11479 
              'attributes' => {
11480 
                'domain' => 'default',
11481 
                'hdlArchAttributes' => [
11482 
                  [
11483 
                    'syn_noprune',
11484 
                    'boolean',
11485 
                    'true',
11486 
                  ],
11487 
                  [
11488 
                    'optimize_primitives',
11489 
                    'boolean',
11490 
                    'false',
11491 
                  ],
11492 
                  [
11493 
                    'dont_touch',
11494 
                    'boolean',
11495 
                    'true',
11496 
                  ],
11497 
                ],
11498 
                'hdlEntityAttributes' => [],
11499 
                'isClkDriver' => 1,
11500 
              },
11501 
              'entityName' => 'default_clock_driver',
11502 
              'ports' => {
11503 
                'ce_1' => {
11504 
                  'attributes' => {
11505 
                    'domain' => 'default',
11506 
                    'group' => 1,
11507 
                    'isCe' => 1,
11508 
                    'period' => 1,
11509 
                    'type' => 'logic',
11510 
                  },
11511 
                  'direction' => 'out',
11512 
                  'hdlType' => 'std_logic',
11513 
                  'width' => 1,
11514 
                },
11515 
                'clk_1' => {
11516 
                  'attributes' => {
11517 
                    'domain' => 'default',
11518 
                    'group' => 1,
11519 
                    'isClk' => 1,
11520 
                    'period' => 1,
11521 
                    'type' => 'logic',
11522 
                  },
11523 
                  'direction' => 'out',
11524 
                  'hdlType' => 'std_logic',
11525 
                  'width' => 1,
11526 
                },
11527 
                'sysce' => {
11528 
                  'attributes' => {
11529 
                    'group' => 4,
11530 
                    'isCe' => 1,
11531 
                    'period' => 1,
11532 
                  },
11533 
                  'direction' => 'in',
11534 
                  'hdlType' => 'std_logic',
11535 
                  'width' => 1,
11536 
                },
11537 
                'sysce_clr' => {
11538 
                  'attributes' => {
11539 
                    'group' => 4,
11540 
                    'isClr' => 1,
11541 
                    'period' => 1,
11542 
                  },
11543 
                  'direction' => 'in',
11544 
                  'hdlType' => 'std_logic',
11545 
                  'width' => 1,
11546 
                },
11547 
                'sysclk' => {
11548 
                  'attributes' => {
11549 
                    'group' => 4,
11550 
                    'isClk' => 1,
11551 
                    'period' => 1,
11552 
                  },
11553 
                  'direction' => 'in',
11554 
                  'hdlType' => 'std_logic',
11555 
                  'width' => 1,
11556 
                },
11557 
              },
11558 
            },
11559 
            'entityName' => 'default_clock_driver',
11560 
          },
11561 
          'inout_logic_x0' => {
11562 
            'connections' => {
11563 
              'data_in' => 'debug_in_2i_net_x0',
11564 
              'data_in_x0' => 'reg04_tv_net_x0',
11565 
              'data_in_x1' => 'reg04_td_net_x0',
11566 
              'data_in_x10' => 'debug_in_3i_net_x0',
11567 
              'data_in_x11' => 'debug_in_4i_net_x0',
11568 
              'data_in_x12' => 'reg09_tv_net_x0',
11569 
              'data_in_x13' => 'reg09_td_net_x0',
11570 
              'data_in_x14' => 'reg10_tv_net_x0',
11571 
              'data_in_x15' => 'reg10_td_net_x0',
11572 
              'data_in_x16' => 'reg08_tv_net_x0',
11573 
              'data_in_x17' => 'reg08_td_net_x0',
11574 
              'data_in_x18' => 'reg11_tv_net_x0',
11575 
              'data_in_x19' => 'reg11_td_net_x0',
11576 
              'data_in_x2' => 'reg05_tv_net_x0',
11577 
              'data_in_x20' => 'reg12_tv_net_x0',
11578 
              'data_in_x21' => 'reg01_tv_net_x0',
11579 
              'data_in_x22' => 'reg12_td_net_x0',
11580 
              'data_in_x23' => 'reg13_tv_net_x0',
11581 
              'data_in_x24' => 'reg13_td_net_x0',
11582 
              'data_in_x25' => 'reg14_tv_net_x0',
11583 
              'data_in_x26' => 'reg14_td_net_x0',
11584 
              'data_in_x27' => 'reg02_tv_net_x0',
11585 
              'data_in_x28' => 'reg02_td_net_x0',
11586 
              'data_in_x29' => 'debug_in_1i_net_x0',
11587 
              'data_in_x3' => 'reg05_td_net_x0',
11588 
              'data_in_x30' => 'reg01_td_net_x0',
11589 
              'data_in_x31' => 'reg03_tv_net_x0',
11590 
              'data_in_x32' => 'reg03_td_net_x0',
11591 
              'data_in_x4' => 'reg06_tv_net_x0',
11592 
              'data_in_x5' => 'reg06_td_net_x0',
11593 
              'data_in_x6' => 'reg07_tv_net_x0',
11594 
              'data_in_x7' => 'reg07_td_net_x0',
11595 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11596 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11597 
              'data_out' => 'from_register1_data_out_net',
11598 
              'data_out_x0' => 'from_register10_data_out_net',
11599 
              'data_out_x1' => 'from_register11_data_out_net',
11600 
              'data_out_x10' => 'from_register2_data_out_net',
11601 
              'data_out_x11' => 'from_register20_data_out_net',
11602 
              'data_out_x12' => 'from_register21_data_out_net',
11603 
              'data_out_x13' => 'from_register22_data_out_net',
11604 
              'data_out_x14' => 'from_register23_data_out_net',
11605 
              'data_out_x15' => 'from_register24_data_out_net',
11606 
              'data_out_x16' => 'from_register25_data_out_net',
11607 
              'data_out_x17' => 'from_register26_data_out_net',
11608 
              'data_out_x18' => 'from_register27_data_out_net',
11609 
              'data_out_x19' => 'from_register28_data_out_net',
11610 
              'data_out_x2' => 'from_register12_data_out_net',
11611 
              'data_out_x20' => 'from_register3_data_out_net',
11612 
              'data_out_x21' => 'from_register4_data_out_net',
11613 
              'data_out_x22' => 'from_register5_data_out_net',
11614 
              'data_out_x23' => 'from_register6_data_out_net',
11615 
              'data_out_x24' => 'from_register7_data_out_net',
11616 
              'data_out_x25' => 'from_register8_data_out_net',
11617 
              'data_out_x26' => 'from_register9_data_out_net',
11618 
              'data_out_x3' => 'from_register13_data_out_net',
11619 
              'data_out_x4' => 'from_register14_data_out_net',
11620 
              'data_out_x5' => 'from_register15_data_out_net',
11621 
              'data_out_x6' => 'from_register16_data_out_net',
11622 
              'data_out_x7' => 'from_register17_data_out_net',
11623 
              'data_out_x8' => 'from_register18_data_out_net',
11624 
              'data_out_x9' => 'from_register19_data_out_net',
11625 
              'debug_in_1i' => 'debug_in_1i_net',
11626 
              'debug_in_2i' => 'debug_in_2i_net',
11627 
              'debug_in_3i' => 'debug_in_3i_net',
11628 
              'debug_in_4i' => 'debug_in_4i_net',
11629 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11630 
              'dma_host2board_done' => 'dma_host2board_done_net',
11631 
              'en' => 'constant5_op_net_x0',
11632 
              'en_x0' => 'constant5_op_net_x1',
11633 
              'en_x1' => 'constant5_op_net_x2',
11634 
              'en_x10' => 'constant5_op_net_x11',
11635 
              'en_x11' => 'constant5_op_net_x12',
11636 
              'en_x12' => 'constant1_op_net_x0',
11637 
              'en_x13' => 'constant1_op_net_x1',
11638 
              'en_x14' => 'constant1_op_net_x2',
11639 
              'en_x15' => 'constant1_op_net_x3',
11640 
              'en_x16' => 'constant1_op_net_x4',
11641 
              'en_x17' => 'constant1_op_net_x5',
11642 
              'en_x18' => 'constant1_op_net_x6',
11643 
              'en_x19' => 'constant1_op_net_x7',
11644 
              'en_x2' => 'constant5_op_net_x3',
11645 
              'en_x20' => 'constant1_op_net_x8',
11646 
              'en_x21' => 'constant5_op_net_x13',
11647 
              'en_x22' => 'constant1_op_net_x9',
11648 
              'en_x23' => 'constant1_op_net_x10',
11649 
              'en_x24' => 'constant1_op_net_x11',
11650 
              'en_x25' => 'constant1_op_net_x12',
11651 
              'en_x26' => 'constant1_op_net_x13',
11652 
              'en_x27' => 'constant5_op_net_x14',
11653 
              'en_x28' => 'constant5_op_net_x15',
11654 
              'en_x29' => 'constant5_op_net_x16',
11655 
              'en_x3' => 'constant5_op_net_x4',
11656 
              'en_x30' => 'constant5_op_net_x17',
11657 
              'en_x31' => 'constant5_op_net_x18',
11658 
              'en_x32' => 'constant5_op_net_x19',
11659 
              'en_x4' => 'constant5_op_net_x5',
11660 
              'en_x5' => 'constant5_op_net_x6',
11661 
              'en_x6' => 'constant5_op_net_x7',
11662 
              'en_x7' => 'constant5_op_net_x8',
11663 
              'en_x8' => 'constant5_op_net_x9',
11664 
              'en_x9' => 'constant5_op_net_x10',
11665 
              'reg01_rd' => 'from_register3_data_out_net_x0',
11666 
              'reg01_rv' => 'from_register1_data_out_net_x0',
11667 
              'reg01_td' => 'reg01_td_net',
11668 
              'reg01_tv' => 'reg01_tv_net',
11669 
              'reg02_rd' => 'from_register5_data_out_net_x0',
11670 
              'reg02_rv' => 'from_register2_data_out_net_x0',
11671 
              'reg02_td' => 'reg02_td_net',
11672 
              'reg02_tv' => 'reg02_tv_net',
11673 
              'reg03_rd' => 'from_register7_data_out_net_x0',
11674 
              'reg03_rv' => 'from_register6_data_out_net_x0',
11675 
              'reg03_td' => 'reg03_td_net',
11676 
              'reg03_tv' => 'reg03_tv_net',
11677 
              'reg04_rd' => 'from_register8_data_out_net_x0',
11678 
              'reg04_rv' => 'from_register4_data_out_net_x0',
11679 
              'reg04_td' => 'reg04_td_net',
11680 
              'reg04_tv' => 'reg04_tv_net',
11681 
              'reg05_rd' => 'from_register10_data_out_net_x0',
11682 
              'reg05_rv' => 'from_register9_data_out_net_x0',
11683 
              'reg05_td' => 'reg05_td_net',
11684 
              'reg05_tv' => 'reg05_tv_net',
11685 
              'reg06_rd' => 'from_register11_data_out_net_x0',
11686 
              'reg06_rv' => 'from_register12_data_out_net_x0',
11687 
              'reg06_td' => 'reg06_td_net',
11688 
              'reg06_tv' => 'reg06_tv_net',
11689 
              'reg07_rd' => 'from_register13_data_out_net_x0',
11690 
              'reg07_rv' => 'from_register14_data_out_net_x0',
11691 
              'reg07_td' => 'reg07_td_net',
11692 
              'reg07_tv' => 'reg07_tv_net',
11693 
              'reg08_rd' => 'from_register15_data_out_net_x0',
11694 
              'reg08_rv' => 'from_register16_data_out_net_x0',
11695 
              'reg08_td' => 'reg08_td_net',
11696 
              'reg08_tv' => 'reg08_tv_net',
11697 
              'reg09_rd' => 'from_register17_data_out_net_x0',
11698 
              'reg09_rv' => 'from_register18_data_out_net_x0',
11699 
              'reg09_td' => 'reg09_td_net',
11700 
              'reg09_tv' => 'reg09_tv_net',
11701 
              'reg10_rd' => 'from_register19_data_out_net_x0',
11702 
              'reg10_rv' => 'from_register20_data_out_net_x0',
11703 
              'reg10_td' => 'reg10_td_net',
11704 
              'reg10_tv' => 'reg10_tv_net',
11705 
              'reg11_rd' => 'from_register21_data_out_net_x0',
11706 
              'reg11_rv' => 'from_register22_data_out_net_x0',
11707 
              'reg11_td' => 'reg11_td_net',
11708 
              'reg11_tv' => 'reg11_tv_net',
11709 
              'reg12_rd' => 'from_register23_data_out_net_x0',
11710 
              'reg12_rv' => 'from_register24_data_out_net_x0',
11711 
              'reg12_td' => 'reg12_td_net',
11712 
              'reg12_tv' => 'reg12_tv_net',
11713 
              'reg13_rd' => 'from_register25_data_out_net_x0',
11714 
              'reg13_rv' => 'from_register26_data_out_net_x0',
11715 
              'reg13_td' => 'reg13_td_net',
11716 
              'reg13_tv' => 'reg13_tv_net',
11717 
              'reg14_rd' => 'from_register27_data_out_net_x0',
11718 
              'reg14_rv' => 'from_register28_data_out_net_x0',
11719 
              'reg14_td' => 'reg14_td_net',
11720 
              'reg14_tv' => 'reg14_tv_net',
11721 
            },
11722 
            'entity' => {
11723 
              'attributes' => {
11724 
                'entityAlreadyNetlisted' => 1,
11725 
                'hdlKind' => 'vhdl',
11726 
                'isDesign' => 1,
11727 
                'simulinkName' => 'INOUT_LOGIC',
11728 
              },
11729 
              'entityName' => 'inout_logic',
11730 
              'ports' => {
11731 
                'data_in' => {
11732 
                  'attributes' => {
11733 
                    'bin_pt' => 0,
11734 
                    'is_floating_block' => 1,
11735 
                    'must_be_hdl_vector' => 1,
11736 
                    'period' => 1,
11737 
                    'port_id' => 0,
11738 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11739 
                    'type' => 'UFix_32_0',
11740 
                  },
11741 
                  'direction' => 'out',
11742 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11743 
                  'width' => 32,
11744 
                },
11745 
                'data_in_x0' => {
11746 
                  'attributes' => {
11747 
                    'bin_pt' => 0,
11748 
                    'is_floating_block' => 1,
11749 
                    'must_be_hdl_vector' => 1,
11750 
                    'period' => 1,
11751 
                    'port_id' => 0,
11752 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11753 
                    'type' => 'Bool',
11754 
                  },
11755 
                  'direction' => 'out',
11756 
                  'hdlType' => 'std_logic',
11757 
                  'width' => 1,
11758 
                },
11759 
                'data_in_x1' => {
11760 
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14196 
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14197 
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14198 
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14206 
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14211 
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14267 
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14272 
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}

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