URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [vcom.do] - Blame information for rev 13

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-- If you see error messages concerning missing libraries for
-- XilinxCoreLib, unisims, or simprims, you may not have set
-- up your ModelSim environment correctly.  See the Xilinx
-- Support Website for instructions telling how to compile
-- these libraries.
 
vlib work
 
vcom  -nowarn 1 inout_logic.vhd
vcom  -nowarn 1 inout_logic_cw.vhd

Line No.	Rev	Author	Line
1	13	barabba	`-- If you see error messages concerning missing libraries for`
2			`-- XilinxCoreLib, unisims, or simprims, you may not have set`
3			`-- up your ModelSim environment correctly. See the Xilinx`
4			`-- Support Website for instructions telling how to compile`
5			`-- these libraries.`
6
7			`vlib work`
8
9			`vcom -nowarn 1 inout_logic.vhd`
10			`vcom -nowarn 1 inout_logic_cw.vhd`

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [vcom.do] - Blame information for rev 13