URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 13

Details | Compare with Previous | View Log




"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 814: Assignment to from_register15_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 815: Assignment to from_register16_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 818: Assignment to from_register19_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 819: Assignment to from_register1_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 830: Assignment to from_register2_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 842: Assignment to from_register_data_out_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 844: Assignment to to_register10_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 845: Assignment to to_register11_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 846: Assignment to to_register12_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 847: Assignment to to_register13_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 848: Assignment to to_register14_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 849: Assignment to to_register15_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 850: Assignment to to_register16_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 851: Assignment to to_register17_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 852: Assignment to to_register18_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 853: Assignment to to_register19_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 854: Assignment to to_register1_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 855: Assignment to to_register20_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 856: Assignment to to_register21_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 857: Assignment to to_register22_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 858: Assignment to to_register23_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 859: Assignment to to_register24_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 860: Assignment to to_register25_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 861: Assignment to to_register26_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 862: Assignment to to_register27_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 863: Assignment to to_register2_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 864: Assignment to to_register3_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 865: Assignment to to_register4_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 866: Assignment to to_register5_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 867: Assignment to to_register6_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 868: Assignment to to_register7_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 869: Assignment to to_register8_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 870: Assignment to to_register9_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic_cw.vhd" Line 871: Assignment to to_register_dout_net ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1898: <fdre> remains a black-box since it has no binding entity.

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2345: Using initial value false for op_mem_22_20_front_din since it is never assigned

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 2351: Assignment to op_mem_22_20_back ignored, since the identifier is never used

 
"C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USER_LOGIC\synth_model\user_logic.vhd" Line 1909: <fdse> remains a black-box since it has no binding entity.

 
Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.

 
Input <from_register15_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <from_register16_data_out<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <from_register19_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <from_register1_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <from_register2_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <from_register_data_out<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register10_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register11_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register12_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register13_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register14_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register15_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register16_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register17_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register18_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register19_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register1_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register20_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register21_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register22_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register23_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register24_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register25_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register26_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register27_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register2_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register3_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register4_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register5_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register6_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register7_dout<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register8_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register9_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <to_register_dout<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <clr> of the instance <xlclockdriver> is unconnected or connected to loadless signal.

 
"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 378: Output port <ce_logic> of the instance <xlclockdriver> is unconnected or connected to loadless signal.

 
"c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_1_pcie_userlogic_00_user_logic/synth_model/user_logic_cw.vhd" line 254: Output port <o> of the instance <clr_reg> is unconnected or connected to loadless signal.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <en<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Input <up<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <load<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <din<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Input <clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.

 
Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

 
Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

 
Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

 
Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

 
Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1

 
Unit <user_logic>: instances <constant1>, <constant10> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant11> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant12> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant19> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant20> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant21> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant22> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant23> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant24> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant25> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant26> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant3> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant4> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant7> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant8> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant1>, <constant9> of unit <constant_963ed6358a> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant14>, <constant15> of unit <constant_6293007044> are equivalent, second instance is removed

 
Unit <user_logic>: instances <constant14>, <constant6> of unit <constant_6293007044> are equivalent, second instance is removed

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
Due to other FF/Latch trimming, FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.

 
No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.

 
No elements found for TNM 'D_CLK' on object 'user_logic_x0/chipscope/i_ila/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_GAND.U_CS_GAND_SRL/I_V6.U_CS_GAND_SRL_V6/I_USE_RPM_EQ0.U_GAND_SRL_SET/CLK_I'.

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[67].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[67].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[32].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[27].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[36].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[41].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[66].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[66].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[71].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[71].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[35].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[40].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[44].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[39].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[69].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[69].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[34].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[29].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 2 FFs/Latches : <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[38].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[43].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[52].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[47].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[12].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[42].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[37].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following 7 FFs/Latches : <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> <user_logic_x0/tx_en_in18/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[51].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[46].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[15].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[20].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[50].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[45].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[49].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[54].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[14].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[18].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[48].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[53].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[13].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[57].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[62].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in107/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in21/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[10].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[1].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[17].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[22].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in109/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in23/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[5].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[26].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[31].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[56].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[61].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[21].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[16].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[65].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[65].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[70].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[70].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[6].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[4].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[25].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[30].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[55].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[60].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in108/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in22/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[9].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[3].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[8].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[59].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[64].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[64].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[19].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[28].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[33].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[58].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in20/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in14/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[63].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in17/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in15/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[7].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in38/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[68].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in24/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[68].bit_is_0.fdre_comp> 

 
The FF/Latch <user_logic_x0/tx_en_in19/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> in Unit <user_logic_cw> is equivalent to the following FF/Latch : <user_logic_x0/tx_en_in11/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[11].bit_is_0.fdre_comp> 

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in3/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in51/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
FF/Latch <user_logic_x0/tx_en_in75/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <user_logic_cw>. This FF/Latch will be trimmed during the optimization process.

 
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

 

 
Browse

Tools

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 13
