OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [synopsis] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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  'attributes' => {
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    'HDLCodeGenStatus' => 0,
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    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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    },
470 
    'from_register17.data_out' => {
471 
      'hdlType' => 'std_logic_vector(31 downto 0)',
472 
      'width' => 32,
473 
    },
474 
    'from_register18.data_out' => {
475 
      'hdlType' => 'std_logic',
476 
      'width' => 1,
477 
    },
478 
    'from_register19.data_out' => {
479 
      'hdlType' => 'std_logic_vector(31 downto 0)',
480 
      'width' => 32,
481 
    },
482 
    'from_register2.data_out' => {
483 
      'hdlType' => 'std_logic_vector(31 downto 0)',
484 
      'width' => 32,
485 
    },
486 
    'from_register20.data_out' => {
487 
      'hdlType' => 'std_logic_vector(31 downto 0)',
488 
      'width' => 32,
489 
    },
490 
    'from_register21.data_out' => {
491 
      'hdlType' => 'std_logic',
492 
      'width' => 1,
493 
    },
494 
    'from_register22.data_out' => {
495 
      'hdlType' => 'std_logic_vector(31 downto 0)',
496 
      'width' => 32,
497 
    },
498 
    'from_register23.data_out' => {
499 
      'hdlType' => 'std_logic',
500 
      'width' => 1,
501 
    },
502 
    'from_register24.data_out' => {
503 
      'hdlType' => 'std_logic_vector(31 downto 0)',
504 
      'width' => 32,
505 
    },
506 
    'from_register25.data_out' => {
507 
      'hdlType' => 'std_logic',
508 
      'width' => 1,
509 
    },
510 
    'from_register26.data_out' => {
511 
      'hdlType' => 'std_logic_vector(31 downto 0)',
512 
      'width' => 32,
513 
    },
514 
    'from_register27.data_out' => {
515 
      'hdlType' => 'std_logic',
516 
      'width' => 1,
517 
    },
518 
    'from_register28.data_out' => {
519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
520 
      'width' => 32,
521 
    },
522 
    'from_register29.data_out' => {
523 
      'hdlType' => 'std_logic',
524 
      'width' => 1,
525 
    },
526 
    'from_register3.data_out' => {
527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
528 
      'width' => 32,
529 
    },
530 
    'from_register30.data_out' => {
531 
      'hdlType' => 'std_logic_vector(31 downto 0)',
532 
      'width' => 32,
533 
    },
534 
    'from_register31.data_out' => {
535 
      'hdlType' => 'std_logic',
536 
      'width' => 1,
537 
    },
538 
    'from_register32.data_out' => {
539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
540 
      'width' => 32,
541 
    },
542 
    'from_register33.data_out' => {
543 
      'hdlType' => 'std_logic',
544 
      'width' => 1,
545 
    },
546 
    'from_register4.data_out' => {
547 
      'hdlType' => 'std_logic',
548 
      'width' => 1,
549 
    },
550 
    'from_register5.data_out' => {
551 
      'hdlType' => 'std_logic_vector(31 downto 0)',
552 
      'width' => 32,
553 
    },
554 
    'from_register6.data_out' => {
555 
      'hdlType' => 'std_logic',
556 
      'width' => 1,
557 
    },
558 
    'from_register7.data_out' => {
559 
      'hdlType' => 'std_logic_vector(31 downto 0)',
560 
      'width' => 32,
561 
    },
562 
    'from_register8.data_out' => {
563 
      'hdlType' => 'std_logic',
564 
      'width' => 1,
565 
    },
566 
    'from_register9.data_out' => {
567 
      'hdlType' => 'std_logic_vector(31 downto 0)',
568 
      'width' => 32,
569 
    },
570 
    'sysgen_dut.bram_rd_addr' => {
571 
      'hdlType' => 'std_logic_vector(11 downto 0)',
572 
      'width' => 12,
573 
    },
574 
    'sysgen_dut.bram_wr_addr' => {
575 
      'hdlType' => 'std_logic_vector(11 downto 0)',
576 
      'width' => 12,
577 
    },
578 
    'sysgen_dut.bram_wr_din' => {
579 
      'hdlType' => 'std_logic_vector(63 downto 0)',
580 
      'width' => 64,
581 
    },
582 
    'sysgen_dut.bram_wr_en' => {
583 
      'hdlType' => 'std_logic_vector(7 downto 0)',
584 
      'width' => 8,
585 
    },
586 
    'sysgen_dut.fifo_rd_en' => {
587 
      'hdlType' => 'std_logic',
588 
      'width' => 1,
589 
    },
590 
    'sysgen_dut.fifo_wr_din' => {
591 
      'hdlType' => 'std_logic_vector(71 downto 0)',
592 
      'width' => 72,
593 
    },
594 
    'sysgen_dut.fifo_wr_en' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'sysgen_dut.rst_o' => {
599 
      'hdlType' => 'std_logic',
600 
      'width' => 1,
601 
    },
602 
    'sysgen_dut.to_register10_ce' => {
603 
      'hdlType' => 'std_logic',
604 
      'width' => 1,
605 
    },
606 
    'sysgen_dut.to_register10_clk' => {
607 
      'hdlType' => 'std_logic',
608 
      'width' => 1,
609 
    },
610 
    'sysgen_dut.to_register10_clr' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'sysgen_dut.to_register10_data_in' => {
615 
      'hdlType' => 'std_logic',
616 
      'width' => 1,
617 
    },
618 
    'sysgen_dut.to_register10_en' => {
619 
      'hdlType' => 'std_logic',
620 
      'width' => 1,
621 
    },
622 
    'sysgen_dut.to_register11_ce' => {
623 
      'hdlType' => 'std_logic',
624 
      'width' => 1,
625 
    },
626 
    'sysgen_dut.to_register11_clk' => {
627 
      'hdlType' => 'std_logic',
628 
      'width' => 1,
629 
    },
630 
    'sysgen_dut.to_register11_clr' => {
631 
      'hdlType' => 'std_logic',
632 
      'width' => 1,
633 
    },
634 
    'sysgen_dut.to_register11_data_in' => {
635 
      'hdlType' => 'std_logic',
636 
      'width' => 1,
637 
    },
638 
    'sysgen_dut.to_register11_en' => {
639 
      'hdlType' => 'std_logic',
640 
      'width' => 1,
641 
    },
642 
    'sysgen_dut.to_register12_ce' => {
643 
      'hdlType' => 'std_logic',
644 
      'width' => 1,
645 
    },
646 
    'sysgen_dut.to_register12_clk' => {
647 
      'hdlType' => 'std_logic',
648 
      'width' => 1,
649 
    },
650 
    'sysgen_dut.to_register12_clr' => {
651 
      'hdlType' => 'std_logic',
652 
      'width' => 1,
653 
    },
654 
    'sysgen_dut.to_register12_data_in' => {
655 
      'hdlType' => 'std_logic',
656 
      'width' => 1,
657 
    },
658 
    'sysgen_dut.to_register12_en' => {
659 
      'hdlType' => 'std_logic',
660 
      'width' => 1,
661 
    },
662 
    'sysgen_dut.to_register13_ce' => {
663 
      'hdlType' => 'std_logic',
664 
      'width' => 1,
665 
    },
666 
    'sysgen_dut.to_register13_clk' => {
667 
      'hdlType' => 'std_logic',
668 
      'width' => 1,
669 
    },
670 
    'sysgen_dut.to_register13_clr' => {
671 
      'hdlType' => 'std_logic',
672 
      'width' => 1,
673 
    },
674 
    'sysgen_dut.to_register13_data_in' => {
675 
      'hdlType' => 'std_logic_vector(31 downto 0)',
676 
      'width' => 32,
677 
    },
678 
    'sysgen_dut.to_register13_en' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'sysgen_dut.to_register14_ce' => {
683 
      'hdlType' => 'std_logic',
684 
      'width' => 1,
685 
    },
686 
    'sysgen_dut.to_register14_clk' => {
687 
      'hdlType' => 'std_logic',
688 
      'width' => 1,
689 
    },
690 
    'sysgen_dut.to_register14_clr' => {
691 
      'hdlType' => 'std_logic',
692 
      'width' => 1,
693 
    },
694 
    'sysgen_dut.to_register14_data_in' => {
695 
      'hdlType' => 'std_logic',
696 
      'width' => 1,
697 
    },
698 
    'sysgen_dut.to_register14_en' => {
699 
      'hdlType' => 'std_logic',
700 
      'width' => 1,
701 
    },
702 
    'sysgen_dut.to_register15_ce' => {
703 
      'hdlType' => 'std_logic',
704 
      'width' => 1,
705 
    },
706 
    'sysgen_dut.to_register15_clk' => {
707 
      'hdlType' => 'std_logic',
708 
      'width' => 1,
709 
    },
710 
    'sysgen_dut.to_register15_clr' => {
711 
      'hdlType' => 'std_logic',
712 
      'width' => 1,
713 
    },
714 
    'sysgen_dut.to_register15_data_in' => {
715 
      'hdlType' => 'std_logic_vector(31 downto 0)',
716 
      'width' => 32,
717 
    },
718 
    'sysgen_dut.to_register15_en' => {
719 
      'hdlType' => 'std_logic',
720 
      'width' => 1,
721 
    },
722 
    'sysgen_dut.to_register16_ce' => {
723 
      'hdlType' => 'std_logic',
724 
      'width' => 1,
725 
    },
726 
    'sysgen_dut.to_register16_clk' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'sysgen_dut.to_register16_clr' => {
731 
      'hdlType' => 'std_logic',
732 
      'width' => 1,
733 
    },
734 
    'sysgen_dut.to_register16_data_in' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'sysgen_dut.to_register16_en' => {
739 
      'hdlType' => 'std_logic',
740 
      'width' => 1,
741 
    },
742 
    'sysgen_dut.to_register17_ce' => {
743 
      'hdlType' => 'std_logic',
744 
      'width' => 1,
745 
    },
746 
    'sysgen_dut.to_register17_clk' => {
747 
      'hdlType' => 'std_logic',
748 
      'width' => 1,
749 
    },
750 
    'sysgen_dut.to_register17_clr' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'sysgen_dut.to_register17_data_in' => {
755 
      'hdlType' => 'std_logic_vector(31 downto 0)',
756 
      'width' => 32,
757 
    },
758 
    'sysgen_dut.to_register17_en' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'sysgen_dut.to_register18_ce' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'sysgen_dut.to_register18_clk' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'sysgen_dut.to_register18_clr' => {
771 
      'hdlType' => 'std_logic',
772 
      'width' => 1,
773 
    },
774 
    'sysgen_dut.to_register18_data_in' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'sysgen_dut.to_register18_en' => {
779 
      'hdlType' => 'std_logic',
780 
      'width' => 1,
781 
    },
782 
    'sysgen_dut.to_register19_ce' => {
783 
      'hdlType' => 'std_logic',
784 
      'width' => 1,
785 
    },
786 
    'sysgen_dut.to_register19_clk' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'sysgen_dut.to_register19_clr' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'sysgen_dut.to_register19_data_in' => {
795 
      'hdlType' => 'std_logic_vector(31 downto 0)',
796 
      'width' => 32,
797 
    },
798 
    'sysgen_dut.to_register19_en' => {
799 
      'hdlType' => 'std_logic',
800 
      'width' => 1,
801 
    },
802 
    'sysgen_dut.to_register1_ce' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'sysgen_dut.to_register1_clk' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'sysgen_dut.to_register1_clr' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'sysgen_dut.to_register1_data_in' => {
815 
      'hdlType' => 'std_logic',
816 
      'width' => 1,
817 
    },
818 
    'sysgen_dut.to_register1_en' => {
819 
      'hdlType' => 'std_logic',
820 
      'width' => 1,
821 
    },
822 
    'sysgen_dut.to_register20_ce' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'sysgen_dut.to_register20_clk' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'sysgen_dut.to_register20_clr' => {
831 
      'hdlType' => 'std_logic',
832 
      'width' => 1,
833 
    },
834 
    'sysgen_dut.to_register20_data_in' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'sysgen_dut.to_register20_en' => {
839 
      'hdlType' => 'std_logic',
840 
      'width' => 1,
841 
    },
842 
    'sysgen_dut.to_register21_ce' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'sysgen_dut.to_register21_clk' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'sysgen_dut.to_register21_clr' => {
851 
      'hdlType' => 'std_logic',
852 
      'width' => 1,
853 
    },
854 
    'sysgen_dut.to_register21_data_in' => {
855 
      'hdlType' => 'std_logic_vector(31 downto 0)',
856 
      'width' => 32,
857 
    },
858 
    'sysgen_dut.to_register21_en' => {
859 
      'hdlType' => 'std_logic',
860 
      'width' => 1,
861 
    },
862 
    'sysgen_dut.to_register22_ce' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'sysgen_dut.to_register22_clk' => {
867 
      'hdlType' => 'std_logic',
868 
      'width' => 1,
869 
    },
870 
    'sysgen_dut.to_register22_clr' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'sysgen_dut.to_register22_data_in' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'sysgen_dut.to_register22_en' => {
879 
      'hdlType' => 'std_logic',
880 
      'width' => 1,
881 
    },
882 
    'sysgen_dut.to_register23_ce' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'sysgen_dut.to_register23_clk' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'sysgen_dut.to_register23_clr' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'sysgen_dut.to_register23_data_in' => {
895 
      'hdlType' => 'std_logic_vector(31 downto 0)',
896 
      'width' => 32,
897 
    },
898 
    'sysgen_dut.to_register23_en' => {
899 
      'hdlType' => 'std_logic',
900 
      'width' => 1,
901 
    },
902 
    'sysgen_dut.to_register24_ce' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'sysgen_dut.to_register24_clk' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'sysgen_dut.to_register24_clr' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'sysgen_dut.to_register24_data_in' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
    'sysgen_dut.to_register24_en' => {
919 
      'hdlType' => 'std_logic',
920 
      'width' => 1,
921 
    },
922 
    'sysgen_dut.to_register25_ce' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'sysgen_dut.to_register25_clk' => {
927 
      'hdlType' => 'std_logic',
928 
      'width' => 1,
929 
    },
930 
    'sysgen_dut.to_register25_clr' => {
931 
      'hdlType' => 'std_logic',
932 
      'width' => 1,
933 
    },
934 
    'sysgen_dut.to_register25_data_in' => {
935 
      'hdlType' => 'std_logic_vector(31 downto 0)',
936 
      'width' => 32,
937 
    },
938 
    'sysgen_dut.to_register25_en' => {
939 
      'hdlType' => 'std_logic',
940 
      'width' => 1,
941 
    },
942 
    'sysgen_dut.to_register26_ce' => {
943 
      'hdlType' => 'std_logic',
944 
      'width' => 1,
945 
    },
946 
    'sysgen_dut.to_register26_clk' => {
947 
      'hdlType' => 'std_logic',
948 
      'width' => 1,
949 
    },
950 
    'sysgen_dut.to_register26_clr' => {
951 
      'hdlType' => 'std_logic',
952 
      'width' => 1,
953 
    },
954 
    'sysgen_dut.to_register26_data_in' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'sysgen_dut.to_register26_en' => {
959 
      'hdlType' => 'std_logic',
960 
      'width' => 1,
961 
    },
962 
    'sysgen_dut.to_register27_ce' => {
963 
      'hdlType' => 'std_logic',
964 
      'width' => 1,
965 
    },
966 
    'sysgen_dut.to_register27_clk' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'sysgen_dut.to_register27_clr' => {
971 
      'hdlType' => 'std_logic',
972 
      'width' => 1,
973 
    },
974 
    'sysgen_dut.to_register27_data_in' => {
975 
      'hdlType' => 'std_logic_vector(31 downto 0)',
976 
      'width' => 32,
977 
    },
978 
    'sysgen_dut.to_register27_en' => {
979 
      'hdlType' => 'std_logic',
980 
      'width' => 1,
981 
    },
982 
    'sysgen_dut.to_register2_ce' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'sysgen_dut.to_register2_clk' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'sysgen_dut.to_register2_clr' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'sysgen_dut.to_register2_data_in' => {
995 
      'hdlType' => 'std_logic_vector(31 downto 0)',
996 
      'width' => 32,
997 
    },
998 
    'sysgen_dut.to_register2_en' => {
999 
      'hdlType' => 'std_logic',
1000 
      'width' => 1,
1001 
    },
1002 
    'sysgen_dut.to_register3_ce' => {
1003 
      'hdlType' => 'std_logic',
1004 
      'width' => 1,
1005 
    },
1006 
    'sysgen_dut.to_register3_clk' => {
1007 
      'hdlType' => 'std_logic',
1008 
      'width' => 1,
1009 
    },
1010 
    'sysgen_dut.to_register3_clr' => {
1011 
      'hdlType' => 'std_logic',
1012 
      'width' => 1,
1013 
    },
1014 
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1015 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1016 
      'width' => 32,
1017 
    },
1018 
    'sysgen_dut.to_register3_en' => {
1019 
      'hdlType' => 'std_logic',
1020 
      'width' => 1,
1021 
    },
1022 
    'sysgen_dut.to_register4_ce' => {
1023 
      'hdlType' => 'std_logic',
1024 
      'width' => 1,
1025 
    },
1026 
    'sysgen_dut.to_register4_clk' => {
1027 
      'hdlType' => 'std_logic',
1028 
      'width' => 1,
1029 
    },
1030 
    'sysgen_dut.to_register4_clr' => {
1031 
      'hdlType' => 'std_logic',
1032 
      'width' => 1,
1033 
    },
1034 
    'sysgen_dut.to_register4_data_in' => {
1035 
      'hdlType' => 'std_logic',
1036 
      'width' => 1,
1037 
    },
1038 
    'sysgen_dut.to_register4_en' => {
1039 
      'hdlType' => 'std_logic',
1040 
      'width' => 1,
1041 
    },
1042 
    'sysgen_dut.to_register5_ce' => {
1043 
      'hdlType' => 'std_logic',
1044 
      'width' => 1,
1045 
    },
1046 
    'sysgen_dut.to_register5_clk' => {
1047 
      'hdlType' => 'std_logic',
1048 
      'width' => 1,
1049 
    },
1050 
    'sysgen_dut.to_register5_clr' => {
1051 
      'hdlType' => 'std_logic',
1052 
      'width' => 1,
1053 
    },
1054 
    'sysgen_dut.to_register5_data_in' => {
1055 
      'hdlType' => 'std_logic',
1056 
      'width' => 1,
1057 
    },
1058 
    'sysgen_dut.to_register5_en' => {
1059 
      'hdlType' => 'std_logic',
1060 
      'width' => 1,
1061 
    },
1062 
    'sysgen_dut.to_register6_ce' => {
1063 
      'hdlType' => 'std_logic',
1064 
      'width' => 1,
1065 
    },
1066 
    'sysgen_dut.to_register6_clk' => {
1067 
      'hdlType' => 'std_logic',
1068 
      'width' => 1,
1069 
    },
1070 
    'sysgen_dut.to_register6_clr' => {
1071 
      'hdlType' => 'std_logic',
1072 
      'width' => 1,
1073 
    },
1074 
    'sysgen_dut.to_register6_data_in' => {
1075 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1076 
      'width' => 32,
1077 
    },
1078 
    'sysgen_dut.to_register6_en' => {
1079 
      'hdlType' => 'std_logic',
1080 
      'width' => 1,
1081 
    },
1082 
    'sysgen_dut.to_register7_ce' => {
1083 
      'hdlType' => 'std_logic',
1084 
      'width' => 1,
1085 
    },
1086 
    'sysgen_dut.to_register7_clk' => {
1087 
      'hdlType' => 'std_logic',
1088 
      'width' => 1,
1089 
    },
1090 
    'sysgen_dut.to_register7_clr' => {
1091 
      'hdlType' => 'std_logic',
1092 
      'width' => 1,
1093 
    },
1094 
    'sysgen_dut.to_register7_data_in' => {
1095 
      'hdlType' => 'std_logic',
1096 
      'width' => 1,
1097 
    },
1098 
    'sysgen_dut.to_register7_en' => {
1099 
      'hdlType' => 'std_logic',
1100 
      'width' => 1,
1101 
    },
1102 
    'sysgen_dut.to_register8_ce' => {
1103 
      'hdlType' => 'std_logic',
1104 
      'width' => 1,
1105 
    },
1106 
    'sysgen_dut.to_register8_clk' => {
1107 
      'hdlType' => 'std_logic',
1108 
      'width' => 1,
1109 
    },
1110 
    'sysgen_dut.to_register8_clr' => {
1111 
      'hdlType' => 'std_logic',
1112 
      'width' => 1,
1113 
    },
1114 
    'sysgen_dut.to_register8_data_in' => {
1115 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1116 
      'width' => 32,
1117 
    },
1118 
    'sysgen_dut.to_register8_en' => {
1119 
      'hdlType' => 'std_logic',
1120 
      'width' => 1,
1121 
    },
1122 
    'sysgen_dut.to_register9_ce' => {
1123 
      'hdlType' => 'std_logic',
1124 
      'width' => 1,
1125 
    },
1126 
    'sysgen_dut.to_register9_clk' => {
1127 
      'hdlType' => 'std_logic',
1128 
      'width' => 1,
1129 
    },
1130 
    'sysgen_dut.to_register9_clr' => {
1131 
      'hdlType' => 'std_logic',
1132 
      'width' => 1,
1133 
    },
1134 
    'sysgen_dut.to_register9_data_in' => {
1135 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1136 
      'width' => 32,
1137 
    },
1138 
    'sysgen_dut.to_register9_en' => {
1139 
      'hdlType' => 'std_logic',
1140 
      'width' => 1,
1141 
    },
1142 
    'sysgen_dut.to_register_ce' => {
1143 
      'hdlType' => 'std_logic',
1144 
      'width' => 1,
1145 
    },
1146 
    'sysgen_dut.to_register_clk' => {
1147 
      'hdlType' => 'std_logic',
1148 
      'width' => 1,
1149 
    },
1150 
    'sysgen_dut.to_register_clr' => {
1151 
      'hdlType' => 'std_logic',
1152 
      'width' => 1,
1153 
    },
1154 
    'sysgen_dut.to_register_data_in' => {
1155 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1156 
      'width' => 32,
1157 
    },
1158 
    'sysgen_dut.to_register_en' => {
1159 
      'hdlType' => 'std_logic',
1160 
      'width' => 1,
1161 
    },
1162 
    'sysgen_dut.user_int_1o' => {
1163 
      'hdlType' => 'std_logic',
1164 
      'width' => 1,
1165 
    },
1166 
    'sysgen_dut.user_int_2o' => {
1167 
      'hdlType' => 'std_logic',
1168 
      'width' => 1,
1169 
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1170 
    'sysgen_dut.user_int_3o' => {
1171 
      'hdlType' => 'std_logic',
1172 
      'width' => 1,
1173 
    },
1174 
    'to_register.dout' => {
1175 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1176 
      'width' => 32,
1177 
    },
1178 
    'to_register1.dout' => {
1179 
      'hdlType' => 'std_logic',
1180 
      'width' => 1,
1181 
    },
1182 
    'to_register10.dout' => {
1183 
      'hdlType' => 'std_logic',
1184 
      'width' => 1,
1185 
    },
1186 
    'to_register11.dout' => {
1187 
      'hdlType' => 'std_logic',
1188 
      'width' => 1,
1189 
    },
1190 
    'to_register12.dout' => {
1191 
      'hdlType' => 'std_logic',
1192 
      'width' => 1,
1193 
    },
1194 
    'to_register13.dout' => {
1195 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1196 
      'width' => 32,
1197 
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1198 
    'to_register14.dout' => {
1199 
      'hdlType' => 'std_logic',
1200 
      'width' => 1,
1201 
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1202 
    'to_register15.dout' => {
1203 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1204 
      'width' => 32,
1205 
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1206 
    'to_register16.dout' => {
1207 
      'hdlType' => 'std_logic',
1208 
      'width' => 1,
1209 
    },
1210 
    'to_register17.dout' => {
1211 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1212 
      'width' => 32,
1213 
    },
1214 
    'to_register18.dout' => {
1215 
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1216 
      'width' => 1,
1217 
    },
1218 
    'to_register19.dout' => {
1219 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1220 
      'width' => 32,
1221 
    },
1222 
    'to_register2.dout' => {
1223 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1224 
      'width' => 32,
1225 
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1226 
    'to_register20.dout' => {
1227 
      'hdlType' => 'std_logic',
1228 
      'width' => 1,
1229 
    },
1230 
    'to_register21.dout' => {
1231 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1232 
      'width' => 32,
1233 
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1234 
    'to_register22.dout' => {
1235 
      'hdlType' => 'std_logic',
1236 
      'width' => 1,
1237 
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1238 
    'to_register23.dout' => {
1239 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1240 
      'width' => 32,
1241 
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1242 
    'to_register24.dout' => {
1243 
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1244 
      'width' => 1,
1245 
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1246 
    'to_register25.dout' => {
1247 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1248 
      'width' => 32,
1249 
    },
1250 
    'to_register26.dout' => {
1251 
      'hdlType' => 'std_logic',
1252 
      'width' => 1,
1253 
    },
1254 
    'to_register27.dout' => {
1255 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1256 
      'width' => 32,
1257 
    },
1258 
    'to_register3.dout' => {
1259 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1260 
      'width' => 32,
1261 
    },
1262 
    'to_register4.dout' => {
1263 
      'hdlType' => 'std_logic',
1264 
      'width' => 1,
1265 
    },
1266 
    'to_register5.dout' => {
1267 
      'hdlType' => 'std_logic',
1268 
      'width' => 1,
1269 
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1270 
    'to_register6.dout' => {
1271 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1272 
      'width' => 32,
1273 
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1274 
    'to_register7.dout' => {
1275 
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1276 
      'width' => 1,
1277 
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1278 
    'to_register8.dout' => {
1279 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1280 
      'width' => 32,
1281 
    },
1282 
    'to_register9.dout' => {
1283 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1284 
      'width' => 32,
1285 
    },
1286 
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1287 
  'subblocks' => {
1288 
    'bram_rd_addr' => {
1289 
      'connections' => {
1290 
        'bram_rd_addr' => 'sysgen_dut.bram_rd_addr',
1291 
      },
1292 
      'entity' => {
1293 
        'attributes' => {
1294 
          'entityAlreadyNetlisted' => 1,
1295 
          'isGateway' => 1,
1296 
          'is_floating_block' => 1,
1297 
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1298 
        'entityName' => 'bram_rd_addr',
1299 
        'ports' => {
1300 
          'bram_rd_addr' => {
1301 
            'attributes' => {
1302 
              'bin_pt' => 0,
1303 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
1304 
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1305 
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1306 
              'must_be_hdl_vector' => 1,
1307 
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1308 
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1309 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
1310 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
1311 
              'timingConstraint' => 'none',
1312 
              'type' => 'UFix_12_0',
1313 
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1314 
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1315 
            'hdlType' => 'std_logic_vector(11 downto 0)',
1316 
            'width' => 12,
1317 
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1318 
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1319 
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1320 
      'entityName' => 'bram_rd_addr',
1321 
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1322 
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1323 
      'connections' => {
1324 
        'bram_rd_dout' => '.bram_rd_dout',
1325 
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1326 
      'entity' => {
1327 
        'attributes' => {
1328 
          'entityAlreadyNetlisted' => 1,
1329 
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1330 
          'is_floating_block' => 1,
1331 
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1332 
        'entityName' => 'bram_rd_dout',
1333 
        'ports' => {
1334 
          'bram_rd_dout' => {
1335 
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1336 
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1337 
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1338 
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1339 
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1340 
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1341 
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1342 
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1343 
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1344 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout',
1345 
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1346 
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1347 
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1348 
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1349 
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1350 
            'width' => 64,
1351 
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1352 
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1353 
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1354 
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1355 
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1356 
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1357 
      'connections' => {
1358 
        'bram_wr_addr' => 'sysgen_dut.bram_wr_addr',
1359 
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1360 
      'entity' => {
1361 
        'attributes' => {
1362 
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1363 
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1364 
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1365 
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1366 
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1367 
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1368 
          'bram_wr_addr' => {
1369 
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1370 
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1371 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
1372 
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1373 
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1374 
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1375 
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1376 
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1377 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr/BRAM_wr_addr',
1378 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr',
1379 
              'timingConstraint' => 'none',
1380 
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1381 
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1382 
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1383 
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1384 
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1385 
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1386 
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1387 
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1388 
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1389 
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1390 
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1391 
      'connections' => {
1392 
        'bram_wr_din' => 'sysgen_dut.bram_wr_din',
1393 
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1394 
      'entity' => {
1395 
        'attributes' => {
1396 
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1397 
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1398 
          'is_floating_block' => 1,
1399 
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1400 
        'entityName' => 'bram_wr_din',
1401 
        'ports' => {
1402 
          'bram_wr_din' => {
1403 
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1404 
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1405 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
1406 
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1407 
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1408 
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1409 
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1410 
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1411 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din/BRAM_wr_din',
1412 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din',
1413 
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1414 
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1415 
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1416 
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1417 
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1418 
            'width' => 64,
1419 
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1420 
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1421 
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1422 
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1423 
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1424 
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1425 
      'connections' => {
1426 
        'bram_wr_en' => 'sysgen_dut.bram_wr_en',
1427 
      },
1428 
      'entity' => {
1429 
        'attributes' => {
1430 
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1431 
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1432 
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1433 
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1434 
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1435 
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1436 
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1437 
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1438 
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1439 
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1440 
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1441 
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1442 
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1443 
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1444 
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1445 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en/BRAM_wr_en',
1446 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en',
1447 
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1448 
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1449 
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1450 
            'direction' => 'in',
1451 
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1452 
            'width' => 8,
1453 
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1454 
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1455 
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1456 
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1457 
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1458 
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1459 
      'connections' => {
1460 
        'fifo_rd_count' => '.fifo_rd_count',
1461 
      },
1462 
      'entity' => {
1463 
        'attributes' => {
1464 
          'entityAlreadyNetlisted' => 1,
1465 
          'isGateway' => 1,
1466 
          'is_floating_block' => 1,
1467 
        },
1468 
        'entityName' => 'fifo_rd_count',
1469 
        'ports' => {
1470 
          'fifo_rd_count' => {
1471 
            'attributes' => {
1472 
              'bin_pt' => 0,
1473 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_count.dat',
1474 
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1475 
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1476 
              'must_be_hdl_vector' => 1,
1477 
              'period' => 1,
1478 
              'port_id' => 0,
1479 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count/FIFO_rd_count',
1480 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count',
1481 
              'timingConstraint' => 'none',
1482 
              'type' => 'UFix_15_0',
1483 
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1484 
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1485 
            'hdlType' => 'std_logic_vector(14 downto 0)',
1486 
            'width' => 15,
1487 
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1488 
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1489 
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1490 
      'entityName' => 'fifo_rd_count',
1491 
    },
1492 
    'fifo_rd_dout' => {
1493 
      'connections' => {
1494 
        'fifo_rd_dout' => '.fifo_rd_dout',
1495 
      },
1496 
      'entity' => {
1497 
        'attributes' => {
1498 
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1499 
          'isGateway' => 1,
1500 
          'is_floating_block' => 1,
1501 
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1502 
        'entityName' => 'fifo_rd_dout',
1503 
        'ports' => {
1504 
          'fifo_rd_dout' => {
1505 
            'attributes' => {
1506 
              'bin_pt' => 0,
1507 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_dout.dat',
1508 
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1509 
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1510 
              'must_be_hdl_vector' => 1,
1511 
              'period' => 1,
1512 
              'port_id' => 0,
1513 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout/FIFO_rd_dout',
1514 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout',
1515 
              'timingConstraint' => 'none',
1516 
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1517 
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1518 
            'direction' => 'out',
1519 
            'hdlType' => 'std_logic_vector(71 downto 0)',
1520 
            'width' => 72,
1521 
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1522 
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1523 
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        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
3908 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
3909 
        'to_register12_dout' => 'to_register12.dout',
3910 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
3911 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
3912 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
3913 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
3914 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
3915 
        'to_register13_dout' => 'to_register13.dout',
3916 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
3917 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
3918 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
3919 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
3920 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
3921 
        'to_register14_dout' => 'to_register14.dout',
3922 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
3923 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
3924 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
3925 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
3926 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
3927 
        'to_register15_dout' => 'to_register15.dout',
3928 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
3929 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
3930 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
3931 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
3932 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
3933 
        'to_register16_dout' => 'to_register16.dout',
3934 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
3935 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
3936 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
3937 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
3938 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
3939 
        'to_register17_dout' => 'to_register17.dout',
3940 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
3941 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
3942 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
3943 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
3944 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
3945 
        'to_register18_dout' => 'to_register18.dout',
3946 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
3947 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
3948 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
3949 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
3950 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
3951 
        'to_register19_dout' => 'to_register19.dout',
3952 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
3953 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
3954 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
3955 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
3956 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
3957 
        'to_register1_dout' => 'to_register1.dout',
3958 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
3959 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
3960 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
3961 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
3962 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
3963 
        'to_register20_dout' => 'to_register20.dout',
3964 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
3965 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
3966 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
3967 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
3968 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
3969 
        'to_register21_dout' => 'to_register21.dout',
3970 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
3971 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
3972 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
3973 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
3974 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
3975 
        'to_register22_dout' => 'to_register22.dout',
3976 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
3977 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
3978 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
3979 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
3980 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
3981 
        'to_register23_dout' => 'to_register23.dout',
3982 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
3983 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
3984 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
3985 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
3986 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
3987 
        'to_register24_dout' => 'to_register24.dout',
3988 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
3989 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
3990 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
3991 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
3992 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
3993 
        'to_register25_dout' => 'to_register25.dout',
3994 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
3995 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
3996 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
3997 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
3998 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
3999 
        'to_register26_dout' => 'to_register26.dout',
4000 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
4001 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
4002 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
4003 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
4004 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
4005 
        'to_register27_dout' => 'to_register27.dout',
4006 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
4007 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
4008 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
4009 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
4010 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
4011 
        'to_register2_dout' => 'to_register2.dout',
4012 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
4013 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
4014 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
4015 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
4016 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
4017 
        'to_register3_dout' => 'to_register3.dout',
4018 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
4019 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
4020 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
4021 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
4022 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
4023 
        'to_register4_dout' => 'to_register4.dout',
4024 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
4025 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
4026 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
4027 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
4028 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
4029 
        'to_register5_dout' => 'to_register5.dout',
4030 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
4031 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
4032 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
4033 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
4034 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
4035 
        'to_register6_dout' => 'to_register6.dout',
4036 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
4037 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
4038 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
4039 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
4040 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
4041 
        'to_register7_dout' => 'to_register7.dout',
4042 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
4043 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
4044 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
4045 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
4046 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
4047 
        'to_register8_dout' => 'to_register8.dout',
4048 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
4049 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
4050 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
4051 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
4052 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
4053 
        'to_register9_dout' => 'to_register9.dout',
4054 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
4055 
        'to_register_ce' => 'sysgen_dut.to_register_ce',
4056 
        'to_register_clk' => 'sysgen_dut.to_register_clk',
4057 
        'to_register_clr' => 'sysgen_dut.to_register_clr',
4058 
        'to_register_data_in' => 'sysgen_dut.to_register_data_in',
4059 
        'to_register_dout' => 'to_register.dout',
4060 
        'to_register_en' => 'sysgen_dut.to_register_en',
4061 
        'user_int_1o' => 'sysgen_dut.user_int_1o',
4062 
        'user_int_2o' => 'sysgen_dut.user_int_2o',
4063 
        'user_int_3o' => 'sysgen_dut.user_int_3o',
4064 
      },
4065 
      'entity' => {
4066 
        'attributes' => {
4067 
          'entityAlreadyNetlisted' => 1,
4068 
          'hdlArchAttributes' => [
4069 
          ],
4070 
          'hdlEntityAttributes' => [
4071 
          ],
4072 
          'isClkWrapper' => 1,
4073 
        },
4074 
        'connections' => {
4075 
          'bram_rd_addr' => 'bram_rd_addr_net',
4076 
          'bram_rd_dout' => 'bram_rd_dout_net',
4077 
          'bram_wr_addr' => 'bram_wr_addr_net',
4078 
          'bram_wr_din' => 'bram_wr_din_net',
4079 
          'bram_wr_en' => 'bram_wr_en_net',
4080 
          'clk' => 'clkNet',
4081 
          'fifo_rd_count' => 'fifo_rd_count_net',
4082 
          'fifo_rd_dout' => 'fifo_rd_dout_net',
4083 
          'fifo_rd_empty' => 'fifo_rd_empty_net',
4084 
          'fifo_rd_en' => 'fifo_rd_en_net',
4085 
          'fifo_rd_pempty' => 'fifo_rd_pempty_net',
4086 
          'fifo_rd_valid' => 'fifo_rd_valid_net',
4087 
          'fifo_wr_count' => 'fifo_wr_count_net',
4088 
          'fifo_wr_din' => 'fifo_wr_din_net',
4089 
          'fifo_wr_en' => 'fifo_wr_en_net',
4090 
          'fifo_wr_full' => 'fifo_wr_full_net',
4091 
          'fifo_wr_pfull' => 'fifo_wr_pfull_net',
4092 
          'from_register10_data_out' => 'data_out_x1_net',
4093 
          'from_register11_data_out' => 'data_out_x2_net',
4094 
          'from_register12_data_out' => 'data_out_x3_net',
4095 
          'from_register13_data_out' => 'data_out_x4_net',
4096 
          'from_register14_data_out' => 'data_out_x5_net',
4097 
          'from_register15_data_out' => 'from_register15_data_out_net',
4098 
          'from_register16_data_out' => 'from_register16_data_out_net',
4099 
          'from_register17_data_out' => 'data_out_x8_net',
4100 
          'from_register18_data_out' => 'data_out_x9_net',
4101 
          'from_register19_data_out' => 'from_register19_data_out_net',
4102 
          'from_register1_data_out' => 'from_register1_data_out_net',
4103 
          'from_register20_data_out' => 'data_out_x12_net',
4104 
          'from_register21_data_out' => 'data_out_x13_net',
4105 
          'from_register22_data_out' => 'data_out_x14_net',
4106 
          'from_register23_data_out' => 'data_out_x15_net',
4107 
          'from_register24_data_out' => 'data_out_x16_net',
4108 
          'from_register25_data_out' => 'data_out_x17_net',
4109 
          'from_register26_data_out' => 'data_out_x18_net',
4110 
          'from_register27_data_out' => 'data_out_x19_net',
4111 
          'from_register28_data_out' => 'data_out_x20_net',
4112 
          'from_register29_data_out' => 'data_out_x21_net',
4113 
          'from_register2_data_out' => 'from_register2_data_out_net',
4114 
          'from_register30_data_out' => 'data_out_x23_net',
4115 
          'from_register31_data_out' => 'data_out_x24_net',
4116 
          'from_register32_data_out' => 'data_out_x25_net',
4117 
          'from_register33_data_out' => 'data_out_x26_net',
4118 
          'from_register3_data_out' => 'data_out_x22_net',
4119 
          'from_register4_data_out' => 'data_out_x27_net',
4120 
          'from_register5_data_out' => 'data_out_x28_net',
4121 
          'from_register6_data_out' => 'data_out_x29_net',
4122 
          'from_register7_data_out' => 'data_out_x30_net',
4123 
          'from_register8_data_out' => 'data_out_x31_net',
4124 
          'from_register9_data_out' => 'data_out_x32_net',
4125 
          'from_register_data_out' => 'from_register_data_out_net',
4126 
          'rst_i' => 'rst_i_net',
4127 
          'rst_o' => 'rst_o_net',
4128 
          'to_register10_ce' => 'ce_1_sg_x0',
4129 
          'to_register10_clk' => 'clk_1_sg_x0',
4130 
          'to_register10_clr' => [
4131 
            'constant',
4132 
            '\'0\'',
4133 
          ],
4134 
          'to_register10_data_in' => 'data_in_x1_net',
4135 
          'to_register10_dout' => 'to_register10_dout_net',
4136 
          'to_register10_en' => 'constant6_op_net_x2',
4137 
          'to_register11_ce' => 'ce_1_sg_x0',
4138 
          'to_register11_clk' => 'clk_1_sg_x0',
4139 
          'to_register11_clr' => [
4140 
            'constant',
4141 
            '\'0\'',
4142 
          ],
4143 
          'to_register11_data_in' => 'data_in_x2_net',
4144 
          'to_register11_dout' => 'to_register11_dout_net',
4145 
          'to_register11_en' => 'constant6_op_net_x3',
4146 
          'to_register12_ce' => 'ce_1_sg_x0',
4147 
          'to_register12_clk' => 'clk_1_sg_x0',
4148 
          'to_register12_clr' => [
4149 
            'constant',
4150 
            '\'0\'',
4151 
          ],
4152 
          'to_register12_data_in' => 'data_in_x3_net',
4153 
          'to_register12_dout' => 'to_register12_dout_net',
4154 
          'to_register12_en' => 'constant6_op_net_x4',
4155 
          'to_register13_ce' => 'ce_1_sg_x0',
4156 
          'to_register13_clk' => 'clk_1_sg_x0',
4157 
          'to_register13_clr' => [
4158 
            'constant',
4159 
            '\'0\'',
4160 
          ],
4161 
          'to_register13_data_in' => 'data_in_x4_net',
4162 
          'to_register13_dout' => 'to_register13_dout_net',
4163 
          'to_register13_en' => 'constant6_op_net_x5',
4164 
          'to_register14_ce' => 'ce_1_sg_x0',
4165 
          'to_register14_clk' => 'clk_1_sg_x0',
4166 
          'to_register14_clr' => [
4167 
            'constant',
4168 
            '\'0\'',
4169 
          ],
4170 
          'to_register14_data_in' => 'data_in_x5_net',
4171 
          'to_register14_dout' => 'to_register14_dout_net',
4172 
          'to_register14_en' => 'constant6_op_net_x6',
4173 
          'to_register15_ce' => 'ce_1_sg_x0',
4174 
          'to_register15_clk' => 'clk_1_sg_x0',
4175 
          'to_register15_clr' => [
4176 
            'constant',
4177 
            '\'0\'',
4178 
          ],
4179 
          'to_register15_data_in' => 'data_in_x6_net',
4180 
          'to_register15_dout' => 'to_register15_dout_net',
4181 
          'to_register15_en' => 'constant6_op_net_x7',
4182 
          'to_register16_ce' => 'ce_1_sg_x0',
4183 
          'to_register16_clk' => 'clk_1_sg_x0',
4184 
          'to_register16_clr' => [
4185 
            'constant',
4186 
            '\'0\'',
4187 
          ],
4188 
          'to_register16_data_in' => 'data_in_x7_net',
4189 
          'to_register16_dout' => 'to_register16_dout_net',
4190 
          'to_register16_en' => 'constant6_op_net_x8',
4191 
          'to_register17_ce' => 'ce_1_sg_x0',
4192 
          'to_register17_clk' => 'clk_1_sg_x0',
4193 
          'to_register17_clr' => [
4194 
            'constant',
4195 
            '\'0\'',
4196 
          ],
4197 
          'to_register17_data_in' => 'data_in_x8_net',
4198 
          'to_register17_dout' => 'to_register17_dout_net',
4199 
          'to_register17_en' => 'constant6_op_net_x9',
4200 
          'to_register18_ce' => 'ce_1_sg_x0',
4201 
          'to_register18_clk' => 'clk_1_sg_x0',
4202 
          'to_register18_clr' => [
4203 
            'constant',
4204 
            '\'0\'',
4205 
          ],
4206 
          'to_register18_data_in' => 'data_in_x9_net',
4207 
          'to_register18_dout' => 'to_register18_dout_net',
4208 
          'to_register18_en' => 'constant6_op_net_x10',
4209 
          'to_register19_ce' => 'ce_1_sg_x0',
4210 
          'to_register19_clk' => 'clk_1_sg_x0',
4211 
          'to_register19_clr' => [
4212 
            'constant',
4213 
            '\'0\'',
4214 
          ],
4215 
          'to_register19_data_in' => 'data_in_x10_net',
4216 
          'to_register19_dout' => 'to_register19_dout_net',
4217 
          'to_register19_en' => 'constant6_op_net_x11',
4218 
          'to_register1_ce' => 'ce_1_sg_x0',
4219 
          'to_register1_clk' => 'clk_1_sg_x0',
4220 
          'to_register1_clr' => [
4221 
            'constant',
4222 
            '\'0\'',
4223 
          ],
4224 
          'to_register1_data_in' => 'data_in_x0_net',
4225 
          'to_register1_dout' => 'to_register1_dout_net',
4226 
          'to_register1_en' => 'constant6_op_net_x1',
4227 
          'to_register20_ce' => 'ce_1_sg_x0',
4228 
          'to_register20_clk' => 'clk_1_sg_x0',
4229 
          'to_register20_clr' => [
4230 
            'constant',
4231 
            '\'0\'',
4232 
          ],
4233 
          'to_register20_data_in' => 'data_in_x12_net',
4234 
          'to_register20_dout' => 'to_register20_dout_net',
4235 
          'to_register20_en' => 'constant6_op_net_x13',
4236 
          'to_register21_ce' => 'ce_1_sg_x0',
4237 
          'to_register21_clk' => 'clk_1_sg_x0',
4238 
          'to_register21_clr' => [
4239 
            'constant',
4240 
            '\'0\'',
4241 
          ],
4242 
          'to_register21_data_in' => 'data_in_x13_net',
4243 
          'to_register21_dout' => 'to_register21_dout_net',
4244 
          'to_register21_en' => 'constant6_op_net_x14',
4245 
          'to_register22_ce' => 'ce_1_sg_x0',
4246 
          'to_register22_clk' => 'clk_1_sg_x0',
4247 
          'to_register22_clr' => [
4248 
            'constant',
4249 
            '\'0\'',
4250 
          ],
4251 
          'to_register22_data_in' => 'data_in_x14_net',
4252 
          'to_register22_dout' => 'to_register22_dout_net',
4253 
          'to_register22_en' => 'constant6_op_net_x15',
4254 
          'to_register23_ce' => 'ce_1_sg_x0',
4255 
          'to_register23_clk' => 'clk_1_sg_x0',
4256 
          'to_register23_clr' => [
4257 
            'constant',
4258 
            '\'0\'',
4259 
          ],
4260 
          'to_register23_data_in' => 'data_in_x15_net',
4261 
          'to_register23_dout' => 'to_register23_dout_net',
4262 
          'to_register23_en' => 'constant6_op_net_x16',
4263 
          'to_register24_ce' => 'ce_1_sg_x0',
4264 
          'to_register24_clk' => 'clk_1_sg_x0',
4265 
          'to_register24_clr' => [
4266 
            'constant',
4267 
            '\'0\'',
4268 
          ],
4269 
          'to_register24_data_in' => 'data_in_x16_net',
4270 
          'to_register24_dout' => 'to_register24_dout_net',
4271 
          'to_register24_en' => 'constant6_op_net_x17',
4272 
          'to_register25_ce' => 'ce_1_sg_x0',
4273 
          'to_register25_clk' => 'clk_1_sg_x0',
4274 
          'to_register25_clr' => [
4275 
            'constant',
4276 
            '\'0\'',
4277 
          ],
4278 
          'to_register25_data_in' => 'data_in_x17_net',
4279 
          'to_register25_dout' => 'to_register25_dout_net',
4280 
          'to_register25_en' => 'constant6_op_net_x18',
4281 
          'to_register26_ce' => 'ce_1_sg_x0',
4282 
          'to_register26_clk' => 'clk_1_sg_x0',
4283 
          'to_register26_clr' => [
4284 
            'constant',
4285 
            '\'0\'',
4286 
          ],
4287 
          'to_register26_data_in' => 'data_in_x18_net',
4288 
          'to_register26_dout' => 'to_register26_dout_net',
4289 
          'to_register26_en' => 'constant6_op_net_x19',
4290 
          'to_register27_ce' => 'ce_1_sg_x0',
4291 
          'to_register27_clk' => 'clk_1_sg_x0',
4292 
          'to_register27_clr' => [
4293 
            'constant',
4294 
            '\'0\'',
4295 
          ],
4296 
          'to_register27_data_in' => 'data_in_x19_net',
4297 
          'to_register27_dout' => 'to_register27_dout_net',
4298 
          'to_register27_en' => 'constant6_op_net_x20',
4299 
          'to_register2_ce' => 'ce_1_sg_x0',
4300 
          'to_register2_clk' => 'clk_1_sg_x0',
4301 
          'to_register2_clr' => [
4302 
            'constant',
4303 
            '\'0\'',
4304 
          ],
4305 
          'to_register2_data_in' => 'data_in_x11_net',
4306 
          'to_register2_dout' => 'to_register2_dout_net',
4307 
          'to_register2_en' => 'constant6_op_net_x12',
4308 
          'to_register3_ce' => 'ce_1_sg_x0',
4309 
          'to_register3_clk' => 'clk_1_sg_x0',
4310 
          'to_register3_clr' => [
4311 
            'constant',
4312 
            '\'0\'',
4313 
          ],
4314 
          'to_register3_data_in' => 'data_in_x20_net',
4315 
          'to_register3_dout' => 'to_register3_dout_net',
4316 
          'to_register3_en' => 'constant6_op_net_x21',
4317 
          'to_register4_ce' => 'ce_1_sg_x0',
4318 
          'to_register4_clk' => 'clk_1_sg_x0',
4319 
          'to_register4_clr' => [
4320 
            'constant',
4321 
            '\'0\'',
4322 
          ],
4323 
          'to_register4_data_in' => 'data_in_x21_net',
4324 
          'to_register4_dout' => 'to_register4_dout_net',
4325 
          'to_register4_en' => 'constant6_op_net_x22',
4326 
          'to_register5_ce' => 'ce_1_sg_x0',
4327 
          'to_register5_clk' => 'clk_1_sg_x0',
4328 
          'to_register5_clr' => [
4329 
            'constant',
4330 
            '\'0\'',
4331 
          ],
4332 
          'to_register5_data_in' => 'data_in_x22_net',
4333 
          'to_register5_dout' => 'to_register5_dout_net',
4334 
          'to_register5_en' => 'constant6_op_net_x23',
4335 
          'to_register6_ce' => 'ce_1_sg_x0',
4336 
          'to_register6_clk' => 'clk_1_sg_x0',
4337 
          'to_register6_clr' => [
4338 
            'constant',
4339 
            '\'0\'',
4340 
          ],
4341 
          'to_register6_data_in' => 'data_in_x23_net',
4342 
          'to_register6_dout' => 'to_register6_dout_net',
4343 
          'to_register6_en' => 'constant6_op_net_x24',
4344 
          'to_register7_ce' => 'ce_1_sg_x0',
4345 
          'to_register7_clk' => 'clk_1_sg_x0',
4346 
          'to_register7_clr' => [
4347 
            'constant',
4348 
            '\'0\'',
4349 
          ],
4350 
          'to_register7_data_in' => 'data_in_x24_net',
4351 
          'to_register7_dout' => 'to_register7_dout_net',
4352 
          'to_register7_en' => 'constant6_op_net_x25',
4353 
          'to_register8_ce' => 'ce_1_sg_x0',
4354 
          'to_register8_clk' => 'clk_1_sg_x0',
4355 
          'to_register8_clr' => [
4356 
            'constant',
4357 
            '\'0\'',
4358 
          ],
4359 
          'to_register8_data_in' => 'data_in_x25_net',
4360 
          'to_register8_dout' => 'to_register8_dout_net',
4361 
          'to_register8_en' => 'constant6_op_net_x26',
4362 
          'to_register9_ce' => 'ce_1_sg_x0',
4363 
          'to_register9_clk' => 'clk_1_sg_x0',
4364 
          'to_register9_clr' => [
4365 
            'constant',
4366 
            '\'0\'',
4367 
          ],
4368 
          'to_register9_data_in' => 'data_in_x26_net',
4369 
          'to_register9_dout' => 'to_register9_dout_net',
4370 
          'to_register9_en' => 'constant6_op_net_x27',
4371 
          'to_register_ce' => 'ce_1_sg_x0',
4372 
          'to_register_clk' => 'clk_1_sg_x0',
4373 
          'to_register_clr' => [
4374 
            'constant',
4375 
            '\'0\'',
4376 
          ],
4377 
          'to_register_data_in' => 'data_in_net',
4378 
          'to_register_dout' => 'to_register_dout_net',
4379 
          'to_register_en' => 'constant6_op_net_x0',
4380 
          'user_int_1o' => 'user_int_1o_net',
4381 
          'user_int_2o' => 'user_int_2o_net',
4382 
          'user_int_3o' => 'user_int_3o_net',
4383 
        },
4384 
        'entityName' => 'user_logic_cw',
4385 
        'nets' => {
4386 
          'bram_rd_addr_net' => {
4387 
            'attributes' => {
4388 
              'hdlNetAttributes' => [
4389 
              ],
4390 
            },
4391 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4392 
            'width' => 12,
4393 
          },
4394 
          'bram_rd_dout_net' => {
4395 
            'attributes' => {
4396 
              'hdlNetAttributes' => [
4397 
              ],
4398 
            },
4399 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4400 
            'width' => 64,
4401 
          },
4402 
          'bram_wr_addr_net' => {
4403 
            'attributes' => {
4404 
              'hdlNetAttributes' => [
4405 
              ],
4406 
            },
4407 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4408 
            'width' => 12,
4409 
          },
4410 
          'bram_wr_din_net' => {
4411 
            'attributes' => {
4412 
              'hdlNetAttributes' => [
4413 
              ],
4414 
            },
4415 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4416 
            'width' => 64,
4417 
          },
4418 
          'bram_wr_en_net' => {
4419 
            'attributes' => {
4420 
              'hdlNetAttributes' => [
4421 
              ],
4422 
            },
4423 
            'hdlType' => 'std_logic_vector(7 downto 0)',
4424 
            'width' => 8,
4425 
          },
4426 
          'ce_1_sg_x0' => {
4427 
            'attributes' => {
4428 
              'hdlNetAttributes' => [
4429 
                [
4430 
                  'MAX_FANOUT',
4431 
                  'string',
4432 
                  '"REDUCE"',
4433 
                ],
4434 
              ],
4435 
            },
4436 
            'hdlType' => 'std_logic',
4437 
            'width' => 1,
4438 
          },
4439 
          'clkNet' => {
4440 
            'attributes' => {
4441 
              'hdlNetAttributes' => [
4442 
              ],
4443 
            },
4444 
            'hdlType' => 'std_logic',
4445 
            'width' => 1,
4446 
          },
4447 
          'clk_1_sg_x0' => {
4448 
            'attributes' => {
4449 
              'hdlNetAttributes' => [
4450 
              ],
4451 
            },
4452 
            'hdlType' => 'std_logic',
4453 
            'width' => 1,
4454 
          },
4455 
          'constant6_op_net_x0' => {
4456 
            'attributes' => {
4457 
              'hdlNetAttributes' => [
4458 
              ],
4459 
            },
4460 
            'hdlType' => 'std_logic',
4461 
            'width' => 1,
4462 
          },
4463 
          'constant6_op_net_x1' => {
4464 
            'attributes' => {
4465 
              'hdlNetAttributes' => [
4466 
              ],
4467 
            },
4468 
            'hdlType' => 'std_logic',
4469 
            'width' => 1,
4470 
          },
4471 
          'constant6_op_net_x10' => {
4472 
            'attributes' => {
4473 
              'hdlNetAttributes' => [
4474 
              ],
4475 
            },
4476 
            'hdlType' => 'std_logic',
4477 
            'width' => 1,
4478 
          },
4479 
          'constant6_op_net_x11' => {
4480 
            'attributes' => {
4481 
              'hdlNetAttributes' => [
4482 
              ],
4483 
            },
4484 
            'hdlType' => 'std_logic',
4485 
            'width' => 1,
4486 
          },
4487 
          'constant6_op_net_x12' => {
4488 
            'attributes' => {
4489 
              'hdlNetAttributes' => [
4490 
              ],
4491 
            },
4492 
            'hdlType' => 'std_logic',
4493 
            'width' => 1,
4494 
          },
4495 
          'constant6_op_net_x13' => {
4496 
            'attributes' => {
4497 
              'hdlNetAttributes' => [
4498 
              ],
4499 
            },
4500 
            'hdlType' => 'std_logic',
4501 
            'width' => 1,
4502 
          },
4503 
          'constant6_op_net_x14' => {
4504 
            'attributes' => {
4505 
              'hdlNetAttributes' => [
4506 
              ],
4507 
            },
4508 
            'hdlType' => 'std_logic',
4509 
            'width' => 1,
4510 
          },
4511 
          'constant6_op_net_x15' => {
4512 
            'attributes' => {
4513 
              'hdlNetAttributes' => [
4514 
              ],
4515 
            },
4516 
            'hdlType' => 'std_logic',
4517 
            'width' => 1,
4518 
          },
4519 
          'constant6_op_net_x16' => {
4520 
            'attributes' => {
4521 
              'hdlNetAttributes' => [
4522 
              ],
4523 
            },
4524 
            'hdlType' => 'std_logic',
4525 
            'width' => 1,
4526 
          },
4527 
          'constant6_op_net_x17' => {
4528 
            'attributes' => {
4529 
              'hdlNetAttributes' => [
4530 
              ],
4531 
            },
4532 
            'hdlType' => 'std_logic',
4533 
            'width' => 1,
4534 
          },
4535 
          'constant6_op_net_x18' => {
4536 
            'attributes' => {
4537 
              'hdlNetAttributes' => [
4538 
              ],
4539 
            },
4540 
            'hdlType' => 'std_logic',
4541 
            'width' => 1,
4542 
          },
4543 
          'constant6_op_net_x19' => {
4544 
            'attributes' => {
4545 
              'hdlNetAttributes' => [
4546 
              ],
4547 
            },
4548 
            'hdlType' => 'std_logic',
4549 
            'width' => 1,
4550 
          },
4551 
          'constant6_op_net_x2' => {
4552 
            'attributes' => {
4553 
              'hdlNetAttributes' => [
4554 
              ],
4555 
            },
4556 
            'hdlType' => 'std_logic',
4557 
            'width' => 1,
4558 
          },
4559 
          'constant6_op_net_x20' => {
4560 
            'attributes' => {
4561 
              'hdlNetAttributes' => [
4562 
              ],
4563 
            },
4564 
            'hdlType' => 'std_logic',
4565 
            'width' => 1,
4566 
          },
4567 
          'constant6_op_net_x21' => {
4568 
            'attributes' => {
4569 
              'hdlNetAttributes' => [
4570 
              ],
4571 
            },
4572 
            'hdlType' => 'std_logic',
4573 
            'width' => 1,
4574 
          },
4575 
          'constant6_op_net_x22' => {
4576 
            'attributes' => {
4577 
              'hdlNetAttributes' => [
4578 
              ],
4579 
            },
4580 
            'hdlType' => 'std_logic',
4581 
            'width' => 1,
4582 
          },
4583 
          'constant6_op_net_x23' => {
4584 
            'attributes' => {
4585 
              'hdlNetAttributes' => [
4586 
              ],
4587 
            },
4588 
            'hdlType' => 'std_logic',
4589 
            'width' => 1,
4590 
          },
4591 
          'constant6_op_net_x24' => {
4592 
            'attributes' => {
4593 
              'hdlNetAttributes' => [
4594 
              ],
4595 
            },
4596 
            'hdlType' => 'std_logic',
4597 
            'width' => 1,
4598 
          },
4599 
          'constant6_op_net_x25' => {
4600 
            'attributes' => {
4601 
              'hdlNetAttributes' => [
4602 
              ],
4603 
            },
4604 
            'hdlType' => 'std_logic',
4605 
            'width' => 1,
4606 
          },
4607 
          'constant6_op_net_x26' => {
4608 
            'attributes' => {
4609 
              'hdlNetAttributes' => [
4610 
              ],
4611 
            },
4612 
            'hdlType' => 'std_logic',
4613 
            'width' => 1,
4614 
          },
4615 
          'constant6_op_net_x27' => {
4616 
            'attributes' => {
4617 
              'hdlNetAttributes' => [
4618 
              ],
4619 
            },
4620 
            'hdlType' => 'std_logic',
4621 
            'width' => 1,
4622 
          },
4623 
          'constant6_op_net_x3' => {
4624 
            'attributes' => {
4625 
              'hdlNetAttributes' => [
4626 
              ],
4627 
            },
4628 
            'hdlType' => 'std_logic',
4629 
            'width' => 1,
4630 
          },
4631 
          'constant6_op_net_x4' => {
4632 
            'attributes' => {
4633 
              'hdlNetAttributes' => [
4634 
              ],
4635 
            },
4636 
            'hdlType' => 'std_logic',
4637 
            'width' => 1,
4638 
          },
4639 
          'constant6_op_net_x5' => {
4640 
            'attributes' => {
4641 
              'hdlNetAttributes' => [
4642 
              ],
4643 
            },
4644 
            'hdlType' => 'std_logic',
4645 
            'width' => 1,
4646 
          },
4647 
          'constant6_op_net_x6' => {
4648 
            'attributes' => {
4649 
              'hdlNetAttributes' => [
4650 
              ],
4651 
            },
4652 
            'hdlType' => 'std_logic',
4653 
            'width' => 1,
4654 
          },
4655 
          'constant6_op_net_x7' => {
4656 
            'attributes' => {
4657 
              'hdlNetAttributes' => [
4658 
              ],
4659 
            },
4660 
            'hdlType' => 'std_logic',
4661 
            'width' => 1,
4662 
          },
4663 
          'constant6_op_net_x8' => {
4664 
            'attributes' => {
4665 
              'hdlNetAttributes' => [
4666 
              ],
4667 
            },
4668 
            'hdlType' => 'std_logic',
4669 
            'width' => 1,
4670 
          },
4671 
          'constant6_op_net_x9' => {
4672 
            'attributes' => {
4673 
              'hdlNetAttributes' => [
4674 
              ],
4675 
            },
4676 
            'hdlType' => 'std_logic',
4677 
            'width' => 1,
4678 
          },
4679 
          'data_in_net' => {
4680 
            'attributes' => {
4681 
              'hdlNetAttributes' => [
4682 
              ],
4683 
            },
4684 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4685 
            'width' => 32,
4686 
          },
4687 
          'data_in_x0_net' => {
4688 
            'attributes' => {
4689 
              'hdlNetAttributes' => [
4690 
              ],
4691 
            },
4692 
            'hdlType' => 'std_logic',
4693 
            'width' => 1,
4694 
          },
4695 
          'data_in_x10_net' => {
4696 
            'attributes' => {
4697 
              'hdlNetAttributes' => [
4698 
              ],
4699 
            },
4700 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4701 
            'width' => 32,
4702 
          },
4703 
          'data_in_x11_net' => {
4704 
            'attributes' => {
4705 
              'hdlNetAttributes' => [
4706 
              ],
4707 
            },
4708 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4709 
            'width' => 32,
4710 
          },
4711 
          'data_in_x12_net' => {
4712 
            'attributes' => {
4713 
              'hdlNetAttributes' => [
4714 
              ],
4715 
            },
4716 
            'hdlType' => 'std_logic',
4717 
            'width' => 1,
4718 
          },
4719 
          'data_in_x13_net' => {
4720 
            'attributes' => {
4721 
              'hdlNetAttributes' => [
4722 
              ],
4723 
            },
4724 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4725 
            'width' => 32,
4726 
          },
4727 
          'data_in_x14_net' => {
4728 
            'attributes' => {
4729 
              'hdlNetAttributes' => [
4730 
              ],
4731 
            },
4732 
            'hdlType' => 'std_logic',
4733 
            'width' => 1,
4734 
          },
4735 
          'data_in_x15_net' => {
4736 
            'attributes' => {
4737 
              'hdlNetAttributes' => [
4738 
              ],
4739 
            },
4740 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4741 
            'width' => 32,
4742 
          },
4743 
          'data_in_x16_net' => {
4744 
            'attributes' => {
4745 
              'hdlNetAttributes' => [
4746 
              ],
4747 
            },
4748 
            'hdlType' => 'std_logic',
4749 
            'width' => 1,
4750 
          },
4751 
          'data_in_x17_net' => {
4752 
            'attributes' => {
4753 
              'hdlNetAttributes' => [
4754 
              ],
4755 
            },
4756 
            'hdlType' => 'std_logic_vector(31 downto 0)',
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5553 
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5554 
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5555 
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5561 
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5562 
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5563 
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5564 
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5565 
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5566 
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5567 
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5568 
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5570 
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5572 
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5579 
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5580 
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5581 
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5583 
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5589 
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5597 
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5598 
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5599 
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5600 
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5601 
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5606 
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5607 
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5608 
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5609 
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5610 
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5611 
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5612 
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5613 
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5614 
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5615 
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5616 
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5617 
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5618 
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5619 
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5620 
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5621 
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5622 
            'width' => 64,
5623 
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5624 
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5625 
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5626 
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5627 
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5628 
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5629 
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5630 
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5631 
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5632 
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5633 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en/BRAM_wr_en',
5634 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en',
5635 
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5636 
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5637 
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5638 
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5639 
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5640 
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5641 
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5642 
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5643 
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5644 
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5645 
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5646 
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5647 
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5648 
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5649 
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5650 
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5651 
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5652 
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5653 
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5654 
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5655 
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5656 
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5657 
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5658 
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5659 
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5660 
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5661 
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5662 
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5663 
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5664 
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5665 
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5666 
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5667 
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5668 
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5669 
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5675 
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5676 
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5677 
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5678 
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5679 
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5680 
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5685 
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5695 
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5696 
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5699 
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5700 
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5701 
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5702 
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5703 
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5705 
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5710 
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5711 
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5712 
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5713 
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5714 
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5715 
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5716 
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5717 
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5718 
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5719 
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5720 
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5721 
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5722 
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5723 
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5729 
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5730 
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5731 
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5732 
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5734 
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5736 
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5737 
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5738 
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5739 
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5740 
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5741 
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5747 
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5748 
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5749 
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5750 
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5751 
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5752 
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5754 
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5755 
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5756 
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5757 
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5758 
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5759 
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5765 
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5766 
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5767 
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5768 
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5769 
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5770 
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5771 
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5772 
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5773 
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5774 
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5775 
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5776 
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5777 
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5780 
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5783 
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5784 
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5785 
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5786 
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5787 
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5788 
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5789 
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5790 
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5791 
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5792 
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5793 
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5794 
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5795 
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5796 
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5799 
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5800 
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5801 
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5802 
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5803 
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5804 
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5805 
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5806 
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5807 
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5808 
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5809 
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5810 
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5811 
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5812 
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5813 
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5814 
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5815 
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5816 
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5817 
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5818 
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5819 
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5820 
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5821 
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5822 
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5823 
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5824 
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5825 
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5826 
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5827 
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5828 
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5829 
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5830 
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5831 
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5832 
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5833 
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5834 
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5835 
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5836 
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5837 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_full/FIFO_wr_full',
5838 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_wr_full',
5839 
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5840 
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5841 
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5842 
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5843 
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5844 
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5845 
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5846 
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5847 
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5848 
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5849 
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5850 
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5851 
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5854 
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5855 
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5856 
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5857 
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5858 
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5859 
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5860 
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5861 
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5862 
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5863 
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5864 
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5865 
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5866 
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5867 
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5868 
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5869 
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5870 
              'port_id' => 0,
5871 
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5872 
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5873 
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5874 
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5875 
            'hdlType' => 'std_logic_vector(0 downto 0)',
5876 
            'width' => 1,
5877 
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5878 
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5879 
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5880 
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5881 
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8000 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/en',
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8025 
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8027 
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8029 
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8030 
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8031 
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8044 
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8050 
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8052 
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            'hdlType' => 'std_logic',
8054 
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8056 
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8057 
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8058 
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/data_in',
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            'hdlType' => 'std_logic_vector(31 downto 0)',
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/dout',
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8080 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/en',
8092 
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8094 
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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8100 
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8112 
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8113 
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8119 
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            'hdlType' => 'std_logic',
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8125 
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8126 
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            'hdlType' => 'std_logic',
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/data_in',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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8154 
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/dout',
8160 
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/en',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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8182 
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8189 
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8208 
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8210 
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8211 
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8212 
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8213 
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8214 
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8215 
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8216 
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8217 
            'hdlType' => 'std_logic',
8218 
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8219 
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8220 
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8221 
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8222 
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8224 
              'must_be_hdl_vector' => 1,
8225 
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              'port_id' => 0,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/data_in',
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8230 
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            'hdlType' => 'std_logic_vector(0 downto 0)',
8232 
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              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/dout',
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/en',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
8260 
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8264 
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8280 
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8300 
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8317 
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8318 
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8330 
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8332 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/en',
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8340 
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8360 
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8364 
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8380 
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8399 
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8400 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/dout',
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8413 
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8414 
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8428 
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8429 
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8431 
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8435 
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8440 
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8445 
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8450 
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8452 
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8462 
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8464 
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8465 
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8466 
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8467 
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8468 
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8469 
              'is_floating_block' => 1,
8470 
              'must_be_hdl_vector' => 1,
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/data_in',
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8475 
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8477 
            'hdlType' => 'std_logic_vector(31 downto 0)',
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8480 
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              'must_be_hdl_vector' => 1,
8485 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/dout',
8488 
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8490 
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8494 
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8495 
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8496 
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              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/en',
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            'hdlType' => 'std_logic_vector(0 downto 0)',
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8508 
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8510 
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8511 
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8512 
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8513 
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8514 
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8515 
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8516 
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8517 
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8518 
            'hdlType' => 'std_logic',
8519 
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8520 
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8521 
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8522 
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8523 
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8524 
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8525 
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8526 
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8527 
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8528 
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8529 
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8530 
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8531 
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8532 
            'width' => 1,
8533 
          },
8534 
          'to_register9_clr' => {
8535 
            'attributes' => {
8536 
              'domain' => '',
8537 
              'group' => 1,
8538 
              'isClr' => 1,
8539 
              'is_floating_block' => 1,
8540 
              'period' => 1,
8541 
              'type' => 'logic',
8542 
              'valid_bit_used' => 0,
8543 
            },
8544 
            'direction' => 'out',
8545 
            'hdlType' => 'std_logic',
8546 
            'width' => 1,
8547 
          },
8548 
          'to_register9_data_in' => {
8549 
            'attributes' => {
8550 
              'bin_pt' => 0,
8551 
              'is_floating_block' => 1,
8552 
              'must_be_hdl_vector' => 1,
8553 
              'period' => 1,
8554 
              'port_id' => 0,
8555 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/data_in',
8556 
              'type' => 'UFix_32_0',
8557 
            },
8558 
            'direction' => 'out',
8559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8560 
            'width' => 32,
8561 
          },
8562 
          'to_register9_dout' => {
8563 
            'attributes' => {
8564 
              'bin_pt' => 0,
8565 
              'is_floating_block' => 1,
8566 
              'must_be_hdl_vector' => 1,
8567 
              'period' => 1,
8568 
              'port_id' => 0,
8569 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
8570 
              'type' => 'UFix_32_0',
8571 
            },
8572 
            'direction' => 'in',
8573 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8574 
            'width' => 32,
8575 
          },
8576 
          'to_register9_en' => {
8577 
            'attributes' => {
8578 
              'bin_pt' => 0,
8579 
              'is_floating_block' => 1,
8580 
              'must_be_hdl_vector' => 1,
8581 
              'period' => 1,
8582 
              'port_id' => 1,
8583 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
8584 
              'type' => 'Bool',
8585 
            },
8586 
            'direction' => 'out',
8587 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8588 
            'width' => 1,
8589 
          },
8590 
          'to_register_ce' => {
8591 
            'attributes' => {
8592 
              'domain' => '',
8593 
              'group' => 1,
8594 
              'isCe' => 1,
8595 
              'is_floating_block' => 1,
8596 
              'period' => 1,
8597 
              'type' => 'logic',
8598 
            },
8599 
            'direction' => 'out',
8600 
            'hdlType' => 'std_logic',
8601 
            'width' => 1,
8602 
          },
8603 
          'to_register_clk' => {
8604 
            'attributes' => {
8605 
              'domain' => '',
8606 
              'group' => 1,
8607 
              'isClk' => 1,
8608 
              'is_floating_block' => 1,
8609 
              'period' => 1,
8610 
              'type' => 'logic',
8611 
            },
8612 
            'direction' => 'out',
8613 
            'hdlType' => 'std_logic',
8614 
            'width' => 1,
8615 
          },
8616 
          'to_register_clr' => {
8617 
            'attributes' => {
8618 
              'domain' => '',
8619 
              'group' => 1,
8620 
              'isClr' => 1,
8621 
              'is_floating_block' => 1,
8622 
              'period' => 1,
8623 
              'type' => 'logic',
8624 
              'valid_bit_used' => 0,
8625 
            },
8626 
            'direction' => 'out',
8627 
            'hdlType' => 'std_logic',
8628 
            'width' => 1,
8629 
          },
8630 
          'to_register_data_in' => {
8631 
            'attributes' => {
8632 
              'bin_pt' => 0,
8633 
              'is_floating_block' => 1,
8634 
              'must_be_hdl_vector' => 1,
8635 
              'period' => 1,
8636 
              'port_id' => 0,
8637 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/data_in',
8638 
              'type' => 'UFix_32_0',
8639 
            },
8640 
            'direction' => 'out',
8641 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8642 
            'width' => 32,
8643 
          },
8644 
          'to_register_dout' => {
8645 
            'attributes' => {
8646 
              'bin_pt' => 0,
8647 
              'is_floating_block' => 1,
8648 
              'must_be_hdl_vector' => 1,
8649 
              'period' => 1,
8650 
              'port_id' => 0,
8651 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/dout',
8652 
              'type' => 'UFix_32_0',
8653 
            },
8654 
            'direction' => 'in',
8655 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8656 
            'width' => 32,
8657 
          },
8658 
          'to_register_en' => {
8659 
            'attributes' => {
8660 
              'bin_pt' => 0,
8661 
              'is_floating_block' => 1,
8662 
              'must_be_hdl_vector' => 1,
8663 
              'period' => 1,
8664 
              'port_id' => 1,
8665 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/en',
8666 
              'type' => 'Bool',
8667 
            },
8668 
            'direction' => 'out',
8669 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8670 
            'width' => 1,
8671 
          },
8672 
          'user_int_1o' => {
8673 
            'attributes' => {
8674 
              'bin_pt' => 0,
8675 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
8676 
              'is_floating_block' => 1,
8677 
              'is_gateway_port' => 1,
8678 
              'must_be_hdl_vector' => 1,
8679 
              'period' => 1,
8680 
              'port_id' => 0,
8681 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
8682 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
8683 
              'timingConstraint' => 'none',
8684 
              'type' => 'Bool',
8685 
            },
8686 
            'direction' => 'out',
8687 
            'hdlType' => 'std_logic',
8688 
            'width' => 1,
8689 
          },
8690 
          'user_int_2o' => {
8691 
            'attributes' => {
8692 
              'bin_pt' => 0,
8693 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
8694 
              'is_floating_block' => 1,
8695 
              'is_gateway_port' => 1,
8696 
              'must_be_hdl_vector' => 1,
8697 
              'period' => 1,
8698 
              'port_id' => 0,
8699 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
8700 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
8701 
              'timingConstraint' => 'none',
8702 
              'type' => 'Bool',
8703 
            },
8704 
            'direction' => 'out',
8705 
            'hdlType' => 'std_logic',
8706 
            'width' => 1,
8707 
          },
8708 
          'user_int_3o' => {
8709 
            'attributes' => {
8710 
              'bin_pt' => 0,
8711 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
8712 
              'is_floating_block' => 1,
8713 
              'is_gateway_port' => 1,
8714 
              'must_be_hdl_vector' => 1,
8715 
              'period' => 1,
8716 
              'port_id' => 0,
8717 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
8718 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
8719 
              'timingConstraint' => 'none',
8720 
              'type' => 'Bool',
8721 
            },
8722 
            'direction' => 'out',
8723 
            'hdlType' => 'std_logic',
8724 
            'width' => 1,
8725 
          },
8726 
        },
8727 
        'subblocks' => {
8728 
          'default_clock_driver_x0' => {
8729 
            'connections' => {
8730 
              'ce_1' => 'ce_1_sg_x0',
8731 
              'clk_1' => 'clk_1_sg_x0',
8732 
              'sysce' => [
8733 
                'constant',
8734 
                '\'1\'',
8735 
              ],
8736 
              'sysce_clr' => [
8737 
                'constant',
8738 
                '\'0\'',
8739 
              ],
8740 
              'sysclk' => 'clkNet',
8741 
            },
8742 
            'entity' => {
8743 
              'attributes' => {
8744 
                'domain' => 'default',
8745 
                'hdlArchAttributes' => [
8746 
                  [
8747 
                    'syn_noprune',
8748 
                    'boolean',
8749 
                    'true',
8750 
                  ],
8751 
                  [
8752 
                    'optimize_primitives',
8753 
                    'boolean',
8754 
                    'false',
8755 
                  ],
8756 
                  [
8757 
                    'dont_touch',
8758 
                    'boolean',
8759 
                    'true',
8760 
                  ],
8761 
                ],
8762 
                'hdlEntityAttributes' => [
8763 
                ],
8764 
                'isClkDriver' => 1,
8765 
              },
8766 
              'entityName' => 'default_clock_driver',
8767 
              'ports' => {
8768 
                'ce_1' => {
8769 
                  'attributes' => {
8770 
                    'domain' => 'default',
8771 
                    'group' => 1,
8772 
                    'isCe' => 1,
8773 
                    'period' => 1,
8774 
                    'type' => 'logic',
8775 
                  },
8776 
                  'direction' => 'out',
8777 
                  'hdlType' => 'std_logic',
8778 
                  'width' => 1,
8779 
                },
8780 
                'clk_1' => {
8781 
                  'attributes' => {
8782 
                    'domain' => 'default',
8783 
                    'group' => 1,
8784 
                    'isClk' => 1,
8785 
                    'period' => 1,
8786 
                    'type' => 'logic',
8787 
                  },
8788 
                  'direction' => 'out',
8789 
                  'hdlType' => 'std_logic',
8790 
                  'width' => 1,
8791 
                },
8792 
                'sysce' => {
8793 
                  'attributes' => {
8794 
                    'group' => 6,
8795 
                    'isCe' => 1,
8796 
                    'period' => 1,
8797 
                  },
8798 
                  'direction' => 'in',
8799 
                  'hdlType' => 'std_logic',
8800 
                  'width' => 1,
8801 
                },
8802 
                'sysce_clr' => {
8803 
                  'attributes' => {
8804 
                    'group' => 6,
8805 
                    'isClr' => 1,
8806 
                    'period' => 1,
8807 
                  },
8808 
                  'direction' => 'in',
8809 
                  'hdlType' => 'std_logic',
8810 
                  'width' => 1,
8811 
                },
8812 
                'sysclk' => {
8813 
                  'attributes' => {
8814 
                    'group' => 6,
8815 
                    'isClk' => 1,
8816 
                    'period' => 1,
8817 
                  },
8818 
                  'direction' => 'in',
8819 
                  'hdlType' => 'std_logic',
8820 
                  'width' => 1,
8821 
                },
8822 
              },
8823 
            },
8824 
            'entityName' => 'default_clock_driver',
8825 
          },
8826 
          'persistentdff_inst' => {
8827 
            'connections' => {
8828 
              'clk' => 'clkNet',
8829 
              'd' => 'persistentdff_inst_q',
8830 
              'q' => 'persistentdff_inst_q',
8831 
            },
8832 
            'entity' => {
8833 
              'attributes' => {
8834 
                'entityAlreadyNetlisted' => 1,
8835 
                'hdlCompAttributes' => [
8836 
                  [
8837 
                    'syn_black_box',
8838 
                    'boolean',
8839 
                    'true',
8840 
                  ],
8841 
                  [
8842 
                    'box_type',
8843 
                    'string',
8844 
                    '"black_box"',
8845 
                  ],
8846 
                ],
8847 
                'is_persistent_dff' => 1,
8848 
                'needsComponentDeclaration' => 1,
8849 
              },
8850 
              'entityName' => 'xlpersistentdff',
8851 
              'ports' => {
8852 
                'clk' => {
8853 
                  'direction' => 'in',
8854 
                  'hdlType' => 'std_logic',
8855 
                  'width' => 1,
8856 
                },
8857 
                'd' => {
8858 
                  'direction' => 'in',
8859 
                  'hdlType' => 'std_logic',
8860 
                  'width' => 1,
8861 
                },
8862 
                'q' => {
8863 
                  'direction' => 'out',
8864 
                  'hdlType' => 'std_logic',
8865 
                  'width' => 1,
8866 
                },
8867 
              },
8868 
            },
8869 
            'entityName' => 'xlpersistentdff',
8870 
          },
8871 
          'user_logic_x0' => {
8872 
            'connections' => {
8873 
              'bram_rd_addr' => 'bram_rd_addr_net',
8874 
              'bram_rd_dout' => 'bram_rd_dout_net',
8875 
              'bram_wr_addr' => 'bram_wr_addr_net',
8876 
              'bram_wr_din' => 'bram_wr_din_net',
8877 
              'bram_wr_en' => 'bram_wr_en_net',
8878 
              'ce_1' => 'ce_1_sg_x0',
8879 
              'clk_1' => 'clk_1_sg_x0',
8880 
              'data_in' => 'data_in_net',
8881 
              'data_in_x0' => 'data_in_x0_net',
8882 
              'data_in_x1' => 'data_in_x1_net',
8883 
              'data_in_x10' => 'data_in_x10_net',
8884 
              'data_in_x11' => 'data_in_x11_net',
8885 
              'data_in_x12' => 'data_in_x12_net',
8886 
              'data_in_x13' => 'data_in_x13_net',
8887 
              'data_in_x14' => 'data_in_x14_net',
8888 
              'data_in_x15' => 'data_in_x15_net',
8889 
              'data_in_x16' => 'data_in_x16_net',
8890 
              'data_in_x17' => 'data_in_x17_net',
8891 
              'data_in_x18' => 'data_in_x18_net',
8892 
              'data_in_x19' => 'data_in_x19_net',
8893 
              'data_in_x2' => 'data_in_x2_net',
8894 
              'data_in_x20' => 'data_in_x20_net',
8895 
              'data_in_x21' => 'data_in_x21_net',
8896 
              'data_in_x22' => 'data_in_x22_net',
8897 
              'data_in_x23' => 'data_in_x23_net',
8898 
              'data_in_x24' => 'data_in_x24_net',
8899 
              'data_in_x25' => 'data_in_x25_net',
8900 
              'data_in_x26' => 'data_in_x26_net',
8901 
              'data_in_x3' => 'data_in_x3_net',
8902 
              'data_in_x4' => 'data_in_x4_net',
8903 
              'data_in_x5' => 'data_in_x5_net',
8904 
              'data_in_x6' => 'data_in_x6_net',
8905 
              'data_in_x7' => 'data_in_x7_net',
8906 
              'data_in_x8' => 'data_in_x8_net',
8907 
              'data_in_x9' => 'data_in_x9_net',
8908 
              'data_out_x1' => 'data_out_x1_net',
8909 
              'data_out_x12' => 'data_out_x12_net',
8910 
              'data_out_x13' => 'data_out_x13_net',
8911 
              'data_out_x14' => 'data_out_x14_net',
8912 
              'data_out_x15' => 'data_out_x15_net',
8913 
              'data_out_x16' => 'data_out_x16_net',
8914 
              'data_out_x17' => 'data_out_x17_net',
8915 
              'data_out_x18' => 'data_out_x18_net',
8916 
              'data_out_x19' => 'data_out_x19_net',
8917 
              'data_out_x2' => 'data_out_x2_net',
8918 
              'data_out_x20' => 'data_out_x20_net',
8919 
              'data_out_x21' => 'data_out_x21_net',
8920 
              'data_out_x22' => 'data_out_x22_net',
8921 
              'data_out_x23' => 'data_out_x23_net',
8922 
              'data_out_x24' => 'data_out_x24_net',
8923 
              'data_out_x25' => 'data_out_x25_net',
8924 
              'data_out_x26' => 'data_out_x26_net',
8925 
              'data_out_x27' => 'data_out_x27_net',
8926 
              'data_out_x28' => 'data_out_x28_net',
8927 
              'data_out_x29' => 'data_out_x29_net',
8928 
              'data_out_x3' => 'data_out_x3_net',
8929 
              'data_out_x30' => 'data_out_x30_net',
8930 
              'data_out_x31' => 'data_out_x31_net',
8931 
              'data_out_x32' => 'data_out_x32_net',
8932 
              'data_out_x4' => 'data_out_x4_net',
8933 
              'data_out_x5' => 'data_out_x5_net',
8934 
              'data_out_x8' => 'data_out_x8_net',
8935 
              'data_out_x9' => 'data_out_x9_net',
8936 
              'en' => 'constant6_op_net_x0',
8937 
              'en_x0' => 'constant6_op_net_x1',
8938 
              'en_x1' => 'constant6_op_net_x2',
8939 
              'en_x10' => 'constant6_op_net_x11',
8940 
              'en_x11' => 'constant6_op_net_x12',
8941 
              'en_x12' => 'constant6_op_net_x13',
8942 
              'en_x13' => 'constant6_op_net_x14',
8943 
              'en_x14' => 'constant6_op_net_x15',
8944 
              'en_x15' => 'constant6_op_net_x16',
8945 
              'en_x16' => 'constant6_op_net_x17',
8946 
              'en_x17' => 'constant6_op_net_x18',
8947 
              'en_x18' => 'constant6_op_net_x19',
8948 
              'en_x19' => 'constant6_op_net_x20',
8949 
              'en_x2' => 'constant6_op_net_x3',
8950 
              'en_x20' => 'constant6_op_net_x21',
8951 
              'en_x21' => 'constant6_op_net_x22',
8952 
              'en_x22' => 'constant6_op_net_x23',
8953 
              'en_x23' => 'constant6_op_net_x24',
8954 
              'en_x24' => 'constant6_op_net_x25',
8955 
              'en_x25' => 'constant6_op_net_x26',
8956 
              'en_x26' => 'constant6_op_net_x27',
8957 
              'en_x3' => 'constant6_op_net_x4',
8958 
              'en_x4' => 'constant6_op_net_x5',
8959 
              'en_x5' => 'constant6_op_net_x6',
8960 
              'en_x6' => 'constant6_op_net_x7',
8961 
              'en_x7' => 'constant6_op_net_x8',
8962 
              'en_x8' => 'constant6_op_net_x9',
8963 
              'en_x9' => 'constant6_op_net_x10',
8964 
              'fifo_rd_count_x0' => 'fifo_rd_count_net',
8965 
              'fifo_rd_dout' => 'fifo_rd_dout_net',
8966 
              'fifo_rd_empty' => 'fifo_rd_empty_net',
8967 
              'fifo_rd_en_x1' => 'fifo_rd_en_net',
8968 
              'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
8969 
              'fifo_rd_valid' => 'fifo_rd_valid_net',
8970 
              'fifo_wr_count_x0' => 'fifo_wr_count_net',
8971 
              'fifo_wr_din' => 'fifo_wr_din_net',
8972 
              'fifo_wr_en_x0' => 'fifo_wr_en_net',
8973 
              'fifo_wr_full_x0' => 'fifo_wr_full_net',
8974 
              'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
8975 
              'rst_i' => 'rst_i_net',
8976 
              'rst_o' => 'rst_o_net',
8977 
              'user_int_1o' => 'user_int_1o_net',
8978 
              'user_int_2o' => 'user_int_2o_net',
8979 
              'user_int_3o' => 'user_int_3o_net',
8980 
            },
8981 
            'entity' => {
8982 
              'attributes' => {
8983 
                'entityAlreadyNetlisted' => 1,
8984 
                'hdlKind' => 'vhdl',
8985 
                'isDesign' => 1,
8986 
                'simulinkName' => 'USER_LOGIC',
8987 
              },
8988 
              'entityName' => 'user_logic',
8989 
              'ports' => {
8990 
                'bram_rd_addr' => {
8991 
                  'attributes' => {
8992 
                    'bin_pt' => 0,
8993 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
8994 
                    'is_floating_block' => 1,
8995 
                    'is_gateway_port' => 1,
8996 
                    'must_be_hdl_vector' => 1,
8997 
                    'period' => 1,
8998 
                    'port_id' => 15,
8999 
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
9000 
                    'source_block' => 'USER_LOGIC',
9001 
                    'timingConstraint' => 'none',
9002 
                    'type' => 'UFix_12_0',
9003 
                  },
9004 
                  'direction' => 'out',
9005 
                  'hdlType' => 'std_logic_vector(11 downto 0)',
9006 
                  'width' => 12,
9007 
                },
9008 
                'bram_rd_dout' => {
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14172 
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14173 
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14174 
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14175 
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14176 
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14177 
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14178 
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14179 
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14180 
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14181 
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14182 
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14183 
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14184 
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14185 
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14186 
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14187 
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14188 
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14189 
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14190 
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14191 
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14192 
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14193 
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14194 
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14195 
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14196 
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14197 
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14198 
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14199 
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14200 
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14201 
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14202 
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14203 
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14204 
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14205 
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14206 
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14207 
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14208 
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14209 
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14210 
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14211 
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14212 
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14213 
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14214 
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14215 
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14216 
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14217 
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14218 
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14219 
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14220 
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14221 
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14222 
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14223 
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14224 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14225 
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14226 
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14227 
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14228 
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14229 
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14230 
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14231 
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14232 
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14233 
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14234 
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14235 
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14236 
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14237 
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14238 
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14239 
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14240 
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14241 
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14242 
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14243 
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14244 
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14245 
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14246 
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14247 
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14248 
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14249 
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14250 
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14251 
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14252 
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14253 
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14254 
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14255 
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14256 
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14257 
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14258 
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14259 
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14260 
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14261 
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14262 
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14263 
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14264 
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14265 
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14266 
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14267 
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14268 
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14269 
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14270 
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14271 
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14272 
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14273 
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14274 
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14275 
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14276 
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14277 
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14278 
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14279 
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14280 
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14281 
        'user_int_2o' => 'sysgen_dut.user_int_2o',
14282 
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14283 
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14284 
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14285 
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14286 
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14287 
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14288 
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14289 
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14290 
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14291 
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14292 
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14293 
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14294 
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14295 
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14296 
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14297 
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14298 
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14299 
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14300 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
14301 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
14302 
              'timingConstraint' => 'none',
14303 
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14304 
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14305 
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14306 
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14307 
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14308 
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14309 
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14310 
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14311 
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14312 
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14313 
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14314 
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14315 
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14316 
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14317 
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14318 
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14319 
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14320 
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14321 
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14322 
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14323 
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14324 
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14325 
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14326 
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14327 
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14328 
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14329 
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14330 
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14331 
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14332 
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14333 
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14334 
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14335 
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14336 
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14337 
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14338 
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14339 
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14340 
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14341 
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14342 
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14343 
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14344 
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14345 
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14346 
    },
14347 
  },
14348 
}

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