OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [synth_model/] [user_logic_cw_complete.blc] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 barabba
Release 13.3 ngcbuild O.76xd (nt)
2
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
3
 
4
Command Line: c:\programmi\xilinx\13.3\ise_ds\ise\bin\nt\unwrapped\ngcbuild.exe
5
-p xc6vlx240t-1ff1156 user_logic_cw user_logic_cw_complete.ngc
6
 
7
Reading NGO file "C:/Temp/Xilinx PCI
8
Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USE
9
R_LOGIC/synth_model/user_logic_cw.ngc" ...
10
Loading design module "C:\Temp\Xilinx PCI
11
Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USE
12
R_LOGIC\synth_model/xlpersistentdff.ngc"...
13
Loading design module "C:\Temp\Xilinx PCI
14
Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USE
15
R_LOGIC\synth_model/ila_1_05_a_b6735eb4b876dee5.ngc"...
16
Loading design module "C:\Temp\Xilinx PCI
17
Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USE
18
R_LOGIC\synth_model/icon_1_06_a_87e2f476e984e565.ngc"...
19
Loading design module "C:\Temp\Xilinx PCI
20
Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_1_PCIe_UserLogic_00_USE
21
R_LOGIC\synth_model/cntr_11_0_341fbb8cfa0e669e.ngc"...
22
 
23
Applying constraints in "user_logic_cw.ucf" to the design...
24
WARNING:ConstraintSystem:191 - The TNM 'clk_5cc36873', does not directly or
25
   indirectly drive any flip-flops, latches and/or RAMS and cannot be actively
26
   used by the referencing Period constraint 'TS_clk_5cc36873'. If clock manager
27
   blocks are directly or indirectly driven, a new TNM constraint will not be
28
   derived even though the referencing constraint is a PERIOD constraint unless
29
   an output of the clock manager drives flip-flops, latches or RAMs. This TNM
30
   is used in the following user PERIOD specification:
31
   
32
   [user_logic_cw.ucf(5)]
33
 
34
WARNING:ConstraintSystem:197 - The following specification is invalid because
35
   the referenced TNM constraint was removed:
36
   
37
   [user_logic_cw.ucf(5)]
38
 
39
Checking Constraint Associations...
40
WARNING:NgdBuild:981 - Could not find any associations for the following
41
   constraint:
42
       ' [user_logic_cw.ucf(4)]'
43
 
44
Partition Implementation Status
45
-------------------------------
46
 
47
  No Partitions were found in this design.
48
 
49
-------------------------------
50
 
51
NGCBUILD Design Results Summary:
52
  Number of errors:     0
53
  Number of warnings:   3
54
 
55
Total memory usage is 105716 kilobytes
56
 
57
Writing NGC file "user_logic_cw_complete.ngc" ...
58
Total REAL time to NGCBUILD completion:  21 sec
59
Total CPU time to NGCBUILD completion:   5 sec
60
 
61
Writing NGCBUILD log file "user_logic_cw_complete.blc"...

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.