Subversion Repositories pcie_sg_dma

-------------------------------------------------------------------------------

-- Copyright (c) 2012 Xilinx, Inc.

-- All Rights Reserved

-------------------------------------------------------------------------------

--   ____  ____

--  /   /\/   /

-- /___/  \  /    Vendor     : Xilinx

-- \   \   \/     Version    : 13.3

--  \   \         Application: XILINX CORE Generator

--  /   /         Filename   : ila_1_05_a_b6735eb4b876dee5.vhd

-- /___/   /\     Timestamp  : Mon Mar 26 13:34:48 ora legale Europa occidentale 2012

-- \   \  /  \

--  \___\/\___\

--

-- Design Name: VHDL Synthesis Wrapper

-------------------------------------------------------------------------------

-- This wrapper is used to integrate with Project Navigator and PlanAhead

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ila_1_05_a_b6735eb4b876dee5 IS

  port (

    CONTROL: inout std_logic_vector(35 downto 0);

    CLK: in std_logic;

    TRIG0: in std_logic_vector(11 downto 0);

    TRIG1: in std_logic_vector(63 downto 0);

    TRIG2: in std_logic_vector(0 to 0);

    TRIG3: in std_logic_vector(0 to 0);

    TRIG4: in std_logic_vector(0 to 0);

    TRIG5: in std_logic_vector(71 downto 0);

    TRIG6: in std_logic_vector(0 to 0);

    TRIG7: in std_logic_vector(14 downto 0);

    TRIG8: in std_logic_vector(0 to 0);

    TRIG9: in std_logic_vector(0 to 0);

    TRIG10: in std_logic_vector(14 downto 0));

END ila_1_05_a_b6735eb4b876dee5;

ARCHITECTURE ila_1_05_a_b6735eb4b876dee5_a OF ila_1_05_a_b6735eb4b876dee5 IS

BEGIN

END ila_1_05_a_b6735eb4b876dee5_a;