OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [masterScript8386646885251483492.pl] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
 
2 
open(PIDFILE, '> pidfile.txt') || die 'Couldn\'t write process ID to file.';
3 
print PIDFILE "$$\n";
4 
close(PIDFILE);
5 
 
6 
eval {
7 
  # Call script(s).
8 
  my $instrs;
9 
  my $results = [];
10 
$ENV{'SYSGEN'} = 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen';
11 
  use Sg;
12 
  $instrs = {
13 
    'HDLCodeGenStatus' => 0.0,
14 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
15 
    'Impl_file' => 'ISE Defaults',
16 
    'Impl_file_sgadvanced' => '',
17 
    'Synth_file' => 'XST Defaults',
18 
    'Synth_file_sgadvanced' => '',
19 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
20 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
21 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
22 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
23 
    'base_system_period_hardware' => 5.0,
24 
    'base_system_period_simulink' => 5.0E-9,
25 
    'block_icon_display' => 'Default',
26 
    'block_type' => 'sysgen',
27 
    'block_version' => '',
28 
    'ce_clr' => 0.0,
29 
    'clock_loc' => '',
30 
    'clock_wrapper' => 'Clock Enables',
31 
    'clock_wrapper_sgadvanced' => '',
32 
    'compilation' => 'NGC Netlist',
33 
    'compilation_lut' => {
34 
      'keys' => [
35 
        'HDL Netlist',
36 
        'Bitstream',
37 
        'NGC Netlist',
38 
      ],
39 
      'values' => [
40 
        'target1',
41 
        'target2',
42 
        'target3',
43 
      ],
44 
    },
45 
    'compilation_target' => 'NGC Netlist',
46 
    'core_generation' => 1.0,
47 
    'core_generation_sgadvanced' => '',
48 
    'core_is_deployed' => 0.0,
49 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c1fefddc63a4b8747',
50 
    'coregen_part_family' => 'virtex6',
51 
    'createTestbench' => 0,
52 
    'create_interface_document' => 'off',
53 
    'dbl_ovrd' => -1.0,
54 
    'dbl_ovrd_sgadvanced' => '',
55 
    'dcm_input_clock_period' => 5.0,
56 
    'deprecated_control' => 'off',
57 
    'deprecated_control_sgadvanced' => '',
58 
    'design' => 'PCIe_UserLogic_00',
59 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
60 
    'device' => 'xc6vlx240t-1ff1156',
61 
    'device_speed' => '-1',
62 
    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
63 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
64 
    'eval_field' => '0',
65 
    'fileDeliveryDefaults' => [
66 
      [
67 
        '(?i)\\.vhd$',
68 
        { 'fileName' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/perl_results.vhd', },
69 
      ],
70 
      [
71 
        '(?i)\\.v$',
72 
        { 'fileName' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/perl_results.v', },
73 
      ],
74 
    ],
75 
    'fxdptinstalled' => 1.0,
76 
    'generateUsing71FrontEnd' => 1,
77 
    'generating_island_subsystem_handle' => 2341.00048828125,
78 
    'generating_subsystem_handle' => 2341.00048828125,
79 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
80 
    'has_advanced_control' => '0',
81 
    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
82 
    'hdlKind' => 'vhdl',
83 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
84 
    'impl_file' => 'ISE Defaults*',
85 
    'incr_netlist' => 'off',
86 
    'incr_netlist_sgadvanced' => '',
87 
    'infoedit' => ' System Generator',
88 
    'isdeployed' => 0,
89 
    'ise_version' => '13.3i',
90 
    'master_sysgen_token_handle' => 2342.00048828125,
91 
    'matlab' => 'C:/Programmi/MATLAB/R2010b',
92 
    'matlab_fixedpoint' => 1.0,
93 
    'mdlHandle' => 2083.00048828125,
94 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
95 
    'modelDiagnostics' => [
96 
      {
97 
        'count' => 351.0,
98 
        'isMask' => 0.0,
99 
        'type' => 'PCIe_UserLogic_00 Total blocks',
100 
      },
101 
      {
102 
        'count' => 4.0,
103 
        'isMask' => 0.0,
104 
        'type' => 'DiscretePulseGenerator',
105 
      },
106 
      {
107 
        'count' => 339.0,
108 
        'isMask' => 0.0,
109 
        'type' => 'S-Function',
110 
      },
111 
      {
112 
        'count' => 4.0,
113 
        'isMask' => 0.0,
114 
        'type' => 'SubSystem',
115 
      },
116 
      {
117 
        'count' => 4.0,
118 
        'isMask' => 0.0,
119 
        'type' => 'Terminator',
120 
      },
121 
      {
122 
        'count' => 1.0,
123 
        'isMask' => 1.0,
124 
        'type' => 'Xilinx ChipScope Block',
125 
      },
126 
      {
127 
        'count' => 23.0,
128 
        'isMask' => 1.0,
129 
        'type' => 'Xilinx Constant Block Block',
130 
      },
131 
      {
132 
        'count' => 1.0,
133 
        'isMask' => 1.0,
134 
        'type' => 'Xilinx Counter Block',
135 
      },
136 
      {
137 
        'count' => 44.0,
138 
        'isMask' => 1.0,
139 
        'type' => 'Xilinx Gateway In Block',
140 
      },
141 
      {
142 
        'count' => 39.0,
143 
        'isMask' => 1.0,
144 
        'type' => 'Xilinx Gateway Out Block',
145 
      },
146 
      {
147 
        'count' => 2.0,
148 
        'isMask' => 1.0,
149 
        'type' => 'Xilinx Inverter Block',
150 
      },
151 
      {
152 
        'count' => 1.0,
153 
        'isMask' => 1.0,
154 
        'type' => 'Xilinx Logical Block Block',
155 
      },
156 
      {
157 
        'count' => 89.0,
158 
        'isMask' => 1.0,
159 
        'type' => 'Xilinx Register Block',
160 
      },
161 
      {
162 
        'count' => 62.0,
163 
        'isMask' => 1.0,
164 
        'type' => 'Xilinx Shared Memory Based From Register Block',
165 
      },
166 
      {
167 
        'count' => 62.0,
168 
        'isMask' => 1.0,
169 
        'type' => 'Xilinx Shared Memory Based To Register Block',
170 
      },
171 
      {
172 
        'count' => 1.0,
173 
        'isMask' => 1.0,
174 
        'type' => 'Xilinx Subsystem Generator Block',
175 
      },
176 
      {
177 
        'count' => 2.0,
178 
        'isMask' => 1.0,
179 
        'type' => 'Xilinx System Generator Block',
180 
      },
181 
      {
182 
        'count' => 14.0,
183 
        'isMask' => 1.0,
184 
        'type' => 'Xilinx Type Converter Block',
185 
      },
186 
    ],
187 
    'model_globals_initialized' => 1.0,
188 
    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
189 
    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
190 
    'ngc_config' => {
191 
      'include_cf' => 1,
192 
      'include_clockwrapper' => 1.0,
193 
    },
194 
    'ngc_files' => [ 'xlpersistentdff.ngc', ],
195 
    'num_sim_cycles' => '2000000000',
196 
    'package' => 'ff1156',
197 
    'part' => 'xc6vlx240t',
198 
    'partFamily' => 'virtex6',
199 
    'port_data_types_enabled' => 1.0,
200 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
201 
    'preserve_hierarchy' => 0.0,
202 
    'proj_type' => 'Project Navigator',
203 
    'proj_type_sgadvanced' => '',
204 
    'run_coregen' => 'off',
205 
    'run_coregen_sgadvanced' => '',
206 
    'sample_time_colors_enabled' => 1.0,
207 
    'sampletimecolors' => 1.0,
208 
    'settings_fcn' => 'xlngcsettings',
209 
    'sg_blockgui_xml' => '',
210 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
211 
    'sg_list_contents' => '',
212 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
213 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
214 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
215 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
216 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
217 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
218 
fprintf(\'\',\'COMMENT: end icon graphics\');
219 
fprintf(\'\',\'COMMENT: begin icon text\');
220 
fprintf(\'\',\'COMMENT: end icon text\');',
221 
    'sg_version' => '',
222 
    'sggui_pos' => '-1,-1,-1,-1',
223 
    'simulation_island_subsystem_handle' => 2341.00048828125,
224 
    'simulink_accelerator_running' => 0.0,
225 
    'simulink_debugger_running' => 0.0,
226 
    'simulink_period' => 5.0E-9,
227 
    'speed' => '-1',
228 
    'synth_file' => 'XST Defaults*',
229 
    'synthesisTool' => 'XST',
230 
    'synthesis_language' => 'vhdl',
231 
    'synthesis_tool' => 'XST',
232 
    'synthesis_tool_sgadvanced' => '',
233 
    'sysclk_period' => 5.0,
234 
    'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
235 
    'sysgenRoot' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
236 
    'sysgenTokenSettings' => {
237 
      'Impl_file' => 'ISE Defaults',
238 
      'Impl_file_sgadvanced' => '',
239 
      'Synth_file' => 'XST Defaults',
240 
      'Synth_file_sgadvanced' => '',
241 
      'base_system_period_hardware' => 5.0,
242 
      'base_system_period_simulink' => 5.0E-9,
243 
      'block_icon_display' => 'Default',
244 
      'block_type' => 'sysgen',
245 
      'block_version' => '',
246 
      'ce_clr' => 0.0,
247 
      'clock_loc' => '',
248 
      'clock_wrapper' => 'Clock Enables',
249 
      'clock_wrapper_sgadvanced' => '',
250 
      'compilation' => 'NGC Netlist',
251 
      'compilation_lut' => {
252 
        'keys' => [
253 
          'HDL Netlist',
254 
          'Bitstream',
255 
          'NGC Netlist',
256 
        ],
257 
        'values' => [
258 
          'target1',
259 
          'target2',
260 
          'target3',
261 
        ],
262 
      },
263 
      'core_generation' => 1.0,
264 
      'core_generation_sgadvanced' => '',
265 
      'coregen_part_family' => 'virtex6',
266 
      'create_interface_document' => 'off',
267 
      'dbl_ovrd' => -1.0,
268 
      'dbl_ovrd_sgadvanced' => '',
269 
      'dcm_input_clock_period' => 5.0,
270 
      'deprecated_control' => 'off',
271 
      'deprecated_control_sgadvanced' => '',
272 
      'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC',
273 
      'eval_field' => '0',
274 
      'has_advanced_control' => '0',
275 
      'impl_file' => 'ISE Defaults*',
276 
      'incr_netlist' => 'off',
277 
      'incr_netlist_sgadvanced' => '',
278 
      'infoedit' => ' System Generator',
279 
      'master_sysgen_token_handle' => 2342.00048828125,
280 
      'ngc_config' => {
281 
        'include_cf' => 1,
282 
        'include_clockwrapper' => 1.0,
283 
      },
284 
      'package' => 'ff1156',
285 
      'part' => 'xc6vlx240t',
286 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
287 
      'preserve_hierarchy' => 0.0,
288 
      'proj_type' => 'Project Navigator',
289 
      'proj_type_sgadvanced' => '',
290 
      'run_coregen' => 'off',
291 
      'run_coregen_sgadvanced' => '',
292 
      'settings_fcn' => 'xlngcsettings',
293 
      'sg_blockgui_xml' => '',
294 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
295 
      'sg_list_contents' => '',
296 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
297 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
298 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
299 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
300 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
301 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
302 
fprintf(\'\',\'COMMENT: end icon graphics\');
303 
fprintf(\'\',\'COMMENT: begin icon text\');
304 
fprintf(\'\',\'COMMENT: end icon text\');',
305 
      'sggui_pos' => '-1,-1,-1,-1',
306 
      'simulation_island_subsystem_handle' => 2341.00048828125,
307 
      'simulink_period' => 5.0E-9,
308 
      'speed' => '-1',
309 
      'synth_file' => 'XST Defaults*',
310 
      'synthesis_language' => 'vhdl',
311 
      'synthesis_tool' => 'XST',
312 
      'synthesis_tool_sgadvanced' => '',
313 
      'sysclk_period' => 5.0,
314 
      'testbench' => 0,
315 
      'testbench_sgadvanced' => '',
316 
      'trim_vbits' => 1.0,
317 
      'trim_vbits_sgadvanced' => '',
318 
      'xilinx_device' => 'xc6vlx240t-1ff1156',
319 
      'xilinxfamily' => 'virtex6',
320 
    },
321 
    'sysgen_Root' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
322 
    'systemClockPeriod' => 5.0,
323 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
324 
    'testbench' => 0,
325 
    'testbench_sgadvanced' => '',
326 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen',
327 
    'trim_vbits' => 1.0,
328 
    'trim_vbits_sgadvanced' => '',
329 
    'use_ce_syn_keep' => 1,
330 
    'use_strict_names' => 1,
331 
    'user_tips_enabled' => 0.0,
332 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
333 
    'using71Netlister' => 1,
334 
    'verilog_files' => [
335 
      'conv_pkg.v',
336 
      'synth_reg.v',
337 
      'synth_reg_w_init.v',
338 
      'convert_type.v',
339 
    ],
340 
    'version' => '',
341 
    'vhdl_files' => [
342 
      'conv_pkg.vhd',
343 
      'synth_reg.vhd',
344 
      'synth_reg_w_init.vhd',
345 
    ],
346 
    'vsimtime' => '11000000275.000000 ns',
347 
    'xilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
348 
    'xilinx_device' => 'xc6vlx240t-1ff1156',
349 
    'xilinx_family' => 'virtex6',
350 
    'xilinx_package' => 'ff1156',
351 
    'xilinx_part' => 'xc6vlx240t',
352 
    'xilinxdevice' => 'xc6vlx240t-1ff1156',
353 
    'xilinxfamily' => 'virtex6',
354 
    'xilinxpart' => 'xc6vlx240t',
355 
  };
356 
  push(@$results, &Sg::setAttributes($instrs));
357 
  use SgDeliverFile;
358 
  $instrs = {
359 
    'collaborationName' => 'conv_pkg.vhd',
360 
    'sourceFile' => 'hdl/conv_pkg.vhd',
361 
    'templateKeyValues' => {},
362 
  };
363 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
364 
  $instrs = {
365 
    'collaborationName' => 'synth_reg.vhd',
366 
    'sourceFile' => 'hdl/synth_reg.vhd',
367 
    'templateKeyValues' => {},
368 
  };
369 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
370 
  $instrs = {
371 
    'collaborationName' => 'synth_reg_w_init.vhd',
372 
    'sourceFile' => 'hdl/synth_reg_w_init.vhd',
373 
    'templateKeyValues' => {},
374 
  };
375 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
376 
  $instrs = {
377 
    'collaborationName' => 'xlpersistentdff.ngc',
378 
    'sourceFile' => 'hdl/xlpersistentdff.ngc',
379 
    'templateKeyValues' => {},
380 
  };
381 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
382 
  $instrs = {
383 
    'entity_declaration_hash' => '26c90b101ce1ca8b2f28c242a8215ef7',
384 
    'sourceFile' => 'hdl/xlmcode.vhd',
385 
    'templateKeyValues' => {
386 
      'crippled_architecture' => 'is
387 
begin
388 
  op <= "0";
389 
end',
390 
      'crippled_entity' => 'is
391 
  port (
392 
    op : out std_logic_vector((1 - 1) downto 0);
393 
    clk : in std_logic;
394 
    ce : in std_logic;
395 
    clr : in std_logic);
396 
end',
397 
      'entity_name' => 'constant_963ed6358a',
398 
    },
399 
  };
400 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
401 
  $instrs = {
402 
    'entity_declaration_hash' => '13366d021ddc9f5413827bc05cb9e24f',
403 
    'sourceFile' => 'hdl/xlmcode.vhd',
404 
    'templateKeyValues' => {
405 
      'crippled_architecture' => 'is
406 
begin
407 
  op <= "1";
408 
end',
409 
      'crippled_entity' => 'is
410 
  port (
411 
    op : out std_logic_vector((1 - 1) downto 0);
412 
    clk : in std_logic;
413 
    ce : in std_logic;
414 
    clr : in std_logic);
415 
end',
416 
      'entity_name' => 'constant_6293007044',
417 
    },
418 
  };
419 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
420 
  $instrs = {
421 
    'entity_declaration_hash' => '2ba5044b83e42ac193c1ef05b1f91478',
422 
    'sourceFile' => 'hdl/xlmcode.vhd',
423 
    'templateKeyValues' => {
424 
      'crippled_architecture' => 'is
425 
begin
426 
  op <= "11111111";
427 
end',
428 
      'crippled_entity' => 'is
429 
  port (
430 
    op : out std_logic_vector((8 - 1) downto 0);
431 
    clk : in std_logic;
432 
    ce : in std_logic;
433 
    clr : in std_logic);
434 
end',
435 
      'entity_name' => 'constant_19562ab42f',
436 
    },
437 
  };
438 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
439 
  $instrs = {
440 
    'entity_declaration_hash' => 'a6f102369ca1079b35bf60e21fd122ee',
441 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlconvert.vhd',
442 
  };
443 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
444 
  use SgGenerateCores;
445 
  $instrs = [
446 
    'SELECT Binary_Counter virtex6 Xilinx,_Inc. 11.0',
447 
    '# 13.3_O.76xd',
448 
    '# DEVICE virtex6',
449 
    '# VHDL',
450 
    'CSET ainit_value = 0',
451 
    'CSET ce = true',
452 
    'CSET count_mode = UP',
453 
    'CSET fb_latency = 0',
454 
    'CSET final_count_value = 1',
455 
    'CSET implementation = Fabric',
456 
    'CSET increment_value = 1',
457 
    'CSET latency = 1',
458 
    'CSET load = false',
459 
    'CSET output_width = 12',
460 
    'CSET restrict_count = false',
461 
    'CSET sclr = false',
462 
    'CSET sinit = true',
463 
    'CSET sinit_value = 0',
464 
    'CSET sset = false',
465 
    'CSET sync_ce_priority = Sync_Overrides_CE',
466 
    'CSET sync_threshold_output = false',
467 
    'CSET syncctrlpriority = Reset_Overrides_Set',
468 
    'CSET component_name = cntr_11_0_341fbb8cfa0e669e',
469 
    'GENERATE',
470 
  ];
471 
  push(@$results, &SgGenerateCores::saveXcoSequence($instrs));
472 
  $instrs = {
473 
    'entity_declaration_hash' => '08fd4e9d602c64ca00cf3724579c5ab2',
474 
    'sourceFile' => 'hdl/xlcounter_free.vhd',
475 
    'templateKeyValues' => {
476 
      'core_component_def' => '      clk: in std_logic;
477 
      ce: in std_logic;
478 
      SINIT: in std_logic;
479 
      q: out std_logic_vector(op_width - 1 downto 0)',
480 
      'core_instance_text' => '        clk => clk,
481 
        ce => core_ce,
482 
        SINIT => core_sinit,
483 
        q => op_net',
484 
      'core_name0' => 'cntr_11_0_341fbb8cfa0e669e',
485 
      'entity_name.0' => 'xlcounter_free',
486 
      'needs_core' => 1,
487 
    },
488 
  };
489 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
490 
  $instrs = {
491 
    'entity_declaration_hash' => 'b32a0080f8f47e0be7ec44c6ad81b20b',
492 
    'sourceFile' => 'hdl/xlmcode.vhd',
493 
    'templateKeyValues' => {
494 
      'crippled_architecture' => 'is
495 
  signal ip_1_26: boolean;
496 
  type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
497 
  signal op_mem_22_20: array_type_op_mem_22_20 := (
498 
 
499 
  signal op_mem_22_20_front_din: boolean;
500 
  signal op_mem_22_20_back: boolean;
501 
  signal op_mem_22_20_push_front_pop_back_en: std_logic;
502 
  signal internal_ip_12_1_bitnot: boolean;
503 
begin
504 
  ip_1_26 <= ((ip) = "1");
505 
  op_mem_22_20_back <= op_mem_22_20(0);
506 
  proc_op_mem_22_20: process (clk)
507 
  is
508 
    variable i: integer;
509 
  begin
510 
    if (clk\'event and (clk = \'1\')) then
511 
      if ((ce = \'1\') and (op_mem_22_20_push_front_pop_back_en = \'1\')) then
512 
        op_mem_22_20(0) <= op_mem_22_20_front_din;
513 
      end if;
514 
    end if;
515 
  end process proc_op_mem_22_20;
516 
  internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
517 
  op_mem_22_20_push_front_pop_back_en <= \'0\';
518 
  op <= boolean_to_vector(internal_ip_12_1_bitnot);
519 
end',
520 
      'crippled_entity' => 'is
521 
  port (
522 
    ip : in std_logic_vector((1 - 1) downto 0);
523 
    op : out std_logic_vector((1 - 1) downto 0);
524 
    clk : in std_logic;
525 
    ce : in std_logic;
526 
    clr : in std_logic);
527 
end',
528 
      'entity_name' => 'inverter_e5b38cca3b',
529 
    },
530 
  };
531 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
532 
  $instrs = {
533 
    'entity_declaration_hash' => '298203483c3de52896eed04fd75246a4',
534 
    'sourceFile' => 'hdl/xlmcode.vhd',
535 
    'templateKeyValues' => {
536 
      'crippled_architecture' => 'is
537 
  signal d0_1_24: std_logic;
538 
  signal d1_1_27: std_logic;
539 
  signal fully_2_1_bit: std_logic;
540 
begin
541 
  d0_1_24 <= d0(0);
542 
  d1_1_27 <= d1(0);
543 
  fully_2_1_bit <= d0_1_24 and d1_1_27;
544 
  y <= std_logic_to_vector(fully_2_1_bit);
545 
end',
546 
      'crippled_entity' => 'is
547 
  port (
548 
    d0 : in std_logic_vector((1 - 1) downto 0);
549 
    d1 : in std_logic_vector((1 - 1) downto 0);
550 
    y : out std_logic_vector((1 - 1) downto 0);
551 
    clk : in std_logic;
552 
    ce : in std_logic;
553 
    clr : in std_logic);
554 
end',
555 
      'entity_name' => 'logical_80f90b97d0',
556 
    },
557 
  };
558 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
559 
  $instrs = {
560 
    'entity_declaration_hash' => 'e80fd0bc9c88351fdade399fbcd4158a',
561 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
562 
  };
563 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
564 
  $instrs = {
565 
    'entity_declaration_hash' => 'db5c30f0988e09973658bcb504101422',
566 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
567 
  };
568 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
569 
  $instrs = {
570 
    'entity_declaration_hash' => 'bf46b70cf2b90b05e5d3f1fb7bea16d9',
571 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
572 
  };
573 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
574 
  $instrs = {
575 
    'entity_declaration_hash' => 'be6f6c8a945a933a2801f0f4f7eba8ac',
576 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
577 
  };
578 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
579 
  $instrs = {
580 
    'entity_declaration_hash' => 'a522509641ca31da2ffb263fa3ca3c87',
581 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
582 
  };
583 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
584 
  $instrs = {
585 
    'entity_declaration_hash' => 'd5c981faf95794d3e3724fc7b1e657fe',
586 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
587 
  };
588 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
589 
  $instrs = {
590 
    'entity_declaration_hash' => 'e34f4091d55c2665d04daba7f7e96ab0',
591 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
592 
  };
593 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
594 
  $instrs = {
595 
    'entity_declaration_hash' => '1240425cba9ad7bd6399a70b90c219be',
596 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
597 
  };
598 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
599 
  $instrs = {
600 
    'entity_declaration_hash' => '1f061d40968f6bff078a4caa5f0072a3',
601 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
602 
  };
603 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
604 
  $instrs = {
605 
    'entity_declaration_hash' => 'b3210728de1a2642633da953faa71e3a',
606 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
607 
  };
608 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
609 
  $instrs = [
610 
    'SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) virtex6 Xilinx,_Inc. 1.06.a',
611 
    '# 13.3_O.76xd',
612 
    '# DEVICE virtex6',
613 
    '# VHDL',
614 
    'CSET enable_jtag_bufg = false',
615 
    'CSET example_design = false',
616 
    'CSET number_control_ports = 1',
617 
    'CSET use_ext_bscan = false',
618 
    'CSET use_softbscan = false',
619 
    'CSET use_unused_bscan = false',
620 
    'CSET user_scan_chain = USER1',
621 
    'CSET component_name = icon_1_06_a_87e2f476e984e565',
622 
    'GENERATE',
623 
  ];
624 
  push(@$results, &SgGenerateCores::saveXcoSequence($instrs));
625 
  $instrs = [
626 
    'SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) virtex6 Xilinx,_Inc. 1.05.a',
627 
    '# 13.3_O.76xd',
628 
    '# DEVICE virtex6',
629 
    '# VHDL',
630 
    'CSET data_same_as_trigger = true',
631 
    'CSET enable_storage_qualification = true',
632 
    'CSET example_design = false',
633 
    'CSET match_type_1 = basic',
634 
    'CSET match_type_10 = basic',
635 
    'CSET match_type_11 = basic',
636 
    'CSET match_type_2 = basic',
637 
    'CSET match_type_3 = basic',
638 
    'CSET match_type_4 = basic',
639 
    'CSET match_type_5 = basic',
640 
    'CSET match_type_6 = basic',
641 
    'CSET match_type_7 = basic',
642 
    'CSET match_type_8 = basic',
643 
    'CSET match_type_9 = basic',
644 
    'CSET match_units_1 = 1',
645 
    'CSET match_units_10 = 1',
646 
    'CSET match_units_11 = 1',
647 
    'CSET match_units_2 = 1',
648 
    'CSET match_units_3 = 1',
649 
    'CSET match_units_4 = 1',
650 
    'CSET match_units_5 = 1',
651 
    'CSET match_units_6 = 1',
652 
    'CSET match_units_7 = 1',
653 
    'CSET match_units_8 = 1',
654 
    'CSET match_units_9 = 1',
655 
    'CSET number_of_trigger_ports = 11',
656 
    'CSET sample_data_depth = 1024',
657 
    'CSET trigger_port_width_1 = 12',
658 
    'CSET trigger_port_width_10 = 1',
659 
    'CSET trigger_port_width_11 = 15',
660 
    'CSET trigger_port_width_2 = 64',
661 
    'CSET trigger_port_width_3 = 1',
662 
    'CSET trigger_port_width_4 = 1',
663 
    'CSET trigger_port_width_5 = 1',
664 
    'CSET trigger_port_width_6 = 72',
665 
    'CSET trigger_port_width_7 = 1',
666 
    'CSET trigger_port_width_8 = 15',
667 
    'CSET trigger_port_width_9 = 1',
668 
    'CSET use_rpms = false',
669 
    'CSET component_name = ila_1_05_a_b6735eb4b876dee5',
670 
    'GENERATE',
671 
  ];
672 
  push(@$results, &SgGenerateCores::saveXcoSequence($instrs));
673 
  $instrs = {
674 
    'sourceFile' => 'hdl/xlchipscope.vhd',
675 
    'templateKeyValues' => {
676 
      'c_data_width' => '184',
677 
      'data_is_trigger' => '1',
678 
      'data_port_declaration' => '',
679 
      'data_port_info' => '',
680 
      'data_port_interface' => '',
681 
      'entity_name' => 'xlchipscope',
682 
      'icon_core_name' => 'icon_1_06_a_87e2f476e984e565',
683 
      'ila_core_name' => 'ila_1_05_a_b6735eb4b876dee5',
684 
      'num_data_ports' => '0',
685 
      'num_trig_ports' => '11',
686 
      'trig_port_declaration' => 'input[11:0] trig0;
687 
input[63:0] trig1;
688 
input[0:0] trig2;
689 
input[0:0] trig3;
690 
input[0:0] trig4;
691 
input[71:0] trig5;
692 
input[0:0] trig6;
693 
input[14:0] trig7;
694 
input[0:0] trig8;
695 
input[0:0] trig9;
696 
input[14:0] trig10;
697 
',
698 
      'trig_port_info' => '     trig0 : in std_logic_vector(12-1 downto 0);
699 
        trig1 : in std_logic_vector(64-1 downto 0);
700 
        trig2 : in std_logic_vector(1-1 downto 0);
701 
        trig3 : in std_logic_vector(1-1 downto 0);
702 
        trig4 : in std_logic_vector(1-1 downto 0);
703 
        trig5 : in std_logic_vector(72-1 downto 0);
704 
        trig6 : in std_logic_vector(1-1 downto 0);
705 
        trig7 : in std_logic_vector(15-1 downto 0);
706 
        trig8 : in std_logic_vector(1-1 downto 0);
707 
        trig9 : in std_logic_vector(1-1 downto 0);
708 
        trig10 : in std_logic_vector(15-1 downto 0);
709 
',
710 
      'trig_port_interface' => ' trig0, trig1, trig2, trig3, trig4, trig5, trig6, trig7, trig8, trig9, trig10,',
711 
    },
712 
  };
713 
  push(@$results, &SgDeliverFile::deliverFile($instrs));
714 
  $instrs = {
715 
    'entity_declaration_hash' => 'a46098a678eecf32c50564a76d264038',
716 
    'sourceFile' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl/xlregister.vhd',
717 
  };
718 
  push(@$results, &SgDeliverFile::saveCollaborationInfo($instrs));
719 
  local *wrapup = $Sg::{'wrapup'};
720 
  push(@$results, &Sg::wrapup())   if (defined(&wrapup));
721 
  local *wrapup = $SgDeliverFile::{'wrapup'};
722 
  push(@$results, &SgDeliverFile::wrapup())   if (defined(&wrapup));
723 
  local *wrapup = $SgGenerateCores::{'wrapup'};
724 
  push(@$results, &SgGenerateCores::wrapup())   if (defined(&wrapup));
725 
  use Carp qw(croak);
726 
  $ENV{'SYSGEN'} = 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen';
727 
  open(RESULTS, '> C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521') ||
728 
    croak 'couldn\'t open C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521';
729 
  binmode(RESULTS);
730 
  print RESULTS &Sg::toString($results) . "\n";
731 
  close(RESULTS) ||
732 
    croak 'trouble writing C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521';
733 
};
734 
 
735 
if ($@) {
736 
  open(RESULTS, '> C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521') ||
737 
    croak 'couldn\'t open C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521';
738 
  binmode(RESULTS);
739 
  print RESULTS $@ . "\n";
740 
  close(RESULTS) ||
741 
    croak 'trouble writing C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_1_PCIe_UserLogic_00_USER_LOGIC/sysgen/script_results9023964121776289521';
742 
  exit(1);
743 
}
744 
 
745 
exit(0);

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