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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [nonleaf_results.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
library IEEE;
2 
use IEEE.std_logic_1164.all;
3 
use work.conv_pkg.all;
4 
 
5 
-- Generated from Simulink block "USER_LOGIC"
6 
 
7 
entity user_logic is
8 
  port (
9 
    bram_rd_dout: in std_logic_vector(63 downto 0);
10 
    ce_1: in std_logic;
11 
    clk_1: in std_logic;
12 
    data_out_x1: in std_logic;
13 
    data_out_x12: in std_logic_vector(31 downto 0);
14 
    data_out_x13: in std_logic;
15 
    data_out_x14: in std_logic_vector(31 downto 0);
16 
    data_out_x15: in std_logic;
17 
    data_out_x16: in std_logic_vector(31 downto 0);
18 
    data_out_x17: in std_logic;
19 
    data_out_x18: in std_logic_vector(31 downto 0);
20 
    data_out_x19: in std_logic;
21 
    data_out_x2: in std_logic_vector(31 downto 0);
22 
    data_out_x20: in std_logic_vector(31 downto 0);
23 
    data_out_x21: in std_logic;
24 
    data_out_x22: in std_logic_vector(31 downto 0);
25 
    data_out_x23: in std_logic_vector(31 downto 0);
26 
    data_out_x24: in std_logic;
27 
    data_out_x25: in std_logic_vector(31 downto 0);
28 
    data_out_x26: in std_logic;
29 
    data_out_x27: in std_logic;
30 
    data_out_x28: in std_logic_vector(31 downto 0);
31 
    data_out_x29: in std_logic;
32 
    data_out_x3: in std_logic;
33 
    data_out_x30: in std_logic_vector(31 downto 0);
34 
    data_out_x31: in std_logic;
35 
    data_out_x32: in std_logic_vector(31 downto 0);
36 
    data_out_x4: in std_logic_vector(31 downto 0);
37 
    data_out_x5: in std_logic;
38 
    data_out_x8: in std_logic_vector(31 downto 0);
39 
    data_out_x9: in std_logic;
40 
    fifo_rd_count_x0: in std_logic_vector(14 downto 0);
41 
    fifo_rd_dout: in std_logic_vector(71 downto 0);
42 
    fifo_rd_empty: in std_logic;
43 
    fifo_rd_pempty_x0: in std_logic;
44 
    fifo_rd_valid: in std_logic;
45 
    fifo_wr_count_x0: in std_logic_vector(14 downto 0);
46 
    fifo_wr_full_x0: in std_logic;
47 
    fifo_wr_pfull_x0: in std_logic;
48 
    rst_i: in std_logic;
49 
    bram_rd_addr: out std_logic_vector(11 downto 0);
50 
    bram_wr_addr: out std_logic_vector(11 downto 0);
51 
    bram_wr_din: out std_logic_vector(63 downto 0);
52 
    bram_wr_en: out std_logic_vector(7 downto 0);
53 
    data_in: out std_logic_vector(31 downto 0);
54 
    data_in_x0: out std_logic;
55 
    data_in_x1: out std_logic;
56 
    data_in_x10: out std_logic_vector(31 downto 0);
57 
    data_in_x11: out std_logic_vector(31 downto 0);
58 
    data_in_x12: out std_logic;
59 
    data_in_x13: out std_logic_vector(31 downto 0);
60 
    data_in_x14: out std_logic;
61 
    data_in_x15: out std_logic_vector(31 downto 0);
62 
    data_in_x16: out std_logic;
63 
    data_in_x17: out std_logic_vector(31 downto 0);
64 
    data_in_x18: out std_logic;
65 
    data_in_x19: out std_logic_vector(31 downto 0);
66 
    data_in_x2: out std_logic;
67 
    data_in_x20: out std_logic_vector(31 downto 0);
68 
    data_in_x21: out std_logic;
69 
    data_in_x22: out std_logic;
70 
    data_in_x23: out std_logic_vector(31 downto 0);
71 
    data_in_x24: out std_logic;
72 
    data_in_x25: out std_logic_vector(31 downto 0);
73 
    data_in_x26: out std_logic_vector(31 downto 0);
74 
    data_in_x3: out std_logic;
75 
    data_in_x4: out std_logic_vector(31 downto 0);
76 
    data_in_x5: out std_logic;
77 
    data_in_x6: out std_logic_vector(31 downto 0);
78 
    data_in_x7: out std_logic;
79 
    data_in_x8: out std_logic_vector(31 downto 0);
80 
    data_in_x9: out std_logic;
81 
    en: out std_logic;
82 
    en_x0: out std_logic;
83 
    en_x1: out std_logic;
84 
    en_x10: out std_logic;
85 
    en_x11: out std_logic;
86 
    en_x12: out std_logic;
87 
    en_x13: out std_logic;
88 
    en_x14: out std_logic;
89 
    en_x15: out std_logic;
90 
    en_x16: out std_logic;
91 
    en_x17: out std_logic;
92 
    en_x18: out std_logic;
93 
    en_x19: out std_logic;
94 
    en_x2: out std_logic;
95 
    en_x20: out std_logic;
96 
    en_x21: out std_logic;
97 
    en_x22: out std_logic;
98 
    en_x23: out std_logic;
99 
    en_x24: out std_logic;
100 
    en_x25: out std_logic;
101 
    en_x26: out std_logic;
102 
    en_x3: out std_logic;
103 
    en_x4: out std_logic;
104 
    en_x5: out std_logic;
105 
    en_x6: out std_logic;
106 
    en_x7: out std_logic;
107 
    en_x8: out std_logic;
108 
    en_x9: out std_logic;
109 
    fifo_rd_en_x1: out std_logic;
110 
    fifo_wr_din: out std_logic_vector(71 downto 0);
111 
    fifo_wr_en_x0: out std_logic;
112 
    rst_o: out std_logic;
113 
    user_int_1o: out std_logic;
114 
    user_int_2o: out std_logic;
115 
    user_int_3o: out std_logic
116 
  );
117 
end user_logic;
118 
 
119 
architecture structural of user_logic is
120 
  attribute core_generation_info: string;
121 
  attribute core_generation_info of structural : architecture is "PCIe_UserLogic_00,sysgen_core,{clock_period=5.00000000,clocking=Clock_Enables,compilation=NGC_Netlist,sample_periods=1.00000000000,testbench=0,total_blocks=351,xilinx_chipscope_block=1,xilinx_constant_block_block=23,xilinx_counter_block=1,xilinx_gateway_in_block=44,xilinx_gateway_out_block=39,xilinx_inverter_block=2,xilinx_logical_block_block=1,xilinx_register_block=89,xilinx_shared_memory_based_from_register_block=62,xilinx_shared_memory_based_to_register_block=62,xilinx_subsystem_generator_block=1,xilinx_system_generator_block=2,xilinx_type_converter_block=14,}";
122 
 
123 
  signal bram_addr: std_logic_vector(11 downto 0);
124 
  signal bram_addr_x0: std_logic_vector(11 downto 0);
125 
  signal bram_data: std_logic_vector(63 downto 0);
126 
  signal bram_rd_addr_net: std_logic_vector(11 downto 0);
127 
  signal bram_rd_dout_net: std_logic_vector(63 downto 0);
128 
  signal bram_wr_addr_net: std_logic_vector(11 downto 0);
129 
  signal bram_wr_din_net: std_logic_vector(63 downto 0);
130 
  signal bram_wr_en_net: std_logic_vector(7 downto 0);
131 
  signal ce_1_sg_x0: std_logic;
132 
  signal clk_1_sg_x0: std_logic;
133 
  signal constant10_op_net: std_logic;
134 
  signal constant11_op_net: std_logic;
135 
  signal constant12_op_net: std_logic;
136 
  signal constant14_op_net: std_logic;
137 
  signal constant15_op_net: std_logic;
138 
  signal constant19_op_net: std_logic;
139 
  signal constant1_op_net: std_logic;
140 
  signal constant20_op_net: std_logic;
141 
  signal constant21_op_net: std_logic;
142 
  signal constant22_op_net: std_logic;
143 
  signal constant23_op_net: std_logic;
144 
  signal constant24_op_net: std_logic;
145 
  signal constant25_op_net: std_logic;
146 
  signal constant26_op_net: std_logic;
147 
  signal constant2_op_net: std_logic_vector(7 downto 0);
148 
  signal constant3_op_net: std_logic;
149 
  signal constant4_op_net: std_logic;
150 
  signal constant6_op_net_x0: std_logic;
151 
  signal constant7_op_net: std_logic;
152 
  signal constant8_op_net: std_logic;
153 
  signal constant9_op_net: std_logic;
154 
  signal convert11_dout_net: std_logic;
155 
  signal convert12_dout_net: std_logic;
156 
  signal convert14_dout_net: std_logic;
157 
  signal convert15_dout_net: std_logic;
158 
  signal convert16_dout_net: std_logic;
159 
  signal convert17_dout_net: std_logic;
160 
  signal convert1_dout_net: std_logic;
161 
  signal convert4_dout_net: std_logic;
162 
  signal convert5_dout_net: std_logic;
163 
  signal convert6_dout_net: std_logic;
164 
  signal convert7_dout_net: std_logic;
165 
  signal convert8_dout_net: std_logic;
166 
  signal counter4_op_net: std_logic_vector(11 downto 0);
167 
  signal data_in_net: std_logic_vector(31 downto 0);
168 
  signal data_in_x0_net: std_logic;
169 
  signal data_in_x10_net: std_logic_vector(31 downto 0);
170 
  signal data_in_x11_net: std_logic_vector(31 downto 0);
171 
  signal data_in_x12_net: std_logic;
172 
  signal data_in_x13_net: std_logic_vector(31 downto 0);
173 
  signal data_in_x14_net: std_logic;
174 
  signal data_in_x15_net: std_logic_vector(31 downto 0);
175 
  signal data_in_x16_net: std_logic;
176 
  signal data_in_x17_net: std_logic_vector(31 downto 0);
177 
  signal data_in_x18_net: std_logic;
178 
  signal data_in_x19_net: std_logic_vector(31 downto 0);
179 
  signal data_in_x1_net: std_logic;
180 
  signal data_in_x20_net: std_logic_vector(31 downto 0);
181 
  signal data_in_x21_net: std_logic;
182 
  signal data_in_x22_net: std_logic;
183 
  signal data_in_x23_net: std_logic_vector(31 downto 0);
184 
  signal data_in_x24_net: std_logic;
185 
  signal data_in_x25_net: std_logic_vector(31 downto 0);
186 
  signal data_in_x26_net: std_logic_vector(31 downto 0);
187 
  signal data_in_x2_net: std_logic;
188 
  signal data_in_x3_net: std_logic;
189 
  signal data_in_x4_net: std_logic_vector(31 downto 0);
190 
  signal data_in_x5_net: std_logic;
191 
  signal data_in_x6_net: std_logic_vector(31 downto 0);
192 
  signal data_in_x7_net: std_logic;
193 
  signal data_in_x8_net: std_logic_vector(31 downto 0);
194 
  signal data_in_x9_net: std_logic;
195 
  signal data_out_x12_net: std_logic_vector(31 downto 0);
196 
  signal data_out_x13_net: std_logic;
197 
  signal data_out_x14_net: std_logic_vector(31 downto 0);
198 
  signal data_out_x15_net: std_logic;
199 
  signal data_out_x16_net: std_logic_vector(31 downto 0);
200 
  signal data_out_x17_net: std_logic;
201 
  signal data_out_x18_net: std_logic_vector(31 downto 0);
202 
  signal data_out_x19_net: std_logic;
203 
  signal data_out_x1_net: std_logic;
204 
  signal data_out_x20_net: std_logic_vector(31 downto 0);
205 
  signal data_out_x21_net: std_logic;
206 
  signal data_out_x22_net: std_logic_vector(31 downto 0);
207 
  signal data_out_x23_net: std_logic_vector(31 downto 0);
208 
  signal data_out_x24_net: std_logic;
209 
  signal data_out_x25_net: std_logic_vector(31 downto 0);
210 
  signal data_out_x26_net: std_logic;
211 
  signal data_out_x27_net: std_logic;
212 
  signal data_out_x28_net: std_logic_vector(31 downto 0);
213 
  signal data_out_x29_net: std_logic;
214 
  signal data_out_x2_net: std_logic_vector(31 downto 0);
215 
  signal data_out_x30_net: std_logic_vector(31 downto 0);
216 
  signal data_out_x31_net: std_logic;
217 
  signal data_out_x32_net: std_logic_vector(31 downto 0);
218 
  signal data_out_x3_net: std_logic;
219 
  signal data_out_x4_net: std_logic_vector(31 downto 0);
220 
  signal data_out_x5_net: std_logic;
221 
  signal data_out_x8_net: std_logic_vector(31 downto 0);
222 
  signal data_out_x9_net: std_logic;
223 
  signal dinb: std_logic_vector(31 downto 0);
224 
  signal dinb_x0: std_logic_vector(31 downto 0);
225 
  signal fifo_data_in_out: std_logic_vector(71 downto 0);
226 
  signal fifo_empty: std_logic;
227 
  signal fifo_empty_x0: std_logic;
228 
  signal fifo_rd_count: std_logic_vector(14 downto 0);
229 
  signal fifo_rd_count_net: std_logic_vector(14 downto 0);
230 
  signal fifo_rd_dout_net: std_logic_vector(71 downto 0);
231 
  signal fifo_rd_empty_net: std_logic;
232 
  signal fifo_rd_en: std_logic;
233 
  signal fifo_rd_en_net: std_logic;
234 
  signal fifo_rd_en_x0: std_logic;
235 
  signal fifo_rd_pempty: std_logic;
236 
  signal fifo_rd_pempty_net: std_logic;
237 
  signal fifo_rd_valid_net: std_logic;
238 
  signal fifo_wr_count: std_logic_vector(14 downto 0);
239 
  signal fifo_wr_count_net: std_logic_vector(14 downto 0);
240 
  signal fifo_wr_din_net: std_logic_vector(71 downto 0);
241 
  signal fifo_wr_en: std_logic;
242 
  signal fifo_wr_en_net: std_logic;
243 
  signal fifo_wr_full: std_logic;
244 
  signal fifo_wr_full_net: std_logic;
245 
  signal fifo_wr_pfull: std_logic;
246 
  signal fifo_wr_pfull_net: std_logic;
247 
  signal inverter3_op_net: std_logic;
248 
  signal inverter5_op_net: std_logic;
249 
  signal rst_i_net: std_logic;
250 
  signal rst_o_net: std_logic;
251 
  signal timecountreset: std_logic;
252 
  signal timecounttrigger: std_logic;
253 
  signal tx_en_in107_q_net: std_logic;
254 
  signal tx_en_in116_q_net: std_logic;
255 
  signal tx_en_in117_q_net: std_logic_vector(31 downto 0);
256 
  signal tx_en_in119_q_net: std_logic;
257 
  signal tx_en_in120_q_net: std_logic_vector(31 downto 0);
258 
  signal tx_en_in123_q_net: std_logic;
259 
  signal tx_en_in124_q_net: std_logic_vector(31 downto 0);
260 
  signal tx_en_in127_q_net: std_logic;
261 
  signal tx_en_in128_q_net: std_logic_vector(31 downto 0);
262 
  signal tx_en_in12_q_net: std_logic_vector(31 downto 0);
263 
  signal tx_en_in17_q_net: std_logic_vector(11 downto 0);
264 
  signal tx_en_in18_q_net: std_logic_vector(7 downto 0);
265 
  signal tx_en_in30_q_net: std_logic_vector(11 downto 0);
266 
  signal tx_en_in4_q_net: std_logic;
267 
  signal tx_en_in52_q_net: std_logic_vector(31 downto 0);
268 
  signal tx_en_in58_q_net: std_logic;
269 
  signal tx_en_in59_q_net: std_logic;
270 
  signal tx_en_in5_q_net: std_logic;
271 
  signal tx_en_in60_q_net: std_logic_vector(31 downto 0);
272 
  signal tx_en_in61_q_net: std_logic;
273 
  signal tx_en_in65_q_net: std_logic_vector(31 downto 0);
274 
  signal tx_en_in67_q_net: std_logic;
275 
  signal tx_en_in6_q_net: std_logic_vector(31 downto 0);
276 
  signal tx_en_in86_q_net: std_logic;
277 
  signal tx_en_in87_q_net: std_logic_vector(31 downto 0);
278 
  signal tx_en_in89_q_net: std_logic;
279 
  signal tx_en_in8_q_net: std_logic;
280 
  signal tx_en_in90_q_net: std_logic_vector(31 downto 0);
281 
  signal tx_en_in92_q_net: std_logic;
282 
  signal tx_en_in93_q_net: std_logic_vector(31 downto 0);
283 
  signal user_int_1o_net: std_logic;
284 
  signal user_int_2o_net: std_logic;
285 
  signal user_int_3o_net: std_logic;
286 
 
287 
begin
288 
  bram_rd_dout_net <= bram_rd_dout;
289 
  ce_1_sg_x0 <= ce_1;
290 
  clk_1_sg_x0 <= clk_1;
291 
  data_out_x1_net <= data_out_x1;
292 
  data_out_x12_net <= data_out_x12;
293 
  data_out_x13_net <= data_out_x13;
294 
  data_out_x14_net <= data_out_x14;
295 
  data_out_x15_net <= data_out_x15;
296 
  data_out_x16_net <= data_out_x16;
297 
  data_out_x17_net <= data_out_x17;
298 
  data_out_x18_net <= data_out_x18;
299 
  data_out_x19_net <= data_out_x19;
300 
  data_out_x2_net <= data_out_x2;
301 
  data_out_x20_net <= data_out_x20;
302 
  data_out_x21_net <= data_out_x21;
303 
  data_out_x22_net <= data_out_x22;
304 
  data_out_x23_net <= data_out_x23;
305 
  data_out_x24_net <= data_out_x24;
306 
  data_out_x25_net <= data_out_x25;
307 
  data_out_x26_net <= data_out_x26;
308 
  data_out_x27_net <= data_out_x27;
309 
  data_out_x28_net <= data_out_x28;
310 
  data_out_x29_net <= data_out_x29;
311 
  data_out_x3_net <= data_out_x3;
312 
  data_out_x30_net <= data_out_x30;
313 
  data_out_x31_net <= data_out_x31;
314 
  data_out_x32_net <= data_out_x32;
315 
  data_out_x4_net <= data_out_x4;
316 
  data_out_x5_net <= data_out_x5;
317 
  data_out_x8_net <= data_out_x8;
318 
  data_out_x9_net <= data_out_x9;
319 
  fifo_rd_count_net <= fifo_rd_count_x0;
320 
  fifo_rd_dout_net <= fifo_rd_dout;
321 
  fifo_rd_empty_net <= fifo_rd_empty;
322 
  fifo_rd_pempty_net <= fifo_rd_pempty_x0;
323 
  fifo_rd_valid_net <= fifo_rd_valid;
324 
  fifo_wr_count_net <= fifo_wr_count_x0;
325 
  fifo_wr_full_net <= fifo_wr_full_x0;
326 
  fifo_wr_pfull_net <= fifo_wr_pfull_x0;
327 
  rst_i_net <= rst_i;
328 
  bram_rd_addr <= bram_rd_addr_net;
329 
  bram_wr_addr <= bram_wr_addr_net;
330 
  bram_wr_din <= bram_wr_din_net;
331 
  bram_wr_en <= bram_wr_en_net;
332 
  data_in <= data_in_net;
333 
  data_in_x0 <= data_in_x0_net;
334 
  data_in_x1 <= data_in_x1_net;
335 
  data_in_x10 <= data_in_x10_net;
336 
  data_in_x11 <= data_in_x11_net;
337 
  data_in_x12 <= data_in_x12_net;
338 
  data_in_x13 <= data_in_x13_net;
339 
  data_in_x14 <= data_in_x14_net;
340 
  data_in_x15 <= data_in_x15_net;
341 
  data_in_x16 <= data_in_x16_net;
342 
  data_in_x17 <= data_in_x17_net;
343 
  data_in_x18 <= data_in_x18_net;
344 
  data_in_x19 <= data_in_x19_net;
345 
  data_in_x2 <= data_in_x2_net;
346 
  data_in_x20 <= data_in_x20_net;
347 
  data_in_x21 <= data_in_x21_net;
348 
  data_in_x22 <= data_in_x22_net;
349 
  data_in_x23 <= data_in_x23_net;
350 
  data_in_x24 <= data_in_x24_net;
351 
  data_in_x25 <= data_in_x25_net;
352 
  data_in_x26 <= data_in_x26_net;
353 
  data_in_x3 <= data_in_x3_net;
354 
  data_in_x4 <= data_in_x4_net;
355 
  data_in_x5 <= data_in_x5_net;
356 
  data_in_x6 <= data_in_x6_net;
357 
  data_in_x7 <= data_in_x7_net;
358 
  data_in_x8 <= data_in_x8_net;
359 
  data_in_x9 <= data_in_x9_net;
360 
  en <= constant6_op_net_x0;
361 
  en_x0 <= constant6_op_net_x0;
362 
  en_x1 <= constant6_op_net_x0;
363 
  en_x10 <= constant6_op_net_x0;
364 
  en_x11 <= constant6_op_net_x0;
365 
  en_x12 <= constant6_op_net_x0;
366 
  en_x13 <= constant6_op_net_x0;
367 
  en_x14 <= constant6_op_net_x0;
368 
  en_x15 <= constant6_op_net_x0;
369 
  en_x16 <= constant6_op_net_x0;
370 
  en_x17 <= constant6_op_net_x0;
371 
  en_x18 <= constant6_op_net_x0;
372 
  en_x19 <= constant6_op_net_x0;
373 
  en_x2 <= constant6_op_net_x0;
374 
  en_x20 <= constant6_op_net_x0;
375 
  en_x21 <= constant6_op_net_x0;
376 
  en_x22 <= constant6_op_net_x0;
377 
  en_x23 <= constant6_op_net_x0;
378 
  en_x24 <= constant6_op_net_x0;
379 
  en_x25 <= constant6_op_net_x0;
380 
  en_x26 <= constant6_op_net_x0;
381 
  en_x3 <= constant6_op_net_x0;
382 
  en_x4 <= constant6_op_net_x0;
383 
  en_x5 <= constant6_op_net_x0;
384 
  en_x6 <= constant6_op_net_x0;
385 
  en_x7 <= constant6_op_net_x0;
386 
  en_x8 <= constant6_op_net_x0;
387 
  en_x9 <= constant6_op_net_x0;
388 
  fifo_rd_en_x1 <= fifo_rd_en_net;
389 
  fifo_wr_din <= fifo_wr_din_net;
390 
  fifo_wr_en_x0 <= fifo_wr_en_net;
391 
  rst_o <= rst_o_net;
392 
  user_int_1o <= user_int_1o_net;
393 
  user_int_2o <= user_int_2o_net;
394 
  user_int_3o <= user_int_3o_net;
395 
 
396 
  chipscope: entity work.xlchipscope
397 
    port map (
398 
      ce => ce_1_sg_x0,
399 
      clk => clk_1_sg_x0,
400 
      clr => '0',
401 
      trig0 => bram_addr,
402 
      trig1 => bram_data,
403 
      trig10 => fifo_wr_count,
404 
      trig2(0) => fifo_empty_x0,
405 
      trig3(0) => fifo_rd_en_x0,
406 
      trig4(0) => fifo_wr_en,
407 
      trig5 => fifo_data_in_out,
408 
      trig6(0) => fifo_rd_pempty,
409 
      trig7 => fifo_rd_count,
410 
      trig8(0) => fifo_wr_full,
411 
      trig9(0) => fifo_wr_pfull
412 
    );
413 
 
414 
  constant1: entity work.constant_963ed6358a
415 
    port map (
416 
      ce => '0',
417 
      clk => '0',
418 
      clr => '0',
419 
      op(0) => constant1_op_net
420 
    );
421 
 
422 
  constant10: entity work.constant_963ed6358a
423 
    port map (
424 
      ce => '0',
425 
      clk => '0',
426 
      clr => '0',
427 
      op(0) => constant10_op_net
428 
    );
429 
 
430 
  constant11: entity work.constant_963ed6358a
431 
    port map (
432 
      ce => '0',
433 
      clk => '0',
434 
      clr => '0',
435 
      op(0) => constant11_op_net
436 
    );
437 
 
438 
  constant12: entity work.constant_963ed6358a
439 
    port map (
440 
      ce => '0',
441 
      clk => '0',
442 
      clr => '0',
443 
      op(0) => constant12_op_net
444 
    );
445 
 
446 
  constant14: entity work.constant_6293007044
447 
    port map (
448 
      ce => '0',
449 
      clk => '0',
450 
      clr => '0',
451 
      op(0) => constant14_op_net
452 
    );
453 
 
454 
  constant15: entity work.constant_6293007044
455 
    port map (
456 
      ce => '0',
457 
      clk => '0',
458 
      clr => '0',
459 
      op(0) => constant15_op_net
460 
    );
461 
 
462 
  constant19: entity work.constant_963ed6358a
463 
    port map (
464 
      ce => '0',
465 
      clk => '0',
466 
      clr => '0',
467 
      op(0) => constant19_op_net
468 
    );
469 
 
470 
  constant2: entity work.constant_19562ab42f
471 
    port map (
472 
      ce => '0',
473 
      clk => '0',
474 
      clr => '0',
475 
      op => constant2_op_net
476 
    );
477 
 
478 
  constant20: entity work.constant_963ed6358a
479 
    port map (
480 
      ce => '0',
481 
      clk => '0',
482 
      clr => '0',
483 
      op(0) => constant20_op_net
484 
    );
485 
 
486 
  constant21: entity work.constant_963ed6358a
487 
    port map (
488 
      ce => '0',
489 
      clk => '0',
490 
      clr => '0',
491 
      op(0) => constant21_op_net
492 
    );
493 
 
494 
  constant22: entity work.constant_963ed6358a
495 
    port map (
496 
      ce => '0',
497 
      clk => '0',
498 
      clr => '0',
499 
      op(0) => constant22_op_net
500 
    );
501 
 
502 
  constant23: entity work.constant_963ed6358a
503 
    port map (
504 
      ce => '0',
505 
      clk => '0',
506 
      clr => '0',
507 
      op(0) => constant23_op_net
508 
    );
509 
 
510 
  constant24: entity work.constant_963ed6358a
511 
    port map (
512 
      ce => '0',
513 
      clk => '0',
514 
      clr => '0',
515 
      op(0) => constant24_op_net
516 
    );
517 
 
518 
  constant25: entity work.constant_963ed6358a
519 
    port map (
520 
      ce => '0',
521 
      clk => '0',
522 
      clr => '0',
523 
      op(0) => constant25_op_net
524 
    );
525 
 
526 
  constant26: entity work.constant_963ed6358a
527 
    port map (
528 
      ce => '0',
529 
      clk => '0',
530 
      clr => '0',
531 
      op(0) => constant26_op_net
532 
    );
533 
 
534 
  constant3: entity work.constant_963ed6358a
535 
    port map (
536 
      ce => '0',
537 
      clk => '0',
538 
      clr => '0',
539 
      op(0) => constant3_op_net
540 
    );
541 
 
542 
  constant4: entity work.constant_963ed6358a
543 
    port map (
544 
      ce => '0',
545 
      clk => '0',
546 
      clr => '0',
547 
      op(0) => constant4_op_net
548 
    );
549 
 
550 
  constant6: entity work.constant_6293007044
551 
    port map (
552 
      ce => '0',
553 
      clk => '0',
554 
      clr => '0',
555 
      op(0) => constant6_op_net_x0
556 
    );
557 
 
558 
  constant7: entity work.constant_963ed6358a
559 
    port map (
560 
      ce => '0',
561 
      clk => '0',
562 
      clr => '0',
563 
      op(0) => constant7_op_net
564 
    );
565 
 
566 
  constant8: entity work.constant_963ed6358a
567 
    port map (
568 
      ce => '0',
569 
      clk => '0',
570 
      clr => '0',
571 
      op(0) => constant8_op_net
572 
    );
573 
 
574 
  constant9: entity work.constant_963ed6358a
575 
    port map (
576 
      ce => '0',
577 
      clk => '0',
578 
      clr => '0',
579 
      op(0) => constant9_op_net
580 
    );
581 
 
582 
  convert1: entity work.xlconvert
583 
    generic map (
584 
      bool_conversion => 1,
585 
      din_arith => 1,
586 
      din_bin_pt => 0,
587 
      din_width => 1,
588 
      dout_arith => 1,
589 
      dout_bin_pt => 0,
590 
      dout_width => 1,
591 
      latency => 0,
592 
      overflow => xlWrap,
593 
      quantization => xlTruncate
594 
    )
595 
    port map (
596 
      ce => ce_1_sg_x0,
597 
      clk => clk_1_sg_x0,
598 
      clr => '0',
599 
      din(0) => tx_en_in5_q_net,
600 
      en => "1",
601 
      dout(0) => convert1_dout_net
602 
    );
603 
 
604 
  convert11: entity work.xlconvert
605 
    generic map (
606 
      bool_conversion => 1,
607 
      din_arith => 1,
608 
      din_bin_pt => 0,
609 
      din_width => 1,
610 
      dout_arith => 1,
611 
      dout_bin_pt => 0,
612 
      dout_width => 1,
613 
      latency => 0,
614 
      overflow => xlWrap,
615 
      quantization => xlTruncate
616 
    )
617 
    port map (
618 
      ce => ce_1_sg_x0,
619 
      clk => clk_1_sg_x0,
620 
      clr => '0',
621 
      din(0) => tx_en_in89_q_net,
622 
      en => "1",
623 
      dout(0) => convert11_dout_net
624 
    );
625 
 
626 
  convert12: entity work.xlconvert
627 
    generic map (
628 
      bool_conversion => 1,
629 
      din_arith => 1,
630 
      din_bin_pt => 0,
631 
      din_width => 1,
632 
      dout_arith => 1,
633 
      dout_bin_pt => 0,
634 
      dout_width => 1,
635 
      latency => 0,
636 
      overflow => xlWrap,
637 
      quantization => xlTruncate
638 
    )
639 
    port map (
640 
      ce => ce_1_sg_x0,
641 
      clk => clk_1_sg_x0,
642 
      clr => '0',
643 
      din(0) => tx_en_in92_q_net,
644 
      en => "1",
645 
      dout(0) => convert12_dout_net
646 
    );
647 
 
648 
  convert14: entity work.xlconvert
649 
    generic map (
650 
      bool_conversion => 1,
651 
      din_arith => 1,
652 
      din_bin_pt => 0,
653 
      din_width => 1,
654 
      dout_arith => 1,
655 
      dout_bin_pt => 0,
656 
      dout_width => 1,
657 
      latency => 0,
658 
      overflow => xlWrap,
659 
      quantization => xlTruncate
660 
    )
661 
    port map (
662 
      ce => ce_1_sg_x0,
663 
      clk => clk_1_sg_x0,
664 
      clr => '0',
665 
      din(0) => tx_en_in116_q_net,
666 
      en => "1",
667 
      dout(0) => convert14_dout_net
668 
    );
669 
 
670 
  convert15: entity work.xlconvert
671 
    generic map (
672 
      bool_conversion => 1,
673 
      din_arith => 1,
674 
      din_bin_pt => 0,
675 
      din_width => 1,
676 
      dout_arith => 1,
677 
      dout_bin_pt => 0,
678 
      dout_width => 1,
679 
      latency => 0,
680 
      overflow => xlWrap,
681 
      quantization => xlTruncate
682 
    )
683 
    port map (
684 
      ce => ce_1_sg_x0,
685 
      clk => clk_1_sg_x0,
686 
      clr => '0',
687 
      din(0) => tx_en_in119_q_net,
688 
      en => "1",
689 
      dout(0) => convert15_dout_net
690 
    );
691 
 
692 
  convert16: entity work.xlconvert
693 
    generic map (
694 
      bool_conversion => 1,
695 
      din_arith => 1,
696 
      din_bin_pt => 0,
697 
      din_width => 1,
698 
      dout_arith => 1,
699 
      dout_bin_pt => 0,
700 
      dout_width => 1,
701 
      latency => 0,
702 
      overflow => xlWrap,
703 
      quantization => xlTruncate
704 
    )
705 
    port map (
706 
      ce => ce_1_sg_x0,
707 
      clk => clk_1_sg_x0,
708 
      clr => '0',
709 
      din(0) => tx_en_in123_q_net,
710 
      en => "1",
711 
      dout(0) => convert16_dout_net
712 
    );
713 
 
714 
  convert17: entity work.xlconvert
715 
    generic map (
716 
      bool_conversion => 1,
717 
      din_arith => 1,
718 
      din_bin_pt => 0,
719 
      din_width => 1,
720 
      dout_arith => 1,
721 
      dout_bin_pt => 0,
722 
      dout_width => 1,
723 
      latency => 0,
724 
      overflow => xlWrap,
725 
      quantization => xlTruncate
726 
    )
727 
    port map (
728 
      ce => ce_1_sg_x0,
729 
      clk => clk_1_sg_x0,
730 
      clr => '0',
731 
      din(0) => tx_en_in127_q_net,
732 
      en => "1",
733 
      dout(0) => convert17_dout_net
734 
    );
735 
 
736 
  convert3: entity work.xlconvert
737 
    generic map (
738 
      bool_conversion => 1,
739 
      din_arith => 1,
740 
      din_bin_pt => 0,
741 
      din_width => 1,
742 
      dout_arith => 1,
743 
      dout_bin_pt => 0,
744 
      dout_width => 1,
745 
      latency => 0,
746 
      overflow => xlWrap,
747 
      quantization => xlTruncate
748 
    )
749 
    port map (
750 
      ce => ce_1_sg_x0,
751 
      clk => clk_1_sg_x0,
752 
      clr => '0',
753 
      din(0) => tx_en_in4_q_net,
754 
      en => "1",
755 
      dout(0) => timecountreset
756 
    );
757 
 
758 
  convert4: entity work.xlconvert
759 
    generic map (
760 
      bool_conversion => 1,
761 
      din_arith => 1,
762 
      din_bin_pt => 0,
763 
      din_width => 1,
764 
      dout_arith => 1,
765 
      dout_bin_pt => 0,
766 
      dout_width => 1,
767 
      latency => 0,
768 
      overflow => xlWrap,
769 
      quantization => xlTruncate
770 
    )
771 
    port map (
772 
      ce => ce_1_sg_x0,
773 
      clk => clk_1_sg_x0,
774 
      clr => '0',
775 
      din(0) => tx_en_in86_q_net,
776 
      en => "1",
777 
      dout(0) => convert4_dout_net
778 
    );
779 
 
780 
  convert5: entity work.xlconvert
781 
    generic map (
782 
      bool_conversion => 1,
783 
      din_arith => 1,
784 
      din_bin_pt => 0,
785 
      din_width => 1,
786 
      dout_arith => 1,
787 
      dout_bin_pt => 0,
788 
      dout_width => 1,
789 
      latency => 0,
790 
      overflow => xlWrap,
791 
      quantization => xlTruncate
792 
    )
793 
    port map (
794 
      ce => ce_1_sg_x0,
795 
      clk => clk_1_sg_x0,
796 
      clr => '0',
797 
      din(0) => tx_en_in58_q_net,
798 
      en => "1",
799 
      dout(0) => convert5_dout_net
800 
    );
801 
 
802 
  convert6: entity work.xlconvert
803 
    generic map (
804 
      bool_conversion => 1,
805 
      din_arith => 1,
806 
      din_bin_pt => 0,
807 
      din_width => 1,
808 
      dout_arith => 1,
809 
      dout_bin_pt => 0,
810 
      dout_width => 1,
811 
      latency => 0,
812 
      overflow => xlWrap,
813 
      quantization => xlTruncate
814 
    )
815 
    port map (
816 
      ce => ce_1_sg_x0,
817 
      clk => clk_1_sg_x0,
818 
      clr => '0',
819 
      din(0) => tx_en_in59_q_net,
820 
      en => "1",
821 
      dout(0) => convert6_dout_net
822 
    );
823 
 
824 
  convert7: entity work.xlconvert
825 
    generic map (
826 
      bool_conversion => 1,
827 
      din_arith => 1,
828 
      din_bin_pt => 0,
829 
      din_width => 1,
830 
      dout_arith => 1,
831 
      dout_bin_pt => 0,
832 
      dout_width => 1,
833 
      latency => 0,
834 
      overflow => xlWrap,
835 
      quantization => xlTruncate
836 
    )
837 
    port map (
838 
      ce => ce_1_sg_x0,
839 
      clk => clk_1_sg_x0,
840 
      clr => '0',
841 
      din(0) => tx_en_in61_q_net,
842 
      en => "1",
843 
      dout(0) => convert7_dout_net
844 
    );
845 
 
846 
  convert8: entity work.xlconvert
847 
    generic map (
848 
      bool_conversion => 1,
849 
      din_arith => 1,
850 
      din_bin_pt => 0,
851 
      din_width => 1,
852 
      dout_arith => 1,
853 
      dout_bin_pt => 0,
854 
      dout_width => 1,
855 
      latency => 0,
856 
      overflow => xlWrap,
857 
      quantization => xlTruncate
858 
    )
859 
    port map (
860 
      ce => ce_1_sg_x0,
861 
      clk => clk_1_sg_x0,
862 
      clr => '0',
863 
      din(0) => tx_en_in67_q_net,
864 
      en => "1",
865 
      dout(0) => convert8_dout_net
866 
    );
867 
 
868 
  convert9: entity work.xlconvert
869 
    generic map (
870 
      bool_conversion => 1,
871 
      din_arith => 1,
872 
      din_bin_pt => 0,
873 
      din_width => 1,
874 
      dout_arith => 1,
875 
      dout_bin_pt => 0,
876 
      dout_width => 1,
877 
      latency => 0,
878 
      overflow => xlWrap,
879 
      quantization => xlTruncate
880 
    )
881 
    port map (
882 
      ce => ce_1_sg_x0,
883 
      clk => clk_1_sg_x0,
884 
      clr => '0',
885 
      din(0) => tx_en_in8_q_net,
886 
      en => "1",
887 
      dout(0) => timecounttrigger
888 
    );
889 
 
890 
  counter4: entity work.xlcounter_free
891 
    generic map (
892 
      core_name0 => "cntr_11_0_341fbb8cfa0e669e",
893 
      op_arith => xlUnsigned,
894 
      op_width => 12
895 
    )
896 
    port map (
897 
      ce => ce_1_sg_x0,
898 
      clk => clk_1_sg_x0,
899 
      clr => '0',
900 
      en => "1",
901 
      rst => "0",
902 
      op => counter4_op_net
903 
    );
904 
 
905 
  inverter3: entity work.inverter_e5b38cca3b
906 
    port map (
907 
      ce => ce_1_sg_x0,
908 
      clk => clk_1_sg_x0,
909 
      clr => '0',
910 
      ip(0) => rst_i_net,
911 
      op(0) => inverter3_op_net
912 
    );
913 
 
914 
  inverter5: entity work.inverter_e5b38cca3b
915 
    port map (
916 
      ce => ce_1_sg_x0,
917 
      clk => clk_1_sg_x0,
918 
      clr => '0',
919 
      ip(0) => tx_en_in107_q_net,
920 
      op(0) => inverter5_op_net
921 
    );
922 
 
923 
  logical4: entity work.logical_80f90b97d0
924 
    port map (
925 
      ce => '0',
926 
      clk => '0',
927 
      clr => '0',
928 
      d0(0) => constant15_op_net,
929 
      d1(0) => inverter5_op_net,
930 
      y(0) => fifo_rd_en
931 
    );
932 
 
933 
  tx_en_in1: entity work.xlregister
934 
    generic map (
935 
      d_width => 1,
936 
      init_value => b"0"
937 
    )
938 
    port map (
939 
      ce => ce_1_sg_x0,
940 
      clk => clk_1_sg_x0,
941 
      d(0) => timecountreset,
942 
      en => "1",
943 
      rst => "0",
944 
      q(0) => data_in_x0_net
945 
    );
946 
 
947 
  tx_en_in10: entity work.xlregister
948 
    generic map (
949 
      d_width => 32,
950 
      init_value => b"00000000000000000000000000000000"
951 
    )
952 
    port map (
953 
      ce => ce_1_sg_x0,
954 
      clk => clk_1_sg_x0,
955 
      d => tx_en_in12_q_net,
956 
      en(0) => timecounttrigger,
957 
      rst(0) => constant3_op_net,
958 
      q => data_in_x20_net
959 
    );
960 
 
961 
  tx_en_in100: entity work.xlregister
962 
    generic map (
963 
      d_width => 1,
964 
      init_value => b"0"
965 
    )
966 
    port map (
967 
      ce => ce_1_sg_x0,
968 
      clk => clk_1_sg_x0,
969 
      d(0) => convert12_dout_net,
970 
      en => "1",
971 
      rst => "0",
972 
      q(0) => data_in_x9_net
973 
    );
974 
 
975 
  tx_en_in105: entity work.xlregister
976 
    generic map (
977 
      d_width => 1,
978 
      init_value => b"0"
979 
    )
980 
    port map (
981 
      ce => ce_1_sg_x0,
982 
      clk => clk_1_sg_x0,
983 
      d(0) => fifo_rd_empty_net,
984 
      en => "1",
985 
      rst => "0",
986 
      q(0) => fifo_empty
987 
    );
988 
 
989 
  tx_en_in107: entity work.xlregister
990 
    generic map (
991 
      d_width => 1,
992 
      init_value => b"0"
993 
    )
994 
    port map (
995 
      ce => ce_1_sg_x0,
996 
      clk => clk_1_sg_x0,
997 
      d(0) => fifo_empty,
998 
      en => "1",
999 
      rst => "0",
1000 
      q(0) => tx_en_in107_q_net
1001 
    );
1002 
 
1003 
  tx_en_in108: entity work.xlregister
1004 
    generic map (
1005 
      d_width => 1,
1006 
      init_value => b"0"
1007 
    )
1008 
    port map (
1009 
      ce => ce_1_sg_x0,
1010 
      clk => clk_1_sg_x0,
1011 
      d(0) => fifo_rd_en,
1012 
      en(0) => constant14_op_net,
1013 
      rst => "0",
1014 
      q(0) => fifo_rd_en_net
1015 
    );
1016 
 
1017 
  tx_en_in109: entity work.xlregister
1018 
    generic map (
1019 
      d_width => 1,
1020 
      init_value => b"0"
1021 
    )
1022 
    port map (
1023 
      ce => ce_1_sg_x0,
1024 
      clk => clk_1_sg_x0,
1025 
      d(0) => fifo_rd_valid_net,
1026 
      en => "1",
1027 
      rst => "0",
1028 
      q(0) => fifo_wr_en_net
1029 
    );
1030 
 
1031 
  tx_en_in11: entity work.xlregister
1032 
    generic map (
1033 
      d_width => 12,
1034 
      init_value => b"000000000000"
1035 
    )
1036 
    port map (
1037 
      ce => ce_1_sg_x0,
1038 
      clk => clk_1_sg_x0,
1039 
      d => bram_addr_x0,
1040 
      en => "1",
1041 
      rst => "0",
1042 
      q => bram_addr
1043 
    );
1044 
 
1045 
  tx_en_in113: entity work.xlregister
1046 
    generic map (
1047 
      d_width => 1,
1048 
      init_value => b"0"
1049 
    )
1050 
    port map (
1051 
      ce => ce_1_sg_x0,
1052 
      clk => clk_1_sg_x0,
1053 
      d(0) => convert14_dout_net,
1054 
      en => "1",
1055 
      rst => "0",
1056 
      q(0) => data_in_x12_net
1057 
    );
1058 
 
1059 
  tx_en_in114: entity work.xlregister
1060 
    generic map (
1061 
      d_width => 1,
1062 
      init_value => b"0"
1063 
    )
1064 
    port map (
1065 
      ce => ce_1_sg_x0,
1066 
      clk => clk_1_sg_x0,
1067 
      d(0) => convert15_dout_net,
1068 
      en => "1",
1069 
      rst => "0",
1070 
      q(0) => data_in_x14_net
1071 
    );
1072 
 
1073 
  tx_en_in115: entity work.xlregister
1074 
    generic map (
1075 
      d_width => 32,
1076 
      init_value => b"00000000000000110000110100100011"
1077 
    )
1078 
    port map (
1079 
      ce => ce_1_sg_x0,
1080 
      clk => clk_1_sg_x0,
1081 
      d => tx_en_in117_q_net,
1082 
      en(0) => convert14_dout_net,
1083 
      rst(0) => constant19_op_net,
1084 
      q => data_in_x13_net
1085 
    );
1086 
 
1087 
  tx_en_in116: entity work.xlregister
1088 
    generic map (
1089 
      d_width => 1,
1090 
      init_value => b"0"
1091 
    )
1092 
    port map (
1093 
      ce => ce_1_sg_x0,
1094 
      clk => clk_1_sg_x0,
1095 
      d(0) => data_out_x19_net,
1096 
      en => "1",
1097 
      rst => "0",
1098 
      q(0) => tx_en_in116_q_net
1099 
    );
1100 
 
1101 
  tx_en_in117: entity work.xlregister
1102 
    generic map (
1103 
      d_width => 32,
1104 
      init_value => b"00000000000000000000000000000000"
1105 
    )
1106 
    port map (
1107 
      ce => ce_1_sg_x0,
1108 
      clk => clk_1_sg_x0,
1109 
      d => data_out_x18_net,
1110 
      en => "1",
1111 
      rst => "0",
1112 
      q => tx_en_in117_q_net
1113 
    );
1114 
 
1115 
  tx_en_in118: entity work.xlregister
1116 
    generic map (
1117 
      d_width => 32,
1118 
      init_value => b"00000000000000000100101011000000"
1119 
    )
1120 
    port map (
1121 
      ce => ce_1_sg_x0,
1122 
      clk => clk_1_sg_x0,
1123 
      d => tx_en_in120_q_net,
1124 
      en(0) => convert15_dout_net,
1125 
      rst(0) => constant21_op_net,
1126 
      q => data_in_x15_net
1127 
    );
1128 
 
1129 
  tx_en_in119: entity work.xlregister
1130 
    generic map (
1131 
      d_width => 1,
1132 
      init_value => b"0"
1133 
    )
1134 
    port map (
1135 
      ce => ce_1_sg_x0,
1136 
      clk => clk_1_sg_x0,
1137 
      d(0) => data_out_x21_net,
1138 
      en => "1",
1139 
      rst => "0",
1140 
      q(0) => tx_en_in119_q_net
1141 
    );
1142 
 
1143 
  tx_en_in12: entity work.xlregister
1144 
    generic map (
1145 
      d_width => 32,
1146 
      init_value => b"00000000000000000000000000000000"
1147 
    )
1148 
    port map (
1149 
      ce => ce_1_sg_x0,
1150 
      clk => clk_1_sg_x0,
1151 
      d => data_out_x30_net,
1152 
      en => "1",
1153 
      rst => "0",
1154 
      q => tx_en_in12_q_net
1155 
    );
1156 
 
1157 
  tx_en_in120: entity work.xlregister
1158 
    generic map (
1159 
      d_width => 32,
1160 
      init_value => b"00000000000000000000000000000000"
1161 
    )
1162 
    port map (
1163 
      ce => ce_1_sg_x0,
1164 
      clk => clk_1_sg_x0,
1165 
      d => data_out_x20_net,
1166 
      en => "1",
1167 
      rst => "0",
1168 
      q => tx_en_in120_q_net
1169 
    );
1170 
 
1171 
  tx_en_in121: entity work.xlregister
1172 
    generic map (
1173 
      d_width => 1,
1174 
      init_value => b"0"
1175 
    )
1176 
    port map (
1177 
      ce => ce_1_sg_x0,
1178 
      clk => clk_1_sg_x0,
1179 
      d(0) => convert16_dout_net,
1180 
      en => "1",
1181 
      rst => "0",
1182 
      q(0) => data_in_x16_net
1183 
    );
1184 
 
1185 
  tx_en_in122: entity work.xlregister
1186 
    generic map (
1187 
      d_width => 32,
1188 
      init_value => b"00000000000000000000000000000000"
1189 
    )
1190 
    port map (
1191 
      ce => ce_1_sg_x0,
1192 
      clk => clk_1_sg_x0,
1193 
      d => tx_en_in124_q_net,
1194 
      en(0) => convert16_dout_net,
1195 
      rst(0) => constant22_op_net,
1196 
      q => data_in_x17_net
1197 
    );
1198 
 
1199 
  tx_en_in123: entity work.xlregister
1200 
    generic map (
1201 
      d_width => 1,
1202 
      init_value => b"0"
1203 
    )
1204 
    port map (
1205 
      ce => ce_1_sg_x0,
1206 
      clk => clk_1_sg_x0,
1207 
      d(0) => data_out_x24_net,
1208 
      en => "1",
1209 
      rst => "0",
1210 
      q(0) => tx_en_in123_q_net
1211 
    );
1212 
 
1213 
  tx_en_in124: entity work.xlregister
1214 
    generic map (
1215 
      d_width => 32,
1216 
      init_value => b"00000000000000000000000000000000"
1217 
    )
1218 
    port map (
1219 
      ce => ce_1_sg_x0,
1220 
      clk => clk_1_sg_x0,
1221 
      d => data_out_x23_net,
1222 
      en => "1",
1223 
      rst => "0",
1224 
      q => tx_en_in124_q_net
1225 
    );
1226 
 
1227 
  tx_en_in125: entity work.xlregister
1228 
    generic map (
1229 
      d_width => 1,
1230 
      init_value => b"0"
1231 
    )
1232 
    port map (
1233 
      ce => ce_1_sg_x0,
1234 
      clk => clk_1_sg_x0,
1235 
      d(0) => convert17_dout_net,
1236 
      en => "1",
1237 
      rst => "0",
1238 
      q(0) => data_in_x18_net
1239 
    );
1240 
 
1241 
  tx_en_in126: entity work.xlregister
1242 
    generic map (
1243 
      d_width => 32,
1244 
      init_value => b"00000000000000000000000000000000"
1245 
    )
1246 
    port map (
1247 
      ce => ce_1_sg_x0,
1248 
      clk => clk_1_sg_x0,
1249 
      d => tx_en_in128_q_net,
1250 
      en(0) => convert17_dout_net,
1251 
      rst(0) => constant23_op_net,
1252 
      q => data_in_x19_net
1253 
    );
1254 
 
1255 
  tx_en_in127: entity work.xlregister
1256 
    generic map (
1257 
      d_width => 1,
1258 
      init_value => b"0"
1259 
    )
1260 
    port map (
1261 
      ce => ce_1_sg_x0,
1262 
      clk => clk_1_sg_x0,
1263 
      d(0) => data_out_x26_net,
1264 
      en => "1",
1265 
      rst => "0",
1266 
      q(0) => tx_en_in127_q_net
1267 
    );
1268 
 
1269 
  tx_en_in128: entity work.xlregister
1270 
    generic map (
1271 
      d_width => 32,
1272 
      init_value => b"00000000000000000000000000000000"
1273 
    )
1274 
    port map (
1275 
      ce => ce_1_sg_x0,
1276 
      clk => clk_1_sg_x0,
1277 
      d => data_out_x25_net,
1278 
      en => "1",
1279 
      rst => "0",
1280 
      q => tx_en_in128_q_net
1281 
    );
1282 
 
1283 
  tx_en_in13: entity work.xlregister
1284 
    generic map (
1285 
      d_width => 1,
1286 
      init_value => b"0"
1287 
    )
1288 
    port map (
1289 
      ce => ce_1_sg_x0,
1290 
      clk => clk_1_sg_x0,
1291 
      d(0) => convert8_dout_net,
1292 
      en => "1",
1293 
      rst => "0",
1294 
      q(0) => data_in_x3_net
1295 
    );
1296 
 
1297 
  tx_en_in14: entity work.xlregister
1298 
    generic map (
1299 
      d_width => 64,
1300 
      init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
1301 
    )
1302 
    port map (
1303 
      ce => ce_1_sg_x0,
1304 
      clk => clk_1_sg_x0,
1305 
      d => bram_rd_dout_net,
1306 
      en => "1",
1307 
      rst => "0",
1308 
      q => bram_data
1309 
    );
1310 
 
1311 
  tx_en_in15: entity work.xlregister
1312 
    generic map (
1313 
      d_width => 12,
1314 
      init_value => b"000000000000"
1315 
    )
1316 
    port map (
1317 
      ce => ce_1_sg_x0,
1318 
      clk => clk_1_sg_x0,
1319 
      d => counter4_op_net,
1320 
      en => "1",
1321 
      rst => "0",
1322 
      q => bram_rd_addr_net
1323 
    );
1324 
 
1325 
  tx_en_in16: entity work.xlregister
1326 
    generic map (
1327 
      d_width => 12,
1328 
      init_value => b"000000000000"
1329 
    )
1330 
    port map (
1331 
      ce => ce_1_sg_x0,
1332 
      clk => clk_1_sg_x0,
1333 
      d => tx_en_in30_q_net,
1334 
      en => "1",
1335 
      rst => "0",
1336 
      q => bram_addr_x0
1337 
    );
1338 
 
1339 
  tx_en_in17: entity work.xlregister
1340 
    generic map (
1341 
      d_width => 12,
1342 
      init_value => b"000000000000"
1343 
    )
1344 
    port map (
1345 
      ce => ce_1_sg_x0,
1346 
      clk => clk_1_sg_x0,
1347 
      d => counter4_op_net,
1348 
      en => "1",
1349 
      rst => "0",
1350 
      q => tx_en_in17_q_net
1351 
    );
1352 
 
1353 
  tx_en_in18: entity work.xlregister
1354 
    generic map (
1355 
      d_width => 8,
1356 
      init_value => b"00000000"
1357 
    )
1358 
    port map (
1359 
      ce => ce_1_sg_x0,
1360 
      clk => clk_1_sg_x0,
1361 
      d => constant2_op_net,
1362 
      en => "1",
1363 
      rst => "0",
1364 
      q => tx_en_in18_q_net
1365 
    );
1366 
 
1367 
  tx_en_in19: entity work.xlregister
1368 
    generic map (
1369 
      d_width => 12,
1370 
      init_value => b"000000000000"
1371 
    )
1372 
    port map (
1373 
      ce => ce_1_sg_x0,
1374 
      clk => clk_1_sg_x0,
1375 
      d => bram_addr_x0,
1376 
      en => "1",
1377 
      rst => "0",
1378 
      q => bram_wr_addr_net
1379 
    );
1380 
 
1381 
  tx_en_in2: entity work.xlregister
1382 
    generic map (
1383 
      d_width => 32,
1384 
      init_value => b"00000000000000000000000000000000"
1385 
    )
1386 
    port map (
1387 
      ce => ce_1_sg_x0,
1388 
      clk => clk_1_sg_x0,
1389 
      d => dinb_x0,
1390 
      en(0) => timecountreset,
1391 
      rst(0) => constant1_op_net,
1392 
      q => data_in_net
1393 
    );
1394 
 
1395 
  tx_en_in20: entity work.xlregister
1396 
    generic map (
1397 
      d_width => 64,
1398 
      init_value => b"0000000000000000000000000000000000000000000000000000000000000000"
1399 
    )
1400 
    port map (
1401 
      ce => ce_1_sg_x0,
1402 
      clk => clk_1_sg_x0,
1403 
      d => bram_rd_dout_net,
1404 
      en => "1",
1405 
      rst => "0",
1406 
      q => bram_wr_din_net
1407 
    );
1408 
 
1409 
  tx_en_in21: entity work.xlregister
1410 
    generic map (
1411 
      d_width => 1,
1412 
      init_value => b"0"
1413 
    )
1414 
    port map (
1415 
      ce => ce_1_sg_x0,
1416 
      clk => clk_1_sg_x0,
1417 
      d(0) => fifo_empty,
1418 
      en => "1",
1419 
      rst => "0",
1420 
      q(0) => fifo_empty_x0
1421 
    );
1422 
 
1423 
  tx_en_in22: entity work.xlregister
1424 
    generic map (
1425 
      d_width => 1,
1426 
      init_value => b"0"
1427 
    )
1428 
    port map (
1429 
      ce => ce_1_sg_x0,
1430 
      clk => clk_1_sg_x0,
1431 
      d(0) => fifo_rd_en,
1432 
      en => "1",
1433 
      rst => "0",
1434 
      q(0) => fifo_rd_en_x0
1435 
    );
1436 
 
1437 
  tx_en_in23: entity work.xlregister
1438 
    generic map (
1439 
      d_width => 1,
1440 
      init_value => b"0"
1441 
    )
1442 
    port map (
1443 
      ce => ce_1_sg_x0,
1444 
      clk => clk_1_sg_x0,
1445 
      d(0) => fifo_rd_valid_net,
1446 
      en => "1",
1447 
      rst => "0",
1448 
      q(0) => fifo_wr_en
1449 
    );
1450 
 
1451 
  tx_en_in24: entity work.xlregister
1452 
    generic map (
1453 
      d_width => 72,
1454 
      init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000"
1455 
    )
1456 
    port map (
1457 
      ce => ce_1_sg_x0,
1458 
      clk => clk_1_sg_x0,
1459 
      d => fifo_rd_dout_net,
1460 
      en => "1",
1461 
      rst => "0",
1462 
      q => fifo_data_in_out
1463 
    );
1464 
 
1465 
  tx_en_in25: entity work.xlregister
1466 
    generic map (
1467 
      d_width => 1,
1468 
      init_value => b"0"
1469 
    )
1470 
    port map (
1471 
      ce => ce_1_sg_x0,
1472 
      clk => clk_1_sg_x0,
1473 
      d(0) => fifo_rd_pempty_net,
1474 
      en => "1",
1475 
      rst => "0",
1476 
      q(0) => fifo_rd_pempty
1477 
    );
1478 
 
1479 
  tx_en_in26: entity work.xlregister
1480 
    generic map (
1481 
      d_width => 1,
1482 
      init_value => b"0"
1483 
    )
1484 
    port map (
1485 
      ce => ce_1_sg_x0,
1486 
      clk => clk_1_sg_x0,
1487 
      d(0) => inverter3_op_net,
1488 
      en => "1",
1489 
      rst => "0",
1490 
      q(0) => rst_o_net
1491 
    );
1492 
 
1493 
  tx_en_in27: entity work.xlregister
1494 
    generic map (
1495 
      d_width => 15,
1496 
      init_value => b"000000000000000"
1497 
    )
1498 
    port map (
1499 
      ce => ce_1_sg_x0,
1500 
      clk => clk_1_sg_x0,
1501 
      d => fifo_rd_count_net,
1502 
      en => "1",
1503 
      rst => "0",
1504 
      q => fifo_rd_count
1505 
    );
1506 
 
1507 
  tx_en_in28: entity work.xlregister
1508 
    generic map (
1509 
      d_width => 1,
1510 
      init_value => b"0"
1511 
    )
1512 
    port map (
1513 
      ce => ce_1_sg_x0,
1514 
      clk => clk_1_sg_x0,
1515 
      d(0) => fifo_wr_full_net,
1516 
      en => "1",
1517 
      rst => "0",
1518 
      q(0) => fifo_wr_full
1519 
    );
1520 
 
1521 
  tx_en_in29: entity work.xlregister
1522 
    generic map (
1523 
      d_width => 1,
1524 
      init_value => b"0"
1525 
    )
1526 
    port map (
1527 
      ce => ce_1_sg_x0,
1528 
      clk => clk_1_sg_x0,
1529 
      d(0) => fifo_wr_pfull_net,
1530 
      en => "1",
1531 
      rst => "0",
1532 
      q(0) => fifo_wr_pfull
1533 
    );
1534 
 
1535 
  tx_en_in3: entity work.xlregister
1536 
    generic map (
1537 
      d_width => 1,
1538 
      init_value => b"0"
1539 
    )
1540 
    port map (
1541 
      ce => ce_1_sg_x0,
1542 
      clk => clk_1_sg_x0,
1543 
      d(0) => constant8_op_net,
1544 
      en => "1",
1545 
      rst => "0",
1546 
      q(0) => user_int_1o_net
1547 
    );
1548 
 
1549 
  tx_en_in30: entity work.xlregister
1550 
    generic map (
1551 
      d_width => 12,
1552 
      init_value => b"000000000000"
1553 
    )
1554 
    port map (
1555 
      ce => ce_1_sg_x0,
1556 
      clk => clk_1_sg_x0,
1557 
      d => tx_en_in17_q_net,
1558 
      en => "1",
1559 
      rst => "0",
1560 
      q => tx_en_in30_q_net
1561 
    );
1562 
 
1563 
  tx_en_in31: entity work.xlregister
1564 
    generic map (
1565 
      d_width => 15,
1566 
      init_value => b"000000000000000"
1567 
    )
1568 
    port map (
1569 
      ce => ce_1_sg_x0,
1570 
      clk => clk_1_sg_x0,
1571 
      d => fifo_wr_count_net,
1572 
      en => "1",
1573 
      rst => "0",
1574 
      q => fifo_wr_count
1575 
    );
1576 
 
1577 
  tx_en_in33: entity work.xlregister
1578 
    generic map (
1579 
      d_width => 32,
1580 
      init_value => b"00000000000000000000000000000000"
1581 
    )
1582 
    port map (
1583 
      ce => ce_1_sg_x0,
1584 
      clk => clk_1_sg_x0,
1585 
      d => tx_en_in6_q_net,
1586 
      en(0) => convert1_dout_net,
1587 
      rst(0) => constant26_op_net,
1588 
      q => data_in_x11_net
1589 
    );
1590 
 
1591 
  tx_en_in38: entity work.xlregister
1592 
    generic map (
1593 
      d_width => 72,
1594 
      init_value => b"000000000000000000000000000000000000000000000000000000000000000000000000"
1595 
    )
1596 
    port map (
1597 
      ce => ce_1_sg_x0,
1598 
      clk => clk_1_sg_x0,
1599 
      d => fifo_rd_dout_net,
1600 
      en => "1",
1601 
      rst => "0",
1602 
      q => fifo_wr_din_net
1603 
    );
1604 
 
1605 
  tx_en_in4: entity work.xlregister
1606 
    generic map (
1607 
      d_width => 1,
1608 
      init_value => b"0"
1609 
    )
1610 
    port map (
1611 
      ce => ce_1_sg_x0,
1612 
      clk => clk_1_sg_x0,
1613 
      d(0) => data_out_x27_net,
1614 
      en => "1",
1615 
      rst => "0",
1616 
      q(0) => tx_en_in4_q_net
1617 
    );
1618 
 
1619 
  tx_en_in43: entity work.xlregister
1620 
    generic map (
1621 
      d_width => 8,
1622 
      init_value => b"00000000"
1623 
    )
1624 
    port map (
1625 
      ce => ce_1_sg_x0,
1626 
      clk => clk_1_sg_x0,
1627 
      d => tx_en_in18_q_net,
1628 
      en => "1",
1629 
      rst => "0",
1630 
      q => bram_wr_en_net
1631 
    );
1632 
 
1633 
  tx_en_in5: entity work.xlregister
1634 
    generic map (
1635 
      d_width => 1,
1636 
      init_value => b"0"
1637 
    )
1638 
    port map (
1639 
      ce => ce_1_sg_x0,
1640 
      clk => clk_1_sg_x0,
1641 
      d(0) => data_out_x29_net,
1642 
      en => "1",
1643 
      rst => "0",
1644 
      q(0) => tx_en_in5_q_net
1645 
    );
1646 
 
1647 
  tx_en_in50: entity work.xlregister
1648 
    generic map (
1649 
      d_width => 32,
1650 
      init_value => b"00000000000000000000000000000000"
1651 
    )
1652 
    port map (
1653 
      ce => ce_1_sg_x0,
1654 
      clk => clk_1_sg_x0,
1655 
      d => dinb,
1656 
      en(0) => convert5_dout_net,
1657 
      rst(0) => constant25_op_net,
1658 
      q => data_in_x23_net
1659 
    );
1660 
 
1661 
  tx_en_in51: entity work.xlregister
1662 
    generic map (
1663 
      d_width => 1,
1664 
      init_value => b"0"
1665 
    )
1666 
    port map (
1667 
      ce => ce_1_sg_x0,
1668 
      clk => clk_1_sg_x0,
1669 
      d(0) => constant11_op_net,
1670 
      en => "1",
1671 
      rst => "0",
1672 
      q(0) => user_int_3o_net
1673 
    );
1674 
 
1675 
  tx_en_in52: entity work.xlregister
1676 
    generic map (
1677 
      d_width => 32,
1678 
      init_value => b"00000000000000000000000000000000"
1679 
    )
1680 
    port map (
1681 
      ce => ce_1_sg_x0,
1682 
      clk => clk_1_sg_x0,
1683 
      d => data_out_x4_net,
1684 
      en => "1",
1685 
      rst => "0",
1686 
      q => tx_en_in52_q_net
1687 
    );
1688 
 
1689 
  tx_en_in53: entity work.xlregister
1690 
    generic map (
1691 
      d_width => 32,
1692 
      init_value => b"00000000000000000000000000000000"
1693 
    )
1694 
    port map (
1695 
      ce => ce_1_sg_x0,
1696 
      clk => clk_1_sg_x0,
1697 
      d => tx_en_in60_q_net,
1698 
      en(0) => convert6_dout_net,
1699 
      rst(0) => constant24_op_net,
1700 
      q => data_in_x25_net
1701 
    );
1702 
 
1703 
  tx_en_in54: entity work.xlregister
1704 
    generic map (
1705 
      d_width => 32,
1706 
      init_value => b"00000000000000000000000000000000"
1707 
    )
1708 
    port map (
1709 
      ce => ce_1_sg_x0,
1710 
      clk => clk_1_sg_x0,
1711 
      d => tx_en_in52_q_net,
1712 
      en(0) => convert7_dout_net,
1713 
      rst(0) => constant20_op_net,
1714 
      q => data_in_x26_net
1715 
    );
1716 
 
1717 
  tx_en_in58: entity work.xlregister
1718 
    generic map (
1719 
      d_width => 1,
1720 
      init_value => b"0"
1721 
    )
1722 
    port map (
1723 
      ce => ce_1_sg_x0,
1724 
      clk => clk_1_sg_x0,
1725 
      d(0) => data_out_x1_net,
1726 
      en => "1",
1727 
      rst => "0",
1728 
      q(0) => tx_en_in58_q_net
1729 
    );
1730 
 
1731 
  tx_en_in59: entity work.xlregister
1732 
    generic map (
1733 
      d_width => 1,
1734 
      init_value => b"0"
1735 
    )
1736 
    port map (
1737 
      ce => ce_1_sg_x0,
1738 
      clk => clk_1_sg_x0,
1739 
      d(0) => data_out_x3_net,
1740 
      en => "1",
1741 
      rst => "0",
1742 
      q(0) => tx_en_in59_q_net
1743 
    );
1744 
 
1745 
  tx_en_in6: entity work.xlregister
1746 
    generic map (
1747 
      d_width => 32,
1748 
      init_value => b"00000000000000000000000000000000"
1749 
    )
1750 
    port map (
1751 
      ce => ce_1_sg_x0,
1752 
      clk => clk_1_sg_x0,
1753 
      d => data_out_x28_net,
1754 
      en => "1",
1755 
      rst => "0",
1756 
      q => tx_en_in6_q_net
1757 
    );
1758 
 
1759 
  tx_en_in60: entity work.xlregister
1760 
    generic map (
1761 
      d_width => 32,
1762 
      init_value => b"00000000000000000000000000000000"
1763 
    )
1764 
    port map (
1765 
      ce => ce_1_sg_x0,
1766 
      clk => clk_1_sg_x0,
1767 
      d => data_out_x2_net,
1768 
      en => "1",
1769 
      rst => "0",
1770 
      q => tx_en_in60_q_net
1771 
    );
1772 
 
1773 
  tx_en_in61: entity work.xlregister
1774 
    generic map (
1775 
      d_width => 1,
1776 
      init_value => b"0"
1777 
    )
1778 
    port map (
1779 
      ce => ce_1_sg_x0,
1780 
      clk => clk_1_sg_x0,
1781 
      d(0) => data_out_x5_net,
1782 
      en => "1",
1783 
      rst => "0",
1784 
      q(0) => tx_en_in61_q_net
1785 
    );
1786 
 
1787 
  tx_en_in62: entity work.xlregister
1788 
    generic map (
1789 
      d_width => 32,
1790 
      init_value => b"00000000000000000000000000000000"
1791 
    )
1792 
    port map (
1793 
      ce => ce_1_sg_x0,
1794 
      clk => clk_1_sg_x0,
1795 
      d => data_out_x32_net,
1796 
      en => "1",
1797 
      rst => "0",
1798 
      q => dinb
1799 
    );
1800 
 
1801 
  tx_en_in65: entity work.xlregister
1802 
    generic map (
1803 
      d_width => 32,
1804 
      init_value => b"00000000000000000000000000000000"
1805 
    )
1806 
    port map (
1807 
      ce => ce_1_sg_x0,
1808 
      clk => clk_1_sg_x0,
1809 
      d => data_out_x8_net,
1810 
      en => "1",
1811 
      rst => "0",
1812 
      q => tx_en_in65_q_net
1813 
    );
1814 
 
1815 
  tx_en_in66: entity work.xlregister
1816 
    generic map (
1817 
      d_width => 32,
1818 
      init_value => b"00000000000000000000000000000000"
1819 
    )
1820 
    port map (
1821 
      ce => ce_1_sg_x0,
1822 
      clk => clk_1_sg_x0,
1823 
      d => tx_en_in65_q_net,
1824 
      en(0) => convert8_dout_net,
1825 
      rst(0) => constant12_op_net,
1826 
      q => data_in_x4_net
1827 
    );
1828 
 
1829 
  tx_en_in67: entity work.xlregister
1830 
    generic map (
1831 
      d_width => 1,
1832 
      init_value => b"0"
1833 
    )
1834 
    port map (
1835 
      ce => ce_1_sg_x0,
1836 
      clk => clk_1_sg_x0,
1837 
      d(0) => data_out_x9_net,
1838 
      en => "1",
1839 
      rst => "0",
1840 
      q(0) => tx_en_in67_q_net
1841 
    );
1842 
 
1843 
  tx_en_in7: entity work.xlregister
1844 
    generic map (
1845 
      d_width => 1,
1846 
      init_value => b"0"
1847 
    )
1848 
    port map (
1849 
      ce => ce_1_sg_x0,
1850 
      clk => clk_1_sg_x0,
1851 
      d(0) => timecounttrigger,
1852 
      en => "1",
1853 
      rst => "0",
1854 
      q(0) => data_in_x22_net
1855 
    );
1856 
 
1857 
  tx_en_in75: entity work.xlregister
1858 
    generic map (
1859 
      d_width => 1,
1860 
      init_value => b"0"
1861 
    )
1862 
    port map (
1863 
      ce => ce_1_sg_x0,
1864 
      clk => clk_1_sg_x0,
1865 
      d(0) => constant10_op_net,
1866 
      en => "1",
1867 
      rst => "0",
1868 
      q(0) => user_int_2o_net
1869 
    );
1870 
 
1871 
  tx_en_in8: entity work.xlregister
1872 
    generic map (
1873 
      d_width => 1,
1874 
      init_value => b"0"
1875 
    )
1876 
    port map (
1877 
      ce => ce_1_sg_x0,
1878 
      clk => clk_1_sg_x0,
1879 
      d(0) => data_out_x31_net,
1880 
      en => "1",
1881 
      rst => "0",
1882 
      q(0) => tx_en_in8_q_net
1883 
    );
1884 
 
1885 
  tx_en_in85: entity work.xlregister
1886 
    generic map (
1887 
      d_width => 32,
1888 
      init_value => b"00000000000000000000000000000001"
1889 
    )
1890 
    port map (
1891 
      ce => ce_1_sg_x0,
1892 
      clk => clk_1_sg_x0,
1893 
      d => tx_en_in87_q_net,
1894 
      en(0) => convert4_dout_net,
1895 
      rst(0) => constant7_op_net,
1896 
      q => data_in_x6_net
1897 
    );
1898 
 
1899 
  tx_en_in86: entity work.xlregister
1900 
    generic map (
1901 
      d_width => 1,
1902 
      init_value => b"0"
1903 
    )
1904 
    port map (
1905 
      ce => ce_1_sg_x0,
1906 
      clk => clk_1_sg_x0,
1907 
      d(0) => data_out_x13_net,
1908 
      en => "1",
1909 
      rst => "0",
1910 
      q(0) => tx_en_in86_q_net
1911 
    );
1912 
 
1913 
  tx_en_in87: entity work.xlregister
1914 
    generic map (
1915 
      d_width => 32,
1916 
      init_value => b"00000000000000000000000000000000"
1917 
    )
1918 
    port map (
1919 
      ce => ce_1_sg_x0,
1920 
      clk => clk_1_sg_x0,
1921 
      d => data_out_x12_net,
1922 
      en => "1",
1923 
      rst => "0",
1924 
      q => tx_en_in87_q_net
1925 
    );
1926 
 
1927 
  tx_en_in88: entity work.xlregister
1928 
    generic map (
1929 
      d_width => 32,
1930 
      init_value => b"10000000000000000000000000000000"
1931 
    )
1932 
    port map (
1933 
      ce => ce_1_sg_x0,
1934 
      clk => clk_1_sg_x0,
1935 
      d => tx_en_in90_q_net,
1936 
      en(0) => convert11_dout_net,
1937 
      rst(0) => constant4_op_net,
1938 
      q => data_in_x8_net
1939 
    );
1940 
 
1941 
  tx_en_in89: entity work.xlregister
1942 
    generic map (
1943 
      d_width => 1,
1944 
      init_value => b"0"
1945 
    )
1946 
    port map (
1947 
      ce => ce_1_sg_x0,
1948 
      clk => clk_1_sg_x0,
1949 
      d(0) => data_out_x15_net,
1950 
      en => "1",
1951 
      rst => "0",
1952 
      q(0) => tx_en_in89_q_net
1953 
    );
1954 
 
1955 
  tx_en_in9: entity work.xlregister
1956 
    generic map (
1957 
      d_width => 32,
1958 
      init_value => b"00000000000000000000000000000000"
1959 
    )
1960 
    port map (
1961 
      ce => ce_1_sg_x0,
1962 
      clk => clk_1_sg_x0,
1963 
      d => data_out_x22_net,
1964 
      en => "1",
1965 
      rst => "0",
1966 
      q => dinb_x0
1967 
    );
1968 
 
1969 
  tx_en_in90: entity work.xlregister
1970 
    generic map (
1971 
      d_width => 32,
1972 
      init_value => b"00000000000000000000000000000000"
1973 
    )
1974 
    port map (
1975 
      ce => ce_1_sg_x0,
1976 
      clk => clk_1_sg_x0,
1977 
      d => data_out_x14_net,
1978 
      en => "1",
1979 
      rst => "0",
1980 
      q => tx_en_in90_q_net
1981 
    );
1982 
 
1983 
  tx_en_in91: entity work.xlregister
1984 
    generic map (
1985 
      d_width => 32,
1986 
      init_value => b"00000000000000000000000000000000"
1987 
    )
1988 
    port map (
1989 
      ce => ce_1_sg_x0,
1990 
      clk => clk_1_sg_x0,
1991 
      d => tx_en_in93_q_net,
1992 
      en(0) => convert12_dout_net,
1993 
      rst(0) => constant9_op_net,
1994 
      q => data_in_x10_net
1995 
    );
1996 
 
1997 
  tx_en_in92: entity work.xlregister
1998 
    generic map (
1999 
      d_width => 1,
2000 
      init_value => b"0"
2001 
    )
2002 
    port map (
2003 
      ce => ce_1_sg_x0,
2004 
      clk => clk_1_sg_x0,
2005 
      d(0) => data_out_x17_net,
2006 
      en => "1",
2007 
      rst => "0",
2008 
      q(0) => tx_en_in92_q_net
2009 
    );
2010 
 
2011 
  tx_en_in93: entity work.xlregister
2012 
    generic map (
2013 
      d_width => 32,
2014 
      init_value => b"00000000000000000000000000000000"
2015 
    )
2016 
    port map (
2017 
      ce => ce_1_sg_x0,
2018 
      clk => clk_1_sg_x0,
2019 
      d => data_out_x16_net,
2020 
      en => "1",
2021 
      rst => "0",
2022 
      q => tx_en_in93_q_net
2023 
    );
2024 
 
2025 
  tx_en_in94: entity work.xlregister
2026 
    generic map (
2027 
      d_width => 1,
2028 
      init_value => b"0"
2029 
    )
2030 
    port map (
2031 
      ce => ce_1_sg_x0,
2032 
      clk => clk_1_sg_x0,
2033 
      d(0) => convert1_dout_net,
2034 
      en => "1",
2035 
      rst => "0",
2036 
      q(0) => data_in_x21_net
2037 
    );
2038 
 
2039 
  tx_en_in95: entity work.xlregister
2040 
    generic map (
2041 
      d_width => 1,
2042 
      init_value => b"0"
2043 
    )
2044 
    port map (
2045 
      ce => ce_1_sg_x0,
2046 
      clk => clk_1_sg_x0,
2047 
      d(0) => convert5_dout_net,
2048 
      en => "1",
2049 
      rst => "0",
2050 
      q(0) => data_in_x24_net
2051 
    );
2052 
 
2053 
  tx_en_in96: entity work.xlregister
2054 
    generic map (
2055 
      d_width => 1,
2056 
      init_value => b"0"
2057 
    )
2058 
    port map (
2059 
      ce => ce_1_sg_x0,
2060 
      clk => clk_1_sg_x0,
2061 
      d(0) => convert6_dout_net,
2062 
      en => "1",
2063 
      rst => "0",
2064 
      q(0) => data_in_x1_net
2065 
    );
2066 
 
2067 
  tx_en_in97: entity work.xlregister
2068 
    generic map (
2069 
      d_width => 1,
2070 
      init_value => b"0"
2071 
    )
2072 
    port map (
2073 
      ce => ce_1_sg_x0,
2074 
      clk => clk_1_sg_x0,
2075 
      d(0) => convert7_dout_net,
2076 
      en => "1",
2077 
      rst => "0",
2078 
      q(0) => data_in_x2_net
2079 
    );
2080 
 
2081 
  tx_en_in98: entity work.xlregister
2082 
    generic map (
2083 
      d_width => 1,
2084 
      init_value => b"0"
2085 
    )
2086 
    port map (
2087 
      ce => ce_1_sg_x0,
2088 
      clk => clk_1_sg_x0,
2089 
      d(0) => convert4_dout_net,
2090 
      en => "1",
2091 
      rst => "0",
2092 
      q(0) => data_in_x5_net
2093 
    );
2094 
 
2095 
  tx_en_in99: entity work.xlregister
2096 
    generic map (
2097 
      d_width => 1,
2098 
      init_value => b"0"
2099 
    )
2100 
    port map (
2101 
      ce => ce_1_sg_x0,
2102 
      clk => clk_1_sg_x0,
2103 
      d(0) => convert11_dout_net,
2104 
      en => "1",
2105 
      rst => "0",
2106 
      q(0) => data_in_x7_net
2107 
    );
2108 
 
2109 
end structural;

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