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-------------------------------------------------------------------

-- System Generator version 13.2 VHDL source file.

--

-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This

-- text/file contains proprietary, confidential information of Xilinx,

-- Inc., is distributed under license from Xilinx, Inc., and may be used,

-- copied and/or disclosed only pursuant to the terms of a valid license

-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use

-- this text/file solely for design, simulation, implementation and

-- creation of design files limited to Xilinx devices or technologies.

-- Use with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license unless covered by a separate

-- agreement.

--

-- Xilinx is providing this design, code, or information "as is" solely

-- for use in developing programs and solutions for Xilinx devices.  By

-- providing this design, code, or information as one possible

-- implementation of this feature, application or standard, Xilinx is

-- making no representation that this implementation is free from any

-- claims of infringement.  You are responsible for obtaining any rights

-- you may require for your implementation.  Xilinx expressly disclaims

-- any warranty whatsoever with respect to the adequacy of the

-- implementation, including but not limited to warranties of

-- merchantability or fitness for a particular purpose.

--

-- Xilinx products are not intended for use in life support appliances,

-- devices, or systems.  Use in such applications is expressly prohibited.

--

-- Any modifications that are made to the source code are done at the user's

-- sole risk and will be unsupported.

--

-- This copyright and support notice must be retained as part of this

-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights

-- reserved.

-------------------------------------------------------------------

-------------------------------------------------------------------

-- System Generator version 13.2 VHDL source file.

--

-- Copyright(C) 2011 by Xilinx, Inc.  All rights reserved.  This

-- text/file contains proprietary, confidential information of Xilinx,

-- Inc., is distributed under license from Xilinx, Inc., and may be used,

-- copied and/or disclosed only pursuant to the terms of a valid license

-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use

-- this text/file solely for design, simulation, implementation and

-- creation of design files limited to Xilinx devices or technologies.

-- Use with non-Xilinx devices or technologies is expressly prohibited

-- and immediately terminates your license unless covered by a separate

-- agreement.

--

-- Xilinx is providing this design, code, or information "as is" solely

-- for use in developing programs and solutions for Xilinx devices.  By

-- providing this design, code, or information as one possible

-- implementation of this feature, application or standard, Xilinx is

-- making no representation that this implementation is free from any

-- claims of infringement.  You are responsible for obtaining any rights

-- you may require for your implementation.  Xilinx expressly disclaims

-- any warranty whatsoever with respect to the adequacy of the

-- implementation, including but not limited to warranties of

-- merchantability or fitness for a particular purpose.

--

-- Xilinx products are not intended for use in life support appliances,

-- devices, or systems.  Use in such applications is expressly prohibited.

--

-- Any modifications that are made to the source code are done at the user's

-- sole risk and will be unsupported.

--

-- This copyright and support notice must be retained as part of this

-- text at all times.  (c) Copyright 1995-2011 Xilinx, Inc.  All rights

-- reserved.

-------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use work.conv_pkg.all;

-- synopsys translate_off

library unisim;

use unisim.vcomponents.all;

-- synopsys translate_on

entity xlclockdriver is

  generic (

    period: integer := 2;

    log_2_period: integer := 0;

    pipeline_regs: integer := 5;

    use_bufg: integer := 0

  );

  port (

    sysclk: in std_logic;

    sysclr: in std_logic;

    sysce: in std_logic;

    clk: out std_logic;

    clr: out std_logic;

    ce: out std_logic;

    ce_logic: out std_logic

  );

end xlclockdriver;

architecture behavior of xlclockdriver is

  component bufg

    port (

      i: in std_logic;

      o: out std_logic

    );

  end component;

  component synth_reg_w_init

    generic (

      width: integer;

      init_index: integer;

      init_value: bit_vector;

      latency: integer

    );

    port (

      i: in std_logic_vector(width - 1 downto 0);

      ce: in std_logic;

      clr: in std_logic;

      clk: in std_logic;

      o: out std_logic_vector(width - 1 downto 0)

    );

  end component;

  function size_of_uint(inp: integer; power_of_2: boolean)

    return integer

  is

    constant inp_vec: std_logic_vector(31 downto 0) :=

      integer_to_std_logic_vector(inp,32, xlUnsigned);

    variable result: integer;

  begin

    result := 32;

    for i in 0 to 31 loop

      if inp_vec(i) = '1' then

        result := i;

      end if;

    end loop;

    if power_of_2 then

      return result;

    else

      return result+1;

    end if;

  end;

  function is_power_of_2(inp: std_logic_vector)

    return boolean

  is

    constant width: integer := inp'length;

    variable vec: std_logic_vector(width - 1 downto 0);

    variable single_bit_set: boolean;

    variable more_than_one_bit_set: boolean;

    variable result: boolean;

  begin

    vec := inp;

    single_bit_set := false;

    more_than_one_bit_set := false;

    -- synopsys translate_off

    if (is_XorU(vec)) then

      return false;

    end if;

     -- synopsys translate_on

    if width > 0 then

      for i in 0 to width - 1 loop

        if vec(i) = '1' then

          if single_bit_set then

            more_than_one_bit_set := true;

          end if;

          single_bit_set := true;

        end if;

      end loop;

    end if;

    if (single_bit_set and not(more_than_one_bit_set)) then

      result := true;

    else

      result := false;

    end if;

    return result;

  end;

  function ce_reg_init_val(index, period : integer)

    return integer

  is

     variable result: integer;

   begin

      result := 0;

      if ((index mod period) = 0) then

          result := 1;

      end if;

      return result;

  end;

  function remaining_pipe_regs(num_pipeline_regs, period : integer)

    return integer

  is

     variable factor, result: integer;

  begin

      factor := (num_pipeline_regs / period);

      result := num_pipeline_regs - (period * factor) + 1;

      return result;

  end;

  function sg_min(L, R: INTEGER) return INTEGER is

  begin

      if L < R then

            return L;

      else

            return R;

      end if;

  end;

  constant max_pipeline_regs : integer := 8;

  constant pipe_regs : integer := 5;

  constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);

  constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);

  constant period_floor: integer := max(2, period);

  constant power_of_2_counter: boolean :=

    is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));

  constant cnt_width: integer :=

    size_of_uint(period_floor, power_of_2_counter);

  constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=

    integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);

  constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=

    integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);

  constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=

    integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);

  signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');

  signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);

  attribute MAX_FANOUT : string;

  attribute MAX_FANOUT of ce_vec:signal is "REDUCE";

  signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);

  attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";

  signal internal_ce: std_logic_vector(0 downto 0);

  signal internal_ce_logic: std_logic_vector(0 downto 0);

  signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);

begin

  clk <= sysclk;

  clr <= sysclr;

  cntr_gen: process(sysclk)

  begin

    if sysclk'event and sysclk = '1'  then

      if (sysce = '1') then

        if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then

          clk_num <= (others => '0');

        else

          clk_num <= clk_num + 1;

        end if;

    end if;

    end if;

  end process;

  clr_gen: process(clk_num, sysclr)

  begin

    if power_of_2_counter then

      cnt_clr(0) <= sysclr;

    else

      if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1

          or sysclr = '1') then

        cnt_clr(0) <= '1';

      else

        cnt_clr(0) <= '0';

      end if;

    end if;

  end process;

  clr_reg: synth_reg_w_init

    generic map (

      width => 1,

      init_index => 0,

      init_value => b"0000",

      latency => 1

    )

    port map (

      i => cnt_clr,

      ce => sysce,

      clr => sysclr,

      clk => sysclk,

      o => cnt_clr_dly

    );

  pipelined_ce : if period > 1 generate

      ce_gen: process(clk_num)

      begin

          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then

              ce_vec(num_pipeline_regs) <= '1';

          else

              ce_vec(num_pipeline_regs) <= '0';

          end if;

      end process;

      ce_pipeline: for index in num_pipeline_regs downto 1 generate

          ce_reg : synth_reg_w_init

              generic map (

                  width => 1,

                  init_index => ce_reg_init_val(index, period),

                  init_value => b"0000",

                  latency => 1

                  )

              port map (

                  i => ce_vec(index downto index),

                  ce => sysce,

                  clr => sysclr,

                  clk => sysclk,

                  o => ce_vec(index-1 downto index-1)

                  );

      end generate;

      internal_ce <= ce_vec(0 downto 0);

  end generate;

  pipelined_ce_logic: if period > 1 generate

      ce_gen_logic: process(clk_num)

      begin

          if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then

              ce_vec_logic(num_pipeline_regs) <= '1';

          else

              ce_vec_logic(num_pipeline_regs) <= '0';

          end if;

      end process;

      ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate

          ce_logic_reg : synth_reg_w_init

              generic map (

                  width => 1,

                  init_index => ce_reg_init_val(index, period),

                  init_value => b"0000",

                  latency => 1

                  )

              port map (

                  i => ce_vec_logic(index downto index),

                  ce => sysce,

                  clr => sysclr,

                  clk => sysclk,

                  o => ce_vec_logic(index-1 downto index-1)

                  );

      end generate;

      internal_ce_logic <= ce_vec_logic(0 downto 0);

  end generate;

  use_bufg_true: if period > 1 and use_bufg = 1 generate

    ce_bufg_inst: bufg

      port map (

        i => internal_ce(0),

        o => ce

      );

    ce_bufg_inst_logic: bufg

      port map (

        i => internal_ce_logic(0),

        o => ce_logic

      );

  end generate;

  use_bufg_false: if period > 1 and (use_bufg = 0) generate

    ce <= internal_ce(0);

    ce_logic <= internal_ce_logic(0);

  end generate;

  generate_system_clk: if period = 1 generate

    ce <= sysce;

    ce_logic <= sysce;

  end generate;

end architecture behavior;

library IEEE;

use IEEE.std_logic_1164.all;

use work.conv_pkg.all;

entity default_clock_driver is

  port (

    sysce: in std_logic;

    sysce_clr: in std_logic;

    sysclk: in std_logic;

    ce_1: out std_logic;

    clk_1: out std_logic

  );

end default_clock_driver;

architecture structural of default_clock_driver is

  attribute syn_noprune: boolean;

  attribute syn_noprune of structural : architecture is true;

  attribute optimize_primitives: boolean;

  attribute optimize_primitives of structural : architecture is false;

  attribute dont_touch: boolean;

  attribute dont_touch of structural : architecture is true;

  signal sysce_clr_x0: std_logic;

  signal sysce_x0: std_logic;

  signal sysclk_x0: std_logic;

  signal xlclockdriver_1_ce: std_logic;

  signal xlclockdriver_1_clk: std_logic;

begin

  sysce_x0 <= sysce;

  sysce_clr_x0 <= sysce_clr;

  sysclk_x0 <= sysclk;

  ce_1 <= xlclockdriver_1_ce;

  clk_1 <= xlclockdriver_1_clk;

  xlclockdriver_1: entity work.xlclockdriver

    generic map (

      log_2_period => 1,

      period => 1,

      use_bufg => 0

    )

    port map (

      sysce => sysce_x0,

      sysclk => sysclk_x0,

      sysclr => sysce_clr_x0,

      ce => xlclockdriver_1_ce,

      clk => xlclockdriver_1_clk

    );

end structural;

library IEEE;

use IEEE.std_logic_1164.all;

use work.conv_pkg.all;

entity user_logic_cw is

  port (

    bram_rd_dout: in std_logic_vector(63 downto 0);

    ce: in std_logic := '1';

    clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    fifo_rd_count: in std_logic_vector(14 downto 0);

    fifo_rd_dout: in std_logic_vector(71 downto 0);

    fifo_rd_empty: in std_logic;

    fifo_rd_pempty: in std_logic;

    fifo_rd_valid: in std_logic;

    fifo_wr_count: in std_logic_vector(14 downto 0);

    fifo_wr_full: in std_logic;

    fifo_wr_pfull: in std_logic;

    from_register10_data_out: in std_logic_vector(0 downto 0);

    from_register11_data_out: in std_logic_vector(31 downto 0);

    from_register12_data_out: in std_logic_vector(0 downto 0);

    from_register13_data_out: in std_logic_vector(31 downto 0);

    from_register14_data_out: in std_logic_vector(0 downto 0);

    from_register15_data_out: in std_logic_vector(0 downto 0);

    from_register16_data_out: in std_logic_vector(0 downto 0);

    from_register17_data_out: in std_logic_vector(31 downto 0);

    from_register18_data_out: in std_logic_vector(0 downto 0);

    from_register19_data_out: in std_logic_vector(31 downto 0);

    from_register1_data_out: in std_logic_vector(31 downto 0);

    from_register20_data_out: in std_logic_vector(31 downto 0);

    from_register21_data_out: in std_logic_vector(0 downto 0);

    from_register22_data_out: in std_logic_vector(31 downto 0);

    from_register23_data_out: in std_logic_vector(0 downto 0);

    from_register24_data_out: in std_logic_vector(31 downto 0);

    from_register25_data_out: in std_logic_vector(0 downto 0);

    from_register26_data_out: in std_logic_vector(31 downto 0);

    from_register27_data_out: in std_logic_vector(0 downto 0);

    from_register28_data_out: in std_logic_vector(31 downto 0);

    from_register29_data_out: in std_logic_vector(0 downto 0);

    from_register2_data_out: in std_logic_vector(31 downto 0);

    from_register30_data_out: in std_logic_vector(31 downto 0);

    from_register31_data_out: in std_logic_vector(0 downto 0);

    from_register32_data_out: in std_logic_vector(31 downto 0);

    from_register33_data_out: in std_logic_vector(0 downto 0);

    from_register3_data_out: in std_logic_vector(31 downto 0);

    from_register4_data_out: in std_logic_vector(0 downto 0);

    from_register5_data_out: in std_logic_vector(31 downto 0);

    from_register6_data_out: in std_logic_vector(0 downto 0);

    from_register7_data_out: in std_logic_vector(31 downto 0);

    from_register8_data_out: in std_logic_vector(0 downto 0);

    from_register9_data_out: in std_logic_vector(31 downto 0);

    from_register_data_out: in std_logic_vector(31 downto 0);

    rst_i: in std_logic;

    to_register10_dout: in std_logic_vector(0 downto 0);

    to_register11_dout: in std_logic_vector(0 downto 0);

    to_register12_dout: in std_logic_vector(0 downto 0);

    to_register13_dout: in std_logic_vector(31 downto 0);

    to_register14_dout: in std_logic_vector(0 downto 0);

    to_register15_dout: in std_logic_vector(31 downto 0);

    to_register16_dout: in std_logic_vector(0 downto 0);

    to_register17_dout: in std_logic_vector(31 downto 0);

    to_register18_dout: in std_logic_vector(0 downto 0);

    to_register19_dout: in std_logic_vector(31 downto 0);

    to_register1_dout: in std_logic_vector(0 downto 0);

    to_register20_dout: in std_logic_vector(0 downto 0);

    to_register21_dout: in std_logic_vector(31 downto 0);

    to_register22_dout: in std_logic_vector(0 downto 0);

    to_register23_dout: in std_logic_vector(31 downto 0);

    to_register24_dout: in std_logic_vector(0 downto 0);

    to_register25_dout: in std_logic_vector(31 downto 0);

    to_register26_dout: in std_logic_vector(0 downto 0);

    to_register27_dout: in std_logic_vector(31 downto 0);

    to_register2_dout: in std_logic_vector(31 downto 0);

    to_register3_dout: in std_logic_vector(31 downto 0);

    to_register4_dout: in std_logic_vector(0 downto 0);

    to_register5_dout: in std_logic_vector(0 downto 0);

    to_register6_dout: in std_logic_vector(31 downto 0);

    to_register7_dout: in std_logic_vector(0 downto 0);

    to_register8_dout: in std_logic_vector(31 downto 0);

    to_register9_dout: in std_logic_vector(31 downto 0);

    to_register_dout: in std_logic_vector(31 downto 0);

    bram_rd_addr: out std_logic_vector(11 downto 0);

    bram_wr_addr: out std_logic_vector(11 downto 0);

    bram_wr_din: out std_logic_vector(63 downto 0);

    bram_wr_en: out std_logic_vector(7 downto 0);

    fifo_rd_en: out std_logic;

    fifo_wr_din: out std_logic_vector(71 downto 0);

    fifo_wr_en: out std_logic;

    rst_o: out std_logic;

    to_register10_ce: out std_logic;

    to_register10_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register10_clr: out std_logic;

    to_register10_data_in: out std_logic_vector(0 downto 0);

    to_register10_en: out std_logic_vector(0 downto 0);

    to_register11_ce: out std_logic;

    to_register11_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register11_clr: out std_logic;

    to_register11_data_in: out std_logic_vector(0 downto 0);

    to_register11_en: out std_logic_vector(0 downto 0);

    to_register12_ce: out std_logic;

    to_register12_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register12_clr: out std_logic;

    to_register12_data_in: out std_logic_vector(0 downto 0);

    to_register12_en: out std_logic_vector(0 downto 0);

    to_register13_ce: out std_logic;

    to_register13_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register13_clr: out std_logic;

    to_register13_data_in: out std_logic_vector(31 downto 0);

    to_register13_en: out std_logic_vector(0 downto 0);

    to_register14_ce: out std_logic;

    to_register14_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register14_clr: out std_logic;

    to_register14_data_in: out std_logic_vector(0 downto 0);

    to_register14_en: out std_logic_vector(0 downto 0);

    to_register15_ce: out std_logic;

    to_register15_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register15_clr: out std_logic;

    to_register15_data_in: out std_logic_vector(31 downto 0);

    to_register15_en: out std_logic_vector(0 downto 0);

    to_register16_ce: out std_logic;

    to_register16_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register16_clr: out std_logic;

    to_register16_data_in: out std_logic_vector(0 downto 0);

    to_register16_en: out std_logic_vector(0 downto 0);

    to_register17_ce: out std_logic;

    to_register17_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register17_clr: out std_logic;

    to_register17_data_in: out std_logic_vector(31 downto 0);

    to_register17_en: out std_logic_vector(0 downto 0);

    to_register18_ce: out std_logic;

    to_register18_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register18_clr: out std_logic;

    to_register18_data_in: out std_logic_vector(0 downto 0);

    to_register18_en: out std_logic_vector(0 downto 0);

    to_register19_ce: out std_logic;

    to_register19_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register19_clr: out std_logic;

    to_register19_data_in: out std_logic_vector(31 downto 0);

    to_register19_en: out std_logic_vector(0 downto 0);

    to_register1_ce: out std_logic;

    to_register1_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register1_clr: out std_logic;

    to_register1_data_in: out std_logic_vector(0 downto 0);

    to_register1_en: out std_logic_vector(0 downto 0);

    to_register20_ce: out std_logic;

    to_register20_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register20_clr: out std_logic;

    to_register20_data_in: out std_logic_vector(0 downto 0);

    to_register20_en: out std_logic_vector(0 downto 0);

    to_register21_ce: out std_logic;

    to_register21_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register21_clr: out std_logic;

    to_register21_data_in: out std_logic_vector(31 downto 0);

    to_register21_en: out std_logic_vector(0 downto 0);

    to_register22_ce: out std_logic;

    to_register22_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register22_clr: out std_logic;

    to_register22_data_in: out std_logic_vector(0 downto 0);

    to_register22_en: out std_logic_vector(0 downto 0);

    to_register23_ce: out std_logic;

    to_register23_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register23_clr: out std_logic;

    to_register23_data_in: out std_logic_vector(31 downto 0);

    to_register23_en: out std_logic_vector(0 downto 0);

    to_register24_ce: out std_logic;

    to_register24_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register24_clr: out std_logic;

    to_register24_data_in: out std_logic_vector(0 downto 0);

    to_register24_en: out std_logic_vector(0 downto 0);

    to_register25_ce: out std_logic;

    to_register25_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register25_clr: out std_logic;

    to_register25_data_in: out std_logic_vector(31 downto 0);

    to_register25_en: out std_logic_vector(0 downto 0);

    to_register26_ce: out std_logic;

    to_register26_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register26_clr: out std_logic;

    to_register26_data_in: out std_logic_vector(0 downto 0);

    to_register26_en: out std_logic_vector(0 downto 0);

    to_register27_ce: out std_logic;

    to_register27_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register27_clr: out std_logic;

    to_register27_data_in: out std_logic_vector(31 downto 0);

    to_register27_en: out std_logic_vector(0 downto 0);

    to_register2_ce: out std_logic;

    to_register2_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register2_clr: out std_logic;

    to_register2_data_in: out std_logic_vector(31 downto 0);

    to_register2_en: out std_logic_vector(0 downto 0);

    to_register3_ce: out std_logic;

    to_register3_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)

    to_register3_clr: out std_logic;

    to_register3_data_in: out std_logic_vector(31 downto 0);