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barabba |
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-------------------------------------------------------------------
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-- System Generator version 13.2 VHDL source file.
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--
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-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
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-- text/file contains proprietary, confidential information of Xilinx,
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-- Inc., is distributed under license from Xilinx, Inc., and may be used,
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-- copied and/or disclosed only pursuant to the terms of a valid license
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-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
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-- this text/file solely for design, simulation, implementation and
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-- creation of design files limited to Xilinx devices or technologies.
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-- Use with non-Xilinx devices or technologies is expressly prohibited
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-- and immediately terminates your license unless covered by a separate
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-- agreement.
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--
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-- Xilinx is providing this design, code, or information "as is" solely
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-- for use in developing programs and solutions for Xilinx devices. By
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-- providing this design, code, or information as one possible
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-- implementation of this feature, application or standard, Xilinx is
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-- making no representation that this implementation is free from any
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-- claims of infringement. You are responsible for obtaining any rights
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-- you may require for your implementation. Xilinx expressly disclaims
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-- any warranty whatsoever with respect to the adequacy of the
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-- implementation, including but not limited to warranties of
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-- merchantability or fitness for a particular purpose.
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--
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-- Xilinx products are not intended for use in life support appliances,
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-- devices, or systems. Use in such applications is expressly prohibited.
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--
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-- Any modifications that are made to the source code are done at the user's
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-- sole risk and will be unsupported.
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--
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-- This copyright and support notice must be retained as part of this
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-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
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-- reserved.
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-------------------------------------------------------------------
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-- The following code must appear in the VHDL architecture header:
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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component user_logic_cw port (
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bram_rd_dout: in std_logic_vector(63 downto 0);
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ce: in std_logic := '1';
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clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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fifo_rd_count: in std_logic_vector(14 downto 0);
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fifo_rd_dout: in std_logic_vector(71 downto 0);
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fifo_rd_empty: in std_logic;
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fifo_rd_pempty: in std_logic;
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fifo_rd_valid: in std_logic;
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fifo_wr_count: in std_logic_vector(14 downto 0);
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fifo_wr_full: in std_logic;
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fifo_wr_pfull: in std_logic;
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from_register10_data_out: in std_logic_vector(0 downto 0);
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from_register11_data_out: in std_logic_vector(31 downto 0);
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from_register12_data_out: in std_logic_vector(0 downto 0);
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from_register13_data_out: in std_logic_vector(31 downto 0);
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from_register14_data_out: in std_logic_vector(0 downto 0);
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from_register15_data_out: in std_logic_vector(0 downto 0);
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from_register16_data_out: in std_logic_vector(0 downto 0);
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from_register17_data_out: in std_logic_vector(31 downto 0);
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from_register18_data_out: in std_logic_vector(0 downto 0);
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from_register19_data_out: in std_logic_vector(31 downto 0);
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from_register1_data_out: in std_logic_vector(31 downto 0);
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from_register20_data_out: in std_logic_vector(31 downto 0);
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from_register21_data_out: in std_logic_vector(0 downto 0);
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from_register22_data_out: in std_logic_vector(31 downto 0);
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from_register23_data_out: in std_logic_vector(0 downto 0);
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from_register24_data_out: in std_logic_vector(31 downto 0);
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from_register25_data_out: in std_logic_vector(0 downto 0);
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from_register26_data_out: in std_logic_vector(31 downto 0);
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from_register27_data_out: in std_logic_vector(0 downto 0);
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from_register28_data_out: in std_logic_vector(31 downto 0);
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from_register29_data_out: in std_logic_vector(0 downto 0);
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from_register2_data_out: in std_logic_vector(31 downto 0);
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from_register30_data_out: in std_logic_vector(31 downto 0);
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from_register31_data_out: in std_logic_vector(0 downto 0);
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from_register32_data_out: in std_logic_vector(31 downto 0);
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from_register33_data_out: in std_logic_vector(0 downto 0);
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from_register3_data_out: in std_logic_vector(31 downto 0);
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from_register4_data_out: in std_logic_vector(0 downto 0);
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from_register5_data_out: in std_logic_vector(31 downto 0);
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from_register6_data_out: in std_logic_vector(0 downto 0);
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from_register7_data_out: in std_logic_vector(31 downto 0);
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from_register8_data_out: in std_logic_vector(0 downto 0);
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from_register9_data_out: in std_logic_vector(31 downto 0);
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from_register_data_out: in std_logic_vector(31 downto 0);
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rst_i: in std_logic;
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to_register10_dout: in std_logic_vector(0 downto 0);
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to_register11_dout: in std_logic_vector(0 downto 0);
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to_register12_dout: in std_logic_vector(0 downto 0);
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to_register13_dout: in std_logic_vector(31 downto 0);
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to_register14_dout: in std_logic_vector(0 downto 0);
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to_register15_dout: in std_logic_vector(31 downto 0);
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to_register16_dout: in std_logic_vector(0 downto 0);
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to_register17_dout: in std_logic_vector(31 downto 0);
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to_register18_dout: in std_logic_vector(0 downto 0);
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to_register19_dout: in std_logic_vector(31 downto 0);
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to_register1_dout: in std_logic_vector(0 downto 0);
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to_register20_dout: in std_logic_vector(0 downto 0);
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to_register21_dout: in std_logic_vector(31 downto 0);
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to_register22_dout: in std_logic_vector(0 downto 0);
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to_register23_dout: in std_logic_vector(31 downto 0);
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to_register24_dout: in std_logic_vector(0 downto 0);
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to_register25_dout: in std_logic_vector(31 downto 0);
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to_register26_dout: in std_logic_vector(0 downto 0);
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to_register27_dout: in std_logic_vector(31 downto 0);
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to_register2_dout: in std_logic_vector(31 downto 0);
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to_register3_dout: in std_logic_vector(31 downto 0);
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to_register4_dout: in std_logic_vector(0 downto 0);
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to_register5_dout: in std_logic_vector(0 downto 0);
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to_register6_dout: in std_logic_vector(31 downto 0);
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to_register7_dout: in std_logic_vector(0 downto 0);
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to_register8_dout: in std_logic_vector(31 downto 0);
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to_register9_dout: in std_logic_vector(31 downto 0);
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to_register_dout: in std_logic_vector(31 downto 0);
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bram_rd_addr: out std_logic_vector(11 downto 0);
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bram_wr_addr: out std_logic_vector(11 downto 0);
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bram_wr_din: out std_logic_vector(63 downto 0);
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bram_wr_en: out std_logic_vector(7 downto 0);
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fifo_rd_en: out std_logic;
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fifo_wr_din: out std_logic_vector(71 downto 0);
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fifo_wr_en: out std_logic;
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rst_o: out std_logic;
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to_register10_ce: out std_logic;
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to_register10_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register10_clr: out std_logic;
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to_register10_data_in: out std_logic_vector(0 downto 0);
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to_register10_en: out std_logic_vector(0 downto 0);
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to_register11_ce: out std_logic;
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to_register11_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register11_clr: out std_logic;
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to_register11_data_in: out std_logic_vector(0 downto 0);
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to_register11_en: out std_logic_vector(0 downto 0);
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to_register12_ce: out std_logic;
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to_register12_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register12_clr: out std_logic;
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to_register12_data_in: out std_logic_vector(0 downto 0);
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to_register12_en: out std_logic_vector(0 downto 0);
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to_register13_ce: out std_logic;
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to_register13_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register13_clr: out std_logic;
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to_register13_data_in: out std_logic_vector(31 downto 0);
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to_register13_en: out std_logic_vector(0 downto 0);
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to_register14_ce: out std_logic;
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to_register14_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register14_clr: out std_logic;
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to_register14_data_in: out std_logic_vector(0 downto 0);
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to_register14_en: out std_logic_vector(0 downto 0);
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to_register15_ce: out std_logic;
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to_register15_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register15_clr: out std_logic;
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to_register15_data_in: out std_logic_vector(31 downto 0);
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to_register15_en: out std_logic_vector(0 downto 0);
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to_register16_ce: out std_logic;
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to_register16_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register16_clr: out std_logic;
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to_register16_data_in: out std_logic_vector(0 downto 0);
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to_register16_en: out std_logic_vector(0 downto 0);
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to_register17_ce: out std_logic;
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to_register17_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register17_clr: out std_logic;
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to_register17_data_in: out std_logic_vector(31 downto 0);
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to_register17_en: out std_logic_vector(0 downto 0);
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to_register18_ce: out std_logic;
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to_register18_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register18_clr: out std_logic;
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to_register18_data_in: out std_logic_vector(0 downto 0);
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to_register18_en: out std_logic_vector(0 downto 0);
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to_register19_ce: out std_logic;
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to_register19_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register19_clr: out std_logic;
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to_register19_data_in: out std_logic_vector(31 downto 0);
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to_register19_en: out std_logic_vector(0 downto 0);
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to_register1_ce: out std_logic;
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to_register1_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register1_clr: out std_logic;
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to_register1_data_in: out std_logic_vector(0 downto 0);
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to_register1_en: out std_logic_vector(0 downto 0);
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to_register20_ce: out std_logic;
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to_register20_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register20_clr: out std_logic;
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to_register20_data_in: out std_logic_vector(0 downto 0);
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to_register20_en: out std_logic_vector(0 downto 0);
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to_register21_ce: out std_logic;
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to_register21_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register21_clr: out std_logic;
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to_register21_data_in: out std_logic_vector(31 downto 0);
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to_register21_en: out std_logic_vector(0 downto 0);
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to_register22_ce: out std_logic;
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to_register22_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register22_clr: out std_logic;
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to_register22_data_in: out std_logic_vector(0 downto 0);
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to_register22_en: out std_logic_vector(0 downto 0);
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to_register23_ce: out std_logic;
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to_register23_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register23_clr: out std_logic;
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to_register23_data_in: out std_logic_vector(31 downto 0);
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to_register23_en: out std_logic_vector(0 downto 0);
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to_register24_ce: out std_logic;
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to_register24_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register24_clr: out std_logic;
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to_register24_data_in: out std_logic_vector(0 downto 0);
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to_register24_en: out std_logic_vector(0 downto 0);
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to_register25_ce: out std_logic;
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to_register25_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register25_clr: out std_logic;
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to_register25_data_in: out std_logic_vector(31 downto 0);
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to_register25_en: out std_logic_vector(0 downto 0);
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208 |
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to_register26_ce: out std_logic;
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to_register26_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register26_clr: out std_logic;
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to_register26_data_in: out std_logic_vector(0 downto 0);
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to_register26_en: out std_logic_vector(0 downto 0);
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213 |
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to_register27_ce: out std_logic;
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214 |
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to_register27_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register27_clr: out std_logic;
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216 |
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to_register27_data_in: out std_logic_vector(31 downto 0);
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217 |
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to_register27_en: out std_logic_vector(0 downto 0);
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218 |
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to_register2_ce: out std_logic;
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to_register2_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register2_clr: out std_logic;
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to_register2_data_in: out std_logic_vector(31 downto 0);
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to_register2_en: out std_logic_vector(0 downto 0);
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223 |
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to_register3_ce: out std_logic;
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224 |
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to_register3_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register3_clr: out std_logic;
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to_register3_data_in: out std_logic_vector(31 downto 0);
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to_register3_en: out std_logic_vector(0 downto 0);
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228 |
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to_register4_ce: out std_logic;
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229 |
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to_register4_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register4_clr: out std_logic;
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to_register4_data_in: out std_logic_vector(0 downto 0);
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to_register4_en: out std_logic_vector(0 downto 0);
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233 |
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to_register5_ce: out std_logic;
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to_register5_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register5_clr: out std_logic;
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to_register5_data_in: out std_logic_vector(0 downto 0);
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to_register5_en: out std_logic_vector(0 downto 0);
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238 |
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to_register6_ce: out std_logic;
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to_register6_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register6_clr: out std_logic;
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to_register6_data_in: out std_logic_vector(31 downto 0);
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to_register6_en: out std_logic_vector(0 downto 0);
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to_register7_ce: out std_logic;
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to_register7_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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245 |
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to_register7_clr: out std_logic;
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to_register7_data_in: out std_logic_vector(0 downto 0);
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to_register7_en: out std_logic_vector(0 downto 0);
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248 |
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to_register8_ce: out std_logic;
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249 |
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to_register8_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
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to_register8_clr: out std_logic;
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251 |
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to_register8_data_in: out std_logic_vector(31 downto 0);
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252 |
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to_register8_en: out std_logic_vector(0 downto 0);
|
253 |
|
|
to_register9_ce: out std_logic;
|
254 |
|
|
to_register9_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
255 |
|
|
to_register9_clr: out std_logic;
|
256 |
|
|
to_register9_data_in: out std_logic_vector(31 downto 0);
|
257 |
|
|
to_register9_en: out std_logic_vector(0 downto 0);
|
258 |
|
|
to_register_ce: out std_logic;
|
259 |
|
|
to_register_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
260 |
|
|
to_register_clr: out std_logic;
|
261 |
|
|
to_register_data_in: out std_logic_vector(31 downto 0);
|
262 |
|
|
to_register_en: out std_logic_vector(0 downto 0);
|
263 |
|
|
user_int_1o: out std_logic;
|
264 |
|
|
user_int_2o: out std_logic;
|
265 |
|
|
user_int_3o: out std_logic
|
266 |
|
|
);
|
267 |
|
|
end component;
|
268 |
|
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
269 |
|
|
|
270 |
|
|
-- The following code must appear in the VHDL architecture
|
271 |
|
|
-- body. Substitute your own instance name and net names.
|
272 |
|
|
|
273 |
|
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
274 |
|
|
your_instance_name : user_logic_cw
|
275 |
|
|
port map (
|
276 |
|
|
bram_rd_dout => bram_rd_dout,
|
277 |
|
|
ce => ce,
|
278 |
|
|
clk => clk,
|
279 |
|
|
fifo_rd_count => fifo_rd_count,
|
280 |
|
|
fifo_rd_dout => fifo_rd_dout,
|
281 |
|
|
fifo_rd_empty => fifo_rd_empty,
|
282 |
|
|
fifo_rd_pempty => fifo_rd_pempty,
|
283 |
|
|
fifo_rd_valid => fifo_rd_valid,
|
284 |
|
|
fifo_wr_count => fifo_wr_count,
|
285 |
|
|
fifo_wr_full => fifo_wr_full,
|
286 |
|
|
fifo_wr_pfull => fifo_wr_pfull,
|
287 |
|
|
from_register10_data_out => from_register10_data_out,
|
288 |
|
|
from_register11_data_out => from_register11_data_out,
|
289 |
|
|
from_register12_data_out => from_register12_data_out,
|
290 |
|
|
from_register13_data_out => from_register13_data_out,
|
291 |
|
|
from_register14_data_out => from_register14_data_out,
|
292 |
|
|
from_register15_data_out => from_register15_data_out,
|
293 |
|
|
from_register16_data_out => from_register16_data_out,
|
294 |
|
|
from_register17_data_out => from_register17_data_out,
|
295 |
|
|
from_register18_data_out => from_register18_data_out,
|
296 |
|
|
from_register19_data_out => from_register19_data_out,
|
297 |
|
|
from_register1_data_out => from_register1_data_out,
|
298 |
|
|
from_register20_data_out => from_register20_data_out,
|
299 |
|
|
from_register21_data_out => from_register21_data_out,
|
300 |
|
|
from_register22_data_out => from_register22_data_out,
|
301 |
|
|
from_register23_data_out => from_register23_data_out,
|
302 |
|
|
from_register24_data_out => from_register24_data_out,
|
303 |
|
|
from_register25_data_out => from_register25_data_out,
|
304 |
|
|
from_register26_data_out => from_register26_data_out,
|
305 |
|
|
from_register27_data_out => from_register27_data_out,
|
306 |
|
|
from_register28_data_out => from_register28_data_out,
|
307 |
|
|
from_register29_data_out => from_register29_data_out,
|
308 |
|
|
from_register2_data_out => from_register2_data_out,
|
309 |
|
|
from_register30_data_out => from_register30_data_out,
|
310 |
|
|
from_register31_data_out => from_register31_data_out,
|
311 |
|
|
from_register32_data_out => from_register32_data_out,
|
312 |
|
|
from_register33_data_out => from_register33_data_out,
|
313 |
|
|
from_register3_data_out => from_register3_data_out,
|
314 |
|
|
from_register4_data_out => from_register4_data_out,
|
315 |
|
|
from_register5_data_out => from_register5_data_out,
|
316 |
|
|
from_register6_data_out => from_register6_data_out,
|
317 |
|
|
from_register7_data_out => from_register7_data_out,
|
318 |
|
|
from_register8_data_out => from_register8_data_out,
|
319 |
|
|
from_register9_data_out => from_register9_data_out,
|
320 |
|
|
from_register_data_out => from_register_data_out,
|
321 |
|
|
rst_i => rst_i,
|
322 |
|
|
to_register10_dout => to_register10_dout,
|
323 |
|
|
to_register11_dout => to_register11_dout,
|
324 |
|
|
to_register12_dout => to_register12_dout,
|
325 |
|
|
to_register13_dout => to_register13_dout,
|
326 |
|
|
to_register14_dout => to_register14_dout,
|
327 |
|
|
to_register15_dout => to_register15_dout,
|
328 |
|
|
to_register16_dout => to_register16_dout,
|
329 |
|
|
to_register17_dout => to_register17_dout,
|
330 |
|
|
to_register18_dout => to_register18_dout,
|
331 |
|
|
to_register19_dout => to_register19_dout,
|
332 |
|
|
to_register1_dout => to_register1_dout,
|
333 |
|
|
to_register20_dout => to_register20_dout,
|
334 |
|
|
to_register21_dout => to_register21_dout,
|
335 |
|
|
to_register22_dout => to_register22_dout,
|
336 |
|
|
to_register23_dout => to_register23_dout,
|
337 |
|
|
to_register24_dout => to_register24_dout,
|
338 |
|
|
to_register25_dout => to_register25_dout,
|
339 |
|
|
to_register26_dout => to_register26_dout,
|
340 |
|
|
to_register27_dout => to_register27_dout,
|
341 |
|
|
to_register2_dout => to_register2_dout,
|
342 |
|
|
to_register3_dout => to_register3_dout,
|
343 |
|
|
to_register4_dout => to_register4_dout,
|
344 |
|
|
to_register5_dout => to_register5_dout,
|
345 |
|
|
to_register6_dout => to_register6_dout,
|
346 |
|
|
to_register7_dout => to_register7_dout,
|
347 |
|
|
to_register8_dout => to_register8_dout,
|
348 |
|
|
to_register9_dout => to_register9_dout,
|
349 |
|
|
to_register_dout => to_register_dout,
|
350 |
|
|
bram_rd_addr => bram_rd_addr,
|
351 |
|
|
bram_wr_addr => bram_wr_addr,
|
352 |
|
|
bram_wr_din => bram_wr_din,
|
353 |
|
|
bram_wr_en => bram_wr_en,
|
354 |
|
|
fifo_rd_en => fifo_rd_en,
|
355 |
|
|
fifo_wr_din => fifo_wr_din,
|
356 |
|
|
fifo_wr_en => fifo_wr_en,
|
357 |
|
|
rst_o => rst_o,
|
358 |
|
|
to_register10_ce => to_register10_ce,
|
359 |
|
|
to_register10_clk => to_register10_clk,
|
360 |
|
|
to_register10_clr => to_register10_clr,
|
361 |
|
|
to_register10_data_in => to_register10_data_in,
|
362 |
|
|
to_register10_en => to_register10_en,
|
363 |
|
|
to_register11_ce => to_register11_ce,
|
364 |
|
|
to_register11_clk => to_register11_clk,
|
365 |
|
|
to_register11_clr => to_register11_clr,
|
366 |
|
|
to_register11_data_in => to_register11_data_in,
|
367 |
|
|
to_register11_en => to_register11_en,
|
368 |
|
|
to_register12_ce => to_register12_ce,
|
369 |
|
|
to_register12_clk => to_register12_clk,
|
370 |
|
|
to_register12_clr => to_register12_clr,
|
371 |
|
|
to_register12_data_in => to_register12_data_in,
|
372 |
|
|
to_register12_en => to_register12_en,
|
373 |
|
|
to_register13_ce => to_register13_ce,
|
374 |
|
|
to_register13_clk => to_register13_clk,
|
375 |
|
|
to_register13_clr => to_register13_clr,
|
376 |
|
|
to_register13_data_in => to_register13_data_in,
|
377 |
|
|
to_register13_en => to_register13_en,
|
378 |
|
|
to_register14_ce => to_register14_ce,
|
379 |
|
|
to_register14_clk => to_register14_clk,
|
380 |
|
|
to_register14_clr => to_register14_clr,
|
381 |
|
|
to_register14_data_in => to_register14_data_in,
|
382 |
|
|
to_register14_en => to_register14_en,
|
383 |
|
|
to_register15_ce => to_register15_ce,
|
384 |
|
|
to_register15_clk => to_register15_clk,
|
385 |
|
|
to_register15_clr => to_register15_clr,
|
386 |
|
|
to_register15_data_in => to_register15_data_in,
|
387 |
|
|
to_register15_en => to_register15_en,
|
388 |
|
|
to_register16_ce => to_register16_ce,
|
389 |
|
|
to_register16_clk => to_register16_clk,
|
390 |
|
|
to_register16_clr => to_register16_clr,
|
391 |
|
|
to_register16_data_in => to_register16_data_in,
|
392 |
|
|
to_register16_en => to_register16_en,
|
393 |
|
|
to_register17_ce => to_register17_ce,
|
394 |
|
|
to_register17_clk => to_register17_clk,
|
395 |
|
|
to_register17_clr => to_register17_clr,
|
396 |
|
|
to_register17_data_in => to_register17_data_in,
|
397 |
|
|
to_register17_en => to_register17_en,
|
398 |
|
|
to_register18_ce => to_register18_ce,
|
399 |
|
|
to_register18_clk => to_register18_clk,
|
400 |
|
|
to_register18_clr => to_register18_clr,
|
401 |
|
|
to_register18_data_in => to_register18_data_in,
|
402 |
|
|
to_register18_en => to_register18_en,
|
403 |
|
|
to_register19_ce => to_register19_ce,
|
404 |
|
|
to_register19_clk => to_register19_clk,
|
405 |
|
|
to_register19_clr => to_register19_clr,
|
406 |
|
|
to_register19_data_in => to_register19_data_in,
|
407 |
|
|
to_register19_en => to_register19_en,
|
408 |
|
|
to_register1_ce => to_register1_ce,
|
409 |
|
|
to_register1_clk => to_register1_clk,
|
410 |
|
|
to_register1_clr => to_register1_clr,
|
411 |
|
|
to_register1_data_in => to_register1_data_in,
|
412 |
|
|
to_register1_en => to_register1_en,
|
413 |
|
|
to_register20_ce => to_register20_ce,
|
414 |
|
|
to_register20_clk => to_register20_clk,
|
415 |
|
|
to_register20_clr => to_register20_clr,
|
416 |
|
|
to_register20_data_in => to_register20_data_in,
|
417 |
|
|
to_register20_en => to_register20_en,
|
418 |
|
|
to_register21_ce => to_register21_ce,
|
419 |
|
|
to_register21_clk => to_register21_clk,
|
420 |
|
|
to_register21_clr => to_register21_clr,
|
421 |
|
|
to_register21_data_in => to_register21_data_in,
|
422 |
|
|
to_register21_en => to_register21_en,
|
423 |
|
|
to_register22_ce => to_register22_ce,
|
424 |
|
|
to_register22_clk => to_register22_clk,
|
425 |
|
|
to_register22_clr => to_register22_clr,
|
426 |
|
|
to_register22_data_in => to_register22_data_in,
|
427 |
|
|
to_register22_en => to_register22_en,
|
428 |
|
|
to_register23_ce => to_register23_ce,
|
429 |
|
|
to_register23_clk => to_register23_clk,
|
430 |
|
|
to_register23_clr => to_register23_clr,
|
431 |
|
|
to_register23_data_in => to_register23_data_in,
|
432 |
|
|
to_register23_en => to_register23_en,
|
433 |
|
|
to_register24_ce => to_register24_ce,
|
434 |
|
|
to_register24_clk => to_register24_clk,
|
435 |
|
|
to_register24_clr => to_register24_clr,
|
436 |
|
|
to_register24_data_in => to_register24_data_in,
|
437 |
|
|
to_register24_en => to_register24_en,
|
438 |
|
|
to_register25_ce => to_register25_ce,
|
439 |
|
|
to_register25_clk => to_register25_clk,
|
440 |
|
|
to_register25_clr => to_register25_clr,
|
441 |
|
|
to_register25_data_in => to_register25_data_in,
|
442 |
|
|
to_register25_en => to_register25_en,
|
443 |
|
|
to_register26_ce => to_register26_ce,
|
444 |
|
|
to_register26_clk => to_register26_clk,
|
445 |
|
|
to_register26_clr => to_register26_clr,
|
446 |
|
|
to_register26_data_in => to_register26_data_in,
|
447 |
|
|
to_register26_en => to_register26_en,
|
448 |
|
|
to_register27_ce => to_register27_ce,
|
449 |
|
|
to_register27_clk => to_register27_clk,
|
450 |
|
|
to_register27_clr => to_register27_clr,
|
451 |
|
|
to_register27_data_in => to_register27_data_in,
|
452 |
|
|
to_register27_en => to_register27_en,
|
453 |
|
|
to_register2_ce => to_register2_ce,
|
454 |
|
|
to_register2_clk => to_register2_clk,
|
455 |
|
|
to_register2_clr => to_register2_clr,
|
456 |
|
|
to_register2_data_in => to_register2_data_in,
|
457 |
|
|
to_register2_en => to_register2_en,
|
458 |
|
|
to_register3_ce => to_register3_ce,
|
459 |
|
|
to_register3_clk => to_register3_clk,
|
460 |
|
|
to_register3_clr => to_register3_clr,
|
461 |
|
|
to_register3_data_in => to_register3_data_in,
|
462 |
|
|
to_register3_en => to_register3_en,
|
463 |
|
|
to_register4_ce => to_register4_ce,
|
464 |
|
|
to_register4_clk => to_register4_clk,
|
465 |
|
|
to_register4_clr => to_register4_clr,
|
466 |
|
|
to_register4_data_in => to_register4_data_in,
|
467 |
|
|
to_register4_en => to_register4_en,
|
468 |
|
|
to_register5_ce => to_register5_ce,
|
469 |
|
|
to_register5_clk => to_register5_clk,
|
470 |
|
|
to_register5_clr => to_register5_clr,
|
471 |
|
|
to_register5_data_in => to_register5_data_in,
|
472 |
|
|
to_register5_en => to_register5_en,
|
473 |
|
|
to_register6_ce => to_register6_ce,
|
474 |
|
|
to_register6_clk => to_register6_clk,
|
475 |
|
|
to_register6_clr => to_register6_clr,
|
476 |
|
|
to_register6_data_in => to_register6_data_in,
|
477 |
|
|
to_register6_en => to_register6_en,
|
478 |
|
|
to_register7_ce => to_register7_ce,
|
479 |
|
|
to_register7_clk => to_register7_clk,
|
480 |
|
|
to_register7_clr => to_register7_clr,
|
481 |
|
|
to_register7_data_in => to_register7_data_in,
|
482 |
|
|
to_register7_en => to_register7_en,
|
483 |
|
|
to_register8_ce => to_register8_ce,
|
484 |
|
|
to_register8_clk => to_register8_clk,
|
485 |
|
|
to_register8_clr => to_register8_clr,
|
486 |
|
|
to_register8_data_in => to_register8_data_in,
|
487 |
|
|
to_register8_en => to_register8_en,
|
488 |
|
|
to_register9_ce => to_register9_ce,
|
489 |
|
|
to_register9_clk => to_register9_clk,
|
490 |
|
|
to_register9_clr => to_register9_clr,
|
491 |
|
|
to_register9_data_in => to_register9_data_in,
|
492 |
|
|
to_register9_en => to_register9_en,
|
493 |
|
|
to_register_ce => to_register_ce,
|
494 |
|
|
to_register_clk => to_register_clk,
|
495 |
|
|
to_register_clr => to_register_clr,
|
496 |
|
|
to_register_data_in => to_register_data_in,
|
497 |
|
|
to_register_en => to_register_en,
|
498 |
|
|
user_int_1o => user_int_1o,
|
499 |
|
|
user_int_2o => user_int_2o,
|
500 |
|
|
user_int_3o => user_int_3o);
|
501 |
|
|
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|