OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [coregen.cgc] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba
2
3 
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991
992 
                  2011-03-14T07:12:32.000Z
993
994
995
996
997 
                  apply_current_project_options_generator
998
999
1000 
                  model_parameter_resolution_generator
1001
1002
1003 
                  ip_xco_generator
1004
1005 
                     ./v6_afifo_256x36.xco
1006 
                     xco
1007 
                     Mon Mar 26 13:26:08 GMT 2012
1008 
                     0x00C798CA
1009 
                     generationid_3768282592
1010
1011
1012
1013 
                  associated_files_generator
1014
1015 
                     ./fifo_generator_ug175.pdf
1016 
                     pdf
1017 
                     Wed Oct 05 00:21:33 GMT 2011
1018 
                     0x42070F84
1019 
                     generationid_3768282592
1020
1021
1022 
                     ./fifo_generator_v8_3_readme.txt
1023 
                     txt
1024 
                     Wed Oct 05 00:21:33 GMT 2011
1025 
                     0xCD35AB83
1026 
                     generationid_3768282592
1027
1028
1029
1030 
                  ejava_generator
1031
1032 
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.ucf
1033 
                     ignore
1034 
                     ucf
1035 
                     Mon Mar 26 13:26:11 GMT 2012
1036 
                     0xB0FB4AAF
1037 
                     generationid_3768282592
1038
1039
1040 
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.vhd
1041 
                     ignore
1042 
                     vhdl
1043 
                     Mon Mar 26 13:26:11 GMT 2012
1044 
                     0xFF5FDC4B
1045 
                     generationid_3768282592
1046
1047
1048 
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.xdc
1049 
                     ignore
1050 
                     xdc
1051 
                     Mon Mar 26 13:26:11 GMT 2012
1052 
                     0xA1CB2F49
1053 
                     generationid_3768282592
1054
1055
1056 
                     ./v6_afifo_256x36_ste/implement/implement.bat
1057 
                     ignore
1058 
                     unknown
1059 
                     Mon Mar 26 13:26:11 GMT 2012
1060 
                     0x6802F528
1061 
                     generationid_3768282592
1062
1063
1064 
                     ./v6_afifo_256x36_ste/implement/implement.sh
1065 
                     ignore
1066 
                     unknown
1067 
                     Mon Mar 26 13:26:11 GMT 2012
1068 
                     0xC3A0E9D1
1069 
                     generationid_3768282592
1070
1071
1072 
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.bat
1073 
                     ignore
1074 
                     unknown
1075 
                     Mon Mar 26 13:26:11 GMT 2012
1076 
                     0xA496078D
1077 
                     generationid_3768282592
1078
1079
1080 
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.sh
1081 
                     ignore
1082 
                     unknown
1083 
                     Mon Mar 26 13:26:11 GMT 2012
1084 
                     0x6AFC3016
1085 
                     generationid_3768282592
1086
1087
1088 
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.tcl
1089 
                     ignore
1090 
                     tcl
1091 
                     Mon Mar 26 13:26:11 GMT 2012
1092 
                     0xFF794213
1093 
                     generationid_3768282592
1094
1095
1096 
                     ./v6_afifo_256x36_ste/implement/xst.prj
1097 
                     ignore
1098 
                     unknown
1099 
                     Mon Mar 26 13:26:11 GMT 2012
1100 
                     0x52D06ED1
1101 
                     generationid_3768282592
1102
1103
1104 
                     ./v6_afifo_256x36_ste/implement/xst.scr
1105 
                     ignore
1106 
                     unknown
1107 
                     Mon Mar 26 13:26:11 GMT 2012
1108 
                     0xDCF3959F
1109 
                     generationid_3768282592
1110
1111
1112
1113 
                  ngc_netlist_generator
1114
1115 
                     ./v6_afifo_256x36.ngc
1116 
                     ngc
1117 
                     Mon Mar 26 13:28:02 GMT 2012
1118 
                     0xABF577D4
1119 
                     generationid_3768282592
1120
1121
1122
1123 
                  obfuscate_netlist_generator
1124
1125
1126 
                  padded_implementation_netlist_generator
1127
1128
1129 
                  instantiation_template_generator
1130
1131 
                     ./v6_afifo_256x36.vho
1132 
                     vho
1133 
                     Mon Mar 26 13:28:04 GMT 2012
1134 
                     0xB9A340C4
1135 
                     generationid_3768282592
1136
1137
1138
1139 
                  structural_simulation_model_generator
1140
1141 
                     ./v6_afifo_256x36.vhd
1142 
                     vhdl
1143 
                     Mon Mar 26 13:28:06 GMT 2012
1144 
                     0xE8F19707
1145 
                     generationid_3768282592
1146
1147
1148
1149 
                  asy_generator
1150
1151 
                     ./v6_afifo_256x36.asy
1152 
                     asy
1153 
                     Mon Mar 26 13:28:12 GMT 2012
1154 
                     0xF028BBDB
1155 
                     generationid_3768282592
1156
1157
1158
1159 
                  xmdf_generator
1160
1161 
                     ./v6_afifo_256x36_xmdf.tcl
1162 
                     tclXmdf
1163 
                     tcl
1164 
                     Mon Mar 26 13:28:13 GMT 2012
1165 
                     0xA1AB5CB8
1166 
                     generationid_3768282592
1167
1168
1169
1170 
                  ise_generator
1171
1172 
                     ./_xmsgs/pn_parser.xmsgs
1173 
                     ignore
1174 
                     unknown
1175 
                     Mon Mar 26 13:28:21 GMT 2012
1176 
                     0x8C85D34A
1177 
                     generationid_3768282592
1178
1179
1180 
                     ./v6_afifo_256x36.gise
1181 
                     ignore
1182 
                     gise
1183 
                     Mon Mar 26 13:28:21 GMT 2012
1184 
                     0xCB19B284
1185 
                     generationid_3768282592
1186
1187
1188 
                     ./v6_afifo_256x36.xise
1189 
                     ignore
1190 
                     xise
1191 
                     Mon Mar 26 13:28:21 GMT 2012
1192 
                     0x7F700B0C
1193 
                     generationid_3768282592
1194
1195
1196
1197 
                  deliver_readme_generator
1198
1199
1200 
                  flist_generator
1201
1202 
                     ./v6_afifo_256x36_flist.txt
1203 
                     ignore
1204 
                     txtFlist
1205 
                     txt
1206 
                     Mon Mar 26 13:28:22 GMT 2012
1207 
                     0x2FB493C5
1208 
                     generationid_3768282592
1209
1210
1211
1212
1213
1214
1215 
         v6_afifo_256x36c_fwft
1216
1217
1218 
            v6_afifo_256x36c_fwft
1219 
            Independent_Clocks_Block_RAM
1220 
            Native
1221 
            First_Word_Fall_Through
1222 
            36
1223 
            512
1224 
            36
1225 
            512
1226 
            false
1227 
            false
1228 
            true
1229 
            true
1230 
            Asynchronous_Reset
1231 
            1
1232 
            true
1233 
            0
1234 
            false
1235 
            false
1236 
            false
1237 
            Active_High
1238 
            false
1239 
            Active_High
1240 
            false
1241 
            Active_High
1242 
            false
1243 
            Active_High
1244 
            false
1245 
            false
1246 
            false
1247 
            false
1248 
            9
1249 
            false
1250 
            9
1251 
            true
1252 
            9
1253 
            false
1254 
            1
1255 
            1
1256 
            Single_Programmable_Full_Threshold_Constant
1257 
            320
1258 
            319
1259 
            Single_Programmable_Empty_Threshold_Constant
1260 
            8
1261 
            9
1262 
            AXI4_Stream
1263 
            Common_Clock
1264 
            false
1265 
            Slave_Interface_Clock_Enable
1266 
            false
1267 
            false
1268 
            4
1269 
            32
1270 
            64
1271 
            false
1272 
            1
1273 
            false
1274 
            1
1275 
            false
1276 
            1
1277 
            false
1278 
            1
1279 
            false
1280 
            1
1281 
            false
1282 
            64
1283 
            false
1284 
            8
1285 
            false
1286 
            4
1287 
            false
1288 
            4
1289 
            true
1290 
            false
1291 
            false
1292 
            4
1293 
            false
1294 
            4
1295 
            FIFO
1296 
            Common_Clock_Block_RAM
1297 
            Data_FIFO
1298 
            false
1299 
            false
1300 
            false
1301 
            16
1302 
            false
1303 
            false
1304 
            Full
1305 
            1023
1306 
            Empty
1307 
            1022
1308 
            FIFO
1309 
            Common_Clock_Block_RAM
1310 
            Data_FIFO
1311 
            false
1312 
            false
1313 
            false
1314 
            1024
1315 
            false
1316 
            false
1317 
            Full
1318 
            1023
1319 
            Empty
1320 
            1022
1321 
            FIFO
1322 
            Common_Clock_Block_RAM
1323 
            Data_FIFO
1324 
            false
1325 
            false
1326 
            false
1327 
            16
1328 
            false
1329 
            false
1330 
            Full
1331 
            1023
1332 
            Empty
1333 
            1022
1334 
            FIFO
1335 
            Common_Clock_Block_RAM
1336 
            Data_FIFO
1337 
            false
1338 
            false
1339 
            false
1340 
            16
1341 
            false
1342 
            false
1343 
            Full
1344 
            1023
1345 
            Empty
1346 
            1022
1347 
            FIFO
1348 
            Common_Clock_Block_RAM
1349 
            Data_FIFO
1350 
            false
1351 
            false
1352 
            false
1353 
            1024
1354 
            false
1355 
            false
1356 
            Full
1357 
            1023
1358 
            Empty
1359 
            1022
1360 
            FIFO
1361 
            Common_Clock_Block_RAM
1362 
            Data_FIFO
1363 
            false
1364 
            false
1365 
            false
1366 
            1024
1367 
            false
1368 
            false
1369 
            Full
1370 
            1023
1371 
            Empty
1372 
            1022
1373 
            Fully_Registered
1374 
            Fully_Registered
1375 
            Fully_Registered
1376 
            Fully_Registered
1377 
            Fully_Registered
1378 
            Fully_Registered
1379 
            false
1380 
            Active_High
1381 
            false
1382 
            Active_High
1383 
            false
1384 
            false
1385 
            false
1386 
            false
1387 
            false
1388 
            0
1389 
            9
1390 
            36
1391 
            0
1392 
            36
1393 
            virtex6
1394 
            1
1395 
            0
1396 
            0
1397 
            0
1398 
            0
1399 
            0
1400 
            1
1401 
            1
1402 
            0
1403 
            0
1404 
            0
1405 
            0
1406 
            0
1407 
            2
1408 
            1
1409 
            0
1410 
            0
1411 
            1
1412 
            512x36
1413 
            8
1414 
            9
1415 
            1
1416 
            320
1417 
            319
1418 
            1
1419 
            9
1420 
            512
1421 
            1
1422 
            9
1423 
            0
1424 
            1
1425 
            0
1426 
            0
1427 
            0
1428 
            0
1429 
            0
1430 
            9
1431 
            512
1432 
            1
1433 
            9
1434 
            1
1435 
            1
1436 
            0
1437 
            0
1438 
            0
1439 
            0
1440 
            0
1441 
            0
1442 
            0
1443 
            0
1444 
            0
1445 
            0
1446 
            4
1447 
            32
1448 
            64
1449 
            0
1450 
            0
1451 
            0
1452 
            0
1453 
            0
1454 
            1
1455 
            1
1456 
            1
1457 
            1
1458 
            1
1459 
            0
1460 
            0
1461 
            0
1462 
            0
1463 
            1
1464 
            0
1465 
            0
1466 
            0
1467 
            64
1468 
            8
1469 
            4
1470 
            4
1471 
            4
1472 
            4
1473 
            0
1474 
            0
1475 
            0
1476 
            0
1477 
            0
1478 
            0
1479 
            1
1480 
            1
1481 
            1
1482 
            1
1483 
            1
1484 
            1
1485 
            0
1486 
            0
1487 
            0
1488 
            0
1489 
            0
1490 
            0
1491 
            0
1492 
            0
1493 
            0
1494 
            0
1495 
            0
1496 
            0
1497 
            0
1498 
            0
1499 
            0
1500 
            0
1501 
            0
1502 
            0
1503 
            32
1504 
            64
1505 
            2
1506 
            32
1507 
            64
1508 
            1
1509 
            16
1510 
            1024
1511 
            16
1512 
            16
1513 
            1024
1514 
            1024
1515 
            4
1516 
            10
1517 
            4
1518 
            4
1519 
            10
1520 
            10
1521 
            0
1522 
            0
1523 
            0
1524 
            0
1525 
            0
1526 
            0
1527 
            0
1528 
            0
1529 
            0
1530 
            0
1531 
            0
1532 
            0
1533 
            5
1534 
            5
1535 
            5
1536 
            5
1537 
            5
1538 
            5
1539 
            1023
1540 
            1023
1541 
            1023
1542 
            1023
1543 
            1023
1544 
            1023
1545 
            5
1546 
            5
1547 
            5
1548 
            5
1549 
            5
1550 
            5
1551 
            1022
1552 
            1022
1553 
            1022
1554 
            1022
1555 
            1022
1556 
            1022
1557 
            0
1558 
            0
1559 
            0
1560 
            0
1561 
            0
1562 
            0
1563
1564
1565
1566
1567 
                  coregen
1568 
                  ./
1569 
                  ./tmp/
1570 
                  ./tmp/_cg/
1571
1572
1573 
                  xc6vlx240t
1574 
                  virtex6
1575 
                  ff1156
1576 
                  -1
1577
1578
1579 
                  BusFormatAngleBracketNotRipped
1580 
                  VHDL
1581 
                  true
1582 
                  Foundation_ISE
1583 
                  false
1584 
                  false
1585 
                  false
1586 
                  Ngc
1587 
                  false
1588
1589
1590 
                  Structural
1591 
                  VHDL
1592 
                  false
1593
1594
1595 
                  2011-03-14T07:12:32.000Z
1596
1597
1598
1599
1600 
                  apply_current_project_options_generator
1601
1602
1603 
                  model_parameter_resolution_generator
1604
1605
1606 
                  ip_xco_generator
1607
1608 
                     ./v6_afifo_256x36c_fwft.xco
1609 
                     xco
1610 
                     Mon Mar 26 13:28:33 GMT 2012
1611 
                     0x5A127C6A
1612 
                     generationid_3768282592
1613
1614
1615
1616 
                  associated_files_generator
1617
1618 
                     ./fifo_generator_ug175.pdf
1619 
                     pdf
1620 
                     Wed Oct 05 00:21:33 GMT 2011
1621 
                     0x42070F84
1622 
                     generationid_3768282592
1623
1624
1625 
                     ./fifo_generator_v8_3_readme.txt
1626 
                     txt
1627 
                     Wed Oct 05 00:21:33 GMT 2011
1628 
                     0xCD35AB83
1629 
                     generationid_3768282592
1630
1631
1632
1633 
                  ejava_generator
1634
1635 
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.ucf
1636 
                     ignore
1637 
                     ucf
1638 
                     Mon Mar 26 13:28:34 GMT 2012
1639 
                     0xB0FB4AAF
1640 
                     generationid_3768282592
1641
1642
1643 
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.vhd
1644 
                     ignore
1645 
                     vhdl
1646 
                     Mon Mar 26 13:28:34 GMT 2012
1647 
                     0x3929C5D1
1648 
                     generationid_3768282592
1649
1650
1651 
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.xdc
1652 
                     ignore
1653 
                     xdc
1654 
                     Mon Mar 26 13:28:34 GMT 2012
1655 
                     0xA1CB2F49
1656 
                     generationid_3768282592
1657
1658
1659 
                     ./v6_afifo_256x36c_fwft_ste/implement/implement.bat
1660 
                     ignore
1661 
                     unknown
1662 
                     Mon Mar 26 13:28:34 GMT 2012
1663 
                     0x731E5FEE
1664 
                     generationid_3768282592
1665
1666
1667 
                     ./v6_afifo_256x36c_fwft_ste/implement/implement.sh
1668 
                     ignore
1669 
                     unknown
1670 
                     Mon Mar 26 13:28:34 GMT 2012
1671 
                     0xD03A1FB2
1672 
                     generationid_3768282592
1673
1674
1675 
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.bat
1676 
                     ignore
1677 
                     unknown
1678 
                     Mon Mar 26 13:28:34 GMT 2012
1679 
                     0xA2ADD42D
1680 
                     generationid_3768282592
1681
1682
1683 
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.sh
1684 
                     ignore
1685 
                     unknown
1686 
                     Mon Mar 26 13:28:34 GMT 2012
1687 
                     0x7AC68DF6
1688 
                     generationid_3768282592
1689
1690
1691 
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.tcl
1692 
                     ignore
1693 
                     tcl
1694 
                     Mon Mar 26 13:28:34 GMT 2012
1695 
                     0x2BCDFC14
1696 
                     generationid_3768282592
1697
1698
1699 
                     ./v6_afifo_256x36c_fwft_ste/implement/xst.prj
1700 
                     ignore
1701 
                     unknown
1702 
                     Mon Mar 26 13:28:34 GMT 2012
1703 
                     0x57CC4E14
1704 
                     generationid_3768282592
1705
1706
1707 
                     ./v6_afifo_256x36c_fwft_ste/implement/xst.scr
1708 
                     ignore
1709 
                     unknown
1710 
                     Mon Mar 26 13:28:34 GMT 2012
1711 
                     0xFA3827C9
1712 
                     generationid_3768282592
1713
1714
1715
1716 
                  ngc_netlist_generator
1717
1718 
                     ./v6_afifo_256x36c_fwft.ngc
1719 
                     ngc
1720 
                     Mon Mar 26 13:30:27 GMT 2012
1721 
                     0x8E013216
1722 
                     generationid_3768282592
1723
1724
1725
1726 
                  obfuscate_netlist_generator
1727
1728
1729 
                  padded_implementation_netlist_generator
1730
1731
1732 
                  instantiation_template_generator
1733
1734 
                     ./v6_afifo_256x36c_fwft.vho
1735 
                     vho
1736 
                     Mon Mar 26 13:30:28 GMT 2012
1737 
                     0xA334A8DC
1738 
                     generationid_3768282592
1739
1740
1741
1742 
                  structural_simulation_model_generator
1743
1744 
                     ./v6_afifo_256x36c_fwft.vhd
1745 
                     vhdl
1746 
                     Mon Mar 26 13:30:30 GMT 2012
1747 
                     0xAF6582C8
1748 
                     generationid_3768282592
1749
1750
1751
1752 
                  asy_generator
1753
1754 
                     ./v6_afifo_256x36c_fwft.asy
1755 
                     asy
1756 
                     Mon Mar 26 13:30:36 GMT 2012
1757 
                     0x7CCD393F
1758 
                     generationid_3768282592
1759
1760
1761
1762 
                  xmdf_generator
1763
1764 
                     ./v6_afifo_256x36c_fwft_xmdf.tcl
1765 
                     tclXmdf
1766 
                     tcl
1767 
                     Mon Mar 26 13:30:36 GMT 2012
1768 
                     0xE612ABDE
1769 
                     generationid_3768282592
1770
1771
1772
1773 
                  ise_generator
1774
1775 
                     ./_xmsgs/pn_parser.xmsgs
1776 
                     ignore
1777 
                     unknown
1778 
                     Mon Mar 26 13:30:43 GMT 2012
1779 
                     0x088DBF37
1780 
                     generationid_3768282592
1781
1782
1783 
                     ./v6_afifo_256x36c_fwft.gise
1784 
                     ignore
1785 
                     gise
1786 
                     Mon Mar 26 13:30:43 GMT 2012
1787 
                     0xB3D8EEB2
1788 
                     generationid_3768282592
1789
1790
1791 
                     ./v6_afifo_256x36c_fwft.xise
1792 
                     ignore
1793 
                     xise
1794 
                     Mon Mar 26 13:30:43 GMT 2012
1795 
                     0xC9F736AE
1796 
                     generationid_3768282592
1797
1798
1799
1800 
                  deliver_readme_generator
1801
1802
1803 
                  flist_generator
1804
1805 
                     ./v6_afifo_256x36c_fwft_flist.txt
1806 
                     ignore
1807 
                     txtFlist
1808 
                     txt
1809 
                     Mon Mar 26 13:30:44 GMT 2012
1810 
                     0x065442DD
1811 
                     generationid_3768282592
1812
1813
1814
1815
1816
1817
1818 
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1863 
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1866 
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1867 
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                  2011-03-14T07:12:32.000Z
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                  2011-03-11T08:24:14.000Z
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2228
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2231 
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2234 
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2238 
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2240 
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2241 
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2260 
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2261 
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2263 
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2264 
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2265 
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2266 
            1
2267 
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2268 
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2269 
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2270 
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2272 
            4096
2273 
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2274 
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2275 
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2276 
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2277 
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2278 
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2281 
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2300 
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2314 
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2329 
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2349 
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2353 
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2361 
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2362 
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2364 
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2385 
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2387 
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2391 
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2392 
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2393 
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2394 
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2395 
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2397 
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2398 
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2399 
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2400
2401
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2403
2404 
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2426
2427 
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2428 
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2429 
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2430
2431
2432 
                  2011-03-14T07:12:32.000Z
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2434
2435
2436
2437
2438 
         v6_eb_fifo_counted_new
2439
2440
2441 
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2442 
            Independent_Clocks_Block_RAM
2443 
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2444 
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2445 
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2446 
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2447 
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2448 
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2449 
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2455 
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2474 
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2478 
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2479 
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2487 
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2688 
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2690 
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2693 
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2694 
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2695 
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2696 
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2697 
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2698 
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2699 
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2700 
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2728 
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2729 
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2730 
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2731 
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2732 
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2757 
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2758 
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2764 
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2765 
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2767 
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2768 
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2769 
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2772 
            false
2773 
            false
2774 
            16
2775 
            false
2776 
            false
2777 
            Full
2778 
            1023
2779 
            Empty
2780 
            1022
2781 
            FIFO
2782 
            Common_Clock_Block_RAM
2783 
            Data_FIFO
2784 
            false
2785 
            false
2786 
            false
2787 
            1024
2788 
            false
2789 
            false
2790 
            Full
2791 
            1023
2792 
            Empty
2793 
            1022
2794 
            FIFO
2795 
            Common_Clock_Block_RAM
2796 
            Data_FIFO
2797 
            false
2798 
            false
2799 
            false
2800 
            1024
2801 
            false
2802 
            false
2803 
            Full
2804 
            1023
2805 
            Empty
2806 
            1022
2807 
            Fully_Registered
2808 
            Fully_Registered
2809 
            Fully_Registered
2810 
            Fully_Registered
2811 
            Fully_Registered
2812 
            Fully_Registered
2813 
            false
2814 
            Active_High
2815 
            false
2816 
            Active_High
2817 
            false
2818 
            false
2819 
            false
2820 
            false
2821 
            false
2822
2823
2824
2825
2826 
                  coregen
2827 
                  ./
2828 
                  ./tmp/
2829 
                  ./tmp/_cg/
2830
2831
2832 
                  xc6vlx240t
2833 
                  virtex6
2834 
                  ff1156
2835 
                  -1
2836
2837
2838 
                  BusFormatAngleBracketNotRipped
2839 
                  VHDL
2840 
                  true
2841 
                  Foundation_ISE
2842 
                  false
2843 
                  false
2844 
                  false
2845 
                  Ngc
2846 
                  false
2847
2848
2849 
                  Behavioral
2850 
                  VHDL_and_Verilog
2851 
                  false
2852
2853
2854 
                  2011-03-14T07:12:32.000Z
2855
2856
2857
2858
2859
2860 
         v6_mBuf_128x72
2861
2862
2863 
            v6_mBuf_128x72
2864 
            Common_Clock_Builtin_FIFO
2865 
            Native
2866 
            Standard_FIFO
2867 
            72
2868 
            512
2869 
            72
2870 
            512
2871 
            false
2872 
            false
2873 
            true
2874 
            true
2875 
            Asynchronous_Reset
2876 
            0
2877 
            false
2878 
            0
2879 
            false
2880 
            false
2881 
            false
2882 
            Active_High
2883 
            false
2884 
            Active_High
2885 
            false
2886 
            Active_High
2887 
            false
2888 
            Active_High
2889 
            false
2890 
            false
2891 
            false
2892 
            false
2893 
            9
2894 
            false
2895 
            9
2896 
            false
2897 
            9
2898 
            false
2899 
            1
2900 
            1
2901 
            Single_Programmable_Full_Threshold_Constant
2902 
            128
2903 
            127
2904 
            No_Programmable_Empty_Threshold
2905 
            2
2906 
            3
2907 
            AXI4_Stream
2908 
            Common_Clock
2909 
            false
2910 
            Slave_Interface_Clock_Enable
2911 
            false
2912 
            false
2913 
            4
2914 
            32
2915 
            64
2916 
            false
2917 
            1
2918 
            false
2919 
            1
2920 
            false
2921 
            1
2922 
            false
2923 
            1
2924 
            false
2925 
            1
2926 
            false
2927 
            64
2928 
            false
2929 
            8
2930 
            false
2931 
            4
2932 
            false
2933 
            4
2934 
            true
2935 
            false
2936 
            false
2937 
            4
2938 
            false
2939 
            4
2940 
            FIFO
2941 
            Common_Clock_Block_RAM
2942 
            Data_FIFO
2943 
            false
2944 
            false
2945 
            false
2946 
            16
2947 
            false
2948 
            false
2949 
            Full
2950 
            1023
2951 
            Empty
2952 
            1022
2953 
            FIFO
2954 
            Common_Clock_Block_RAM
2955 
            Data_FIFO
2956 
            false
2957 
            false
2958 
            false
2959 
            1024
2960 
            false
2961 
            false
2962 
            Full
2963 
            1023
2964 
            Empty
2965 
            1022
2966 
            FIFO
2967 
            Common_Clock_Block_RAM
2968 
            Data_FIFO
2969 
            false
2970 
            false
2971 
            false
2972 
            16
2973 
            false
2974 
            false
2975 
            Full
2976 
            1023
2977 
            Empty
2978 
            1022
2979 
            FIFO
2980 
            Common_Clock_Block_RAM
2981 
            Data_FIFO
2982 
            false
2983 
            false
2984 
            false
2985 
            16
2986 
            false
2987 
            false
2988 
            Full
2989 
            1023
2990 
            Empty
2991 
            1022
2992 
            FIFO
2993 
            Common_Clock_Block_RAM
2994 
            Data_FIFO
2995 
            false
2996 
            false
2997 
            false
2998 
            1024
2999 
            false
3000 
            false
3001 
            Full
3002 
            1023
3003 
            Empty
3004 
            1022
3005 
            FIFO
3006 
            Common_Clock_Block_RAM
3007 
            Data_FIFO
3008 
            false
3009 
            false
3010 
            false
3011 
            1024
3012 
            false
3013 
            false
3014 
            Full
3015 
            1023
3016 
            Empty
3017 
            1022
3018 
            Fully_Registered
3019 
            Fully_Registered
3020 
            Fully_Registered
3021 
            Fully_Registered
3022 
            Fully_Registered
3023 
            Fully_Registered
3024 
            false
3025 
            Active_High
3026 
            false
3027 
            Active_High
3028 
            false
3029 
            false
3030 
            false
3031 
            false
3032 
            false
3033
3034
3035
3036
3037 
                  coregen
3038 
                  ./
3039 
                  ./tmp/
3040 
                  ./tmp/_cg/
3041
3042
3043 
                  xc6vlx240t
3044 
                  virtex6
3045 
                  ff1156
3046 
                  -1
3047
3048
3049 
                  BusFormatAngleBracketNotRipped
3050 
                  VHDL
3051 
                  true
3052 
                  Foundation_ISE
3053 
                  false
3054 
                  false
3055 
                  false
3056 
                  Ngc
3057 
                  false
3058
3059
3060 
                  Behavioral
3061 
                  VHDL_and_Verilog
3062 
                  false
3063
3064
3065 
                  2011-03-14T07:12:32.000Z
3066
3067
3068
3069
3070
3071 
         v6_pcie_v1_6
3072
3073
3074 
            v6_pcie_v1_6
3075 
            High
3076 
            false
3077 
            false
3078 
            false
3079 
            Kilobytes
3080 
            Add
3081 
            false
3082 
            Memory
3083 
            Simple_communication_controllers
3084 
            1
3085 
            0
3086 
            0
3087 
            true
3088 
            false
3089 
            00
3090 
            Disabled
3091 
            0
3092 
            false
3093 
            false
3094 
            2
3095 
            false
3096 
            false
3097 
            false
3098 
            false
3099 
            false
3100 
            false
3101 
            false
3102 
            64
3103 
            false
3104 
            6014
3105 
            10EE
3106 
            No_limit
3107 
            1
3108 
            X0Y0
3109 
            false
3110 
            PCI_Express_Endpoint_device
3111 
            false
3112 
            N/A
3113 
            true
3114 
            0026
3115 
            true
3116 
            100_MHz
3117 
            05
3118 
            0
3119 
            ML_605
3120 
            3F
3121 
            2
3122 
            false
3123 
            0
3124 
            true
3125 
            false
3126 
            0
3127 
            4'h1
3128 
            false
3129 
            true
3130 
            0
3131 
            false
3132 
            1
3133 
            512_bytes
3134 
            true
3135 
            0
3136 
            125_default
3137 
            false
3138 
            N/A
3139 
            false
3140 
            0
3141 
            false
3142 
            Absolute
3143 
            false
3144 
            true
3145 
            0
3146 
            Kilobytes
3147 
            false
3148 
            false
3149 
            false
3150 
            false
3151 
            false
3152 
            false
3153 
            false
3154 
            Kilobytes
3155 
            0
3156 
            0
3157 
            false
3158 
            false
3159 
            false
3160 
            Kilobytes
3161 
            false
3162 
            true
3163 
            false
3164 
            4
3165 
            false
3166 
            false
3167 
            Range_B
3168 
            true
3169 
            Kilobytes
3170 
            ABB3
3171 
            N/A
3172 
            true
3173 
            X4
3174 
            false
3175 
            Megabytes
3176 
            false
3177 
            0
3178 
            0
3179 
            Memory
3180 
            0
3181 
            true
3182 
            false
3183 
            BAR_0
3184 
            Kilobytes
3185 
            false
3186 
            false
3187 
            false
3188 
            false
3189 
            0
3190 
            false
3191 
            2.5_GT/s
3192 
            false
3193 
            true
3194 
            false
3195 
            None
3196 
            None
3197 
            3FF
3198 
            false
3199 
            No_function_number_bits_used
3200 
            00
3201 
            2
3202 
            false
3203 
            false
3204 
            0
3205 
            false
3206 
            0
3207 
            INTA
3208 
            64_byte
3209 
            0
3210 
            false
3211 
            false
3212 
            Memory
3213 
            06
3214 
            false
3215 
            BAR_0
3216 
            1_vector
3217 
            false
3218 
            0
3219 
            0
3220 
            0084
3221 
            false
3222 
            0000
3223 
            00
3224 
            false
3225 
            00000000
3226 
            true
3227 
            true
3228 
            No_limit
3229 
            Disabled
3230 
            false
3231 
            Generic_XT_compatible_serial_controller
3232 
            0
3233 
            2
3234 
            false
3235
3236
3237
3238
3239 
                  coregen
3240 
                  ./
3241 
                  ./tmp/
3242 
                  ./tmp/_cg/
3243
3244
3245 
                  xc6vlx240t
3246 
                  virtex6
3247 
                  ff1156
3248 
                  -1
3249
3250
3251 
                  BusFormatAngleBracketNotRipped
3252 
                  VHDL
3253 
                  true
3254 
                  Foundation_ISE
3255 
                  false
3256 
                  false
3257 
                  false
3258 
                  Ngc
3259 
                  false
3260
3261
3262 
                  Behavioral
3263 
                  VHDL_and_Verilog
3264 
                  false
3265
3266
3267
3268
3269
3270 
         v6_pcie_v1_7_x1
3271
3272
3273 
            v6_pcie_v1_7_x1
3274 
            High
3275 
            false
3276 
            false
3277 
            false
3278 
            Kilobytes
3279 
            Add
3280 
            false
3281 
            Memory
3282 
            Simple_communication_controllers
3283 
            1
3284 
            0
3285 
            0
3286 
            true
3287 
            false
3288 
            00
3289 
            Disabled
3290 
            0
3291 
            false
3292 
            false
3293 
            2
3294 
            false
3295 
            false
3296 
            false
3297 
            false
3298 
            false
3299 
            false
3300 
            false
3301 
            64
3302 
            false
3303 
            6021
3304 
            10EE
3305 
            No_limit
3306 
            1
3307 
            X0Y0
3308 
            false
3309 
            PCI_Express_Endpoint_device
3310 
            false
3311 
            N/A
3312 
            true
3313 
            0026
3314 
            true
3315 
            100_MHz
3316 
            05
3317 
            0
3318 
            ML_605
3319 
            3F
3320 
            2
3321 
            false
3322 
            0
3323 
            true
3324 
            false
3325 
            0
3326 
            4'h2
3327 
            false
3328 
            true
3329 
            0
3330 
            false
3331 
            1
3332 
            512_bytes
3333 
            true
3334 
            0
3335 
            125
3336 
            false
3337 
            N/A
3338 
            false
3339 
            0
3340 
            false
3341 
            Absolute
3342 
            false
3343 
            true
3344 
            0
3345 
            Kilobytes
3346 
            false
3347 
            false
3348 
            false
3349 
            false
3350 
            false
3351 
            false
3352 
            false
3353 
            Kilobytes
3354 
            0
3355 
            0
3356 
            false
3357 
            false
3358 
            false
3359 
            Kilobytes
3360 
            false
3361 
            true
3362 
            false
3363 
            4
3364 
            false
3365 
            false
3366 
            Range_B
3367 
            true
3368 
            Kilobytes
3369 
            ABB3
3370 
            N/A
3371 
            true
3372 
            X1
3373 
            false
3374 
            Megabytes
3375 
            false
3376 
            0
3377 
            0
3378 
            Memory
3379 
            0
3380 
            true
3381 
            false
3382 
            BAR_0
3383 
            Kilobytes
3384 
            false
3385 
            false
3386 
            false
3387 
            false
3388 
            0
3389 
            false
3390 
            5.0_GT/s
3391 
            false
3392 
            true
3393 
            false
3394 
            None
3395 
            None
3396 
            3FF
3397 
            false
3398 
            No_function_number_bits_used
3399 
            00
3400 
            2
3401 
            false
3402 
            false
3403 
            0
3404 
            false
3405 
            0
3406 
            INTA
3407 
            64_byte
3408 
            0
3409 
            false
3410 
            false
3411 
            Memory
3412 
            06
3413 
            false
3414 
            BAR_0
3415 
            1_vector
3416 
            false
3417 
            0
3418 
            0
3419 
            0084
3420 
            false
3421 
            0000
3422 
            00
3423 
            false
3424 
            00000000
3425 
            true
3426 
            true
3427 
            No_limit
3428 
            Disabled
3429 
            false
3430 
            Generic_XT_compatible_serial_controller
3431 
            0
3432 
            2
3433 
            false
3434
3435
3436
3437
3438 
                  coregen
3439 
                  ./
3440 
                  ./tmp/
3441 
                  ./tmp/_cg/
3442
3443
3444 
                  xc6vlx240t
3445 
                  virtex6
3446 
                  ff1156
3447 
                  -1
3448
3449
3450 
                  BusFormatAngleBracketNotRipped
3451 
                  VHDL
3452 
                  true
3453 
                  Foundation_ISE
3454 
                  false
3455 
                  false
3456 
                  false
3457 
                  Ngc
3458 
                  false
3459
3460
3461 
                  Behavioral
3462 
                  VHDL_and_Verilog
3463 
                  false
3464
3465
3466
3467
3468
3469 
         v6_pcie_v1_7_x4
3470
3471
3472 
            v6_pcie_v1_7_x4
3473 
            High
3474 
            false
3475 
            false
3476 
            false
3477 
            Kilobytes
3478 
            Add
3479 
            false
3480 
            Memory
3481 
            Simple_communication_controllers
3482 
            1
3483 
            0
3484 
            0
3485 
            true
3486 
            false
3487 
            00
3488 
            Disabled
3489 
            0
3490 
            false
3491 
            false
3492 
            2
3493 
            false
3494 
            false
3495 
            false
3496 
            false
3497 
            false
3498 
            false
3499 
            false
3500 
            64
3501 
            false
3502 
            6014
3503 
            10EE
3504 
            No_limit
3505 
            1
3506 
            X0Y0
3507 
            false
3508 
            PCI_Express_Endpoint_device
3509 
            false
3510 
            N/A
3511 
            true
3512 
            0026
3513 
            true
3514 
            100_MHz
3515 
            05
3516 
            0
3517 
            ML_605
3518 
            3F
3519 
            2
3520 
            false
3521 
            0
3522 
            true
3523 
            false
3524 
            0
3525 
            4'h1
3526 
            false
3527 
            true
3528 
            0
3529 
            false
3530 
            1
3531 
            512_bytes
3532 
            true
3533 
            0
3534 
            125_default
3535 
            false
3536 
            N/A
3537 
            false
3538 
            0
3539 
            false
3540 
            Absolute
3541 
            false
3542 
            true
3543 
            0
3544 
            Kilobytes
3545 
            false
3546 
            false
3547 
            false
3548 
            false
3549 
            false
3550 
            false
3551 
            false
3552 
            Kilobytes
3553 
            0
3554 
            0
3555 
            false
3556 
            false
3557 
            false
3558 
            Kilobytes
3559 
            false
3560 
            true
3561 
            false
3562 
            4
3563 
            false
3564 
            false
3565 
            Range_B
3566 
            true
3567 
            Kilobytes
3568 
            ABB3
3569 
            N/A
3570 
            true
3571 
            X4
3572 
            false
3573 
            Megabytes
3574 
            false
3575 
            0
3576 
            0
3577 
            Memory
3578 
            0
3579 
            true
3580 
            false
3581 
            BAR_0
3582 
            Kilobytes
3583 
            false
3584 
            false
3585 
            false
3586 
            false
3587 
            0
3588 
            false
3589 
            2.5_GT/s
3590 
            false
3591 
            true
3592 
            false
3593 
            None
3594 
            None
3595 
            3FF
3596 
            false
3597 
            No_function_number_bits_used
3598 
            00
3599 
            2
3600 
            false
3601 
            false
3602 
            0
3603 
            false
3604 
            0
3605 
            INTA
3606 
            64_byte
3607 
            0
3608 
            false
3609 
            false
3610 
            Memory
3611 
            06
3612 
            false
3613 
            BAR_0
3614 
            1_vector
3615 
            false
3616 
            0
3617 
            0
3618 
            0084
3619 
            false
3620 
            0000
3621 
            00
3622 
            false
3623 
            00000000
3624 
            true
3625 
            true
3626 
            No_limit
3627 
            Disabled
3628 
            false
3629 
            Generic_XT_compatible_serial_controller
3630 
            0
3631 
            2
3632 
            false
3633
3634
3635
3636
3637 
                  coregen
3638 
                  ./
3639 
                  ./tmp/
3640 
                  ./tmp/_cg/
3641
3642
3643 
                  xc6vlx240t
3644 
                  virtex6
3645 
                  ff1156
3646 
                  -1
3647
3648
3649 
                  BusFormatAngleBracketNotRipped
3650 
                  VHDL
3651 
                  true
3652 
                  Foundation_ISE
3653 
                  false
3654 
                  false
3655 
                  false
3656 
                  Ngc
3657 
                  false
3658
3659
3660 
                  Behavioral
3661 
                  VHDL_and_Verilog
3662 
                  false
3663
3664
3665
3666
3667
3668 
         v6_pkt_counter_1024
3669
3670
3671 
            v6_pkt_counter_1024
3672 
            Independent_Clocks_Distributed_RAM
3673 
            Native
3674 
            Standard_FIFO
3675 
            1
3676 
            1024
3677 
            1
3678 
            1024
3679 
            false
3680 
            false
3681 
            true
3682 
            true
3683 
            Asynchronous_Reset
3684 
            1
3685 
            true
3686 
            0
3687 
            false
3688 
            false
3689 
            false
3690 
            Active_High
3691 
            false
3692 
            Active_High
3693 
            false
3694 
            Active_High
3695 
            false
3696 
            Active_High
3697 
            false
3698 
            false
3699 
            false
3700 
            false
3701 
            10
3702 
            false
3703 
            10
3704 
            false
3705 
            10
3706 
            false
3707 
            1
3708 
            1
3709 
            Single_Programmable_Full_Threshold_Constant
3710 
            1016
3711 
            1015
3712 
            Single_Programmable_Empty_Threshold_Constant
3713 
            2
3714 
            3
3715 
            AXI4_Stream
3716 
            Common_Clock
3717 
            false
3718 
            Slave_Interface_Clock_Enable
3719 
            false
3720 
            false
3721 
            4
3722 
            32
3723 
            64
3724 
            false
3725 
            1
3726 
            false
3727 
            1
3728 
            false
3729 
            1
3730 
            false
3731 
            1
3732 
            false
3733 
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3738 
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3740 
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3745 
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3746 
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3767 
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3768 
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3821 
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3824 
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3826 
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3827 
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3828 
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3829 
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3830 
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3831 
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3832 
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3833 
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3834 
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3835 
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3836 
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3856
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3867
3868 
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3869 
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3870 
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3871
3872
3873 
                  2011-03-14T07:12:32.000Z
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3876
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3878
3879 
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3881
3882 
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3885 
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3886 
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3887 
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3888 
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3889 
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3890 
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3891 
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3892 
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3893 
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3894 
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3896 
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3900 
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3903 
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3904 
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3910 
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3913 
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3914 
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3915 
            false
3916 
            9
3917 
            false
3918 
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3919 
            125
3920 
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3921 
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3922 
            495
3923 
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3924 
            5
3925 
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3926 
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3927 
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3928 
            false
3929 
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3930 
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3931 
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3951 
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3955 
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3956 
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3957 
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3958 
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3959 
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3960 
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3961 
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3962 
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3964 
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3965 
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3966 
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3967 
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3968 
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3970 
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3978 
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3990 
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3991 
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3992 
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3993 
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3994 
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3999 
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4001 
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4011 
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4012 
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4014 
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4015 
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4016 
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4017 
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4018 
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4020 
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4021 
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4022 
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4023 
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4024 
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4025 
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4026 
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4027 
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4030 
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4031 
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4032 
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4034 
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4037 
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4040 
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4042 
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4043 
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4044 
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4045 
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4047 
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                  2011-03-14T07:12:32.000Z
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4091
4092
4093 
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4094 
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4095 
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4096 
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4097 
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4098 
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4100 
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4101 
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4102 
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4111 
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4112 
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4125 
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4126 
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4127 
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4128 
            false
4129 
            1
4130 
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4131 
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4132 
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4134 
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4135 
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4136 
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4137 
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4138 
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4139 
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4140 
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4141 
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4142 
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4146 
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4210 
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4225 
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4230 
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4231 
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4232 
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4253 
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4256 
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4260 
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4290 
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4292 
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4318 
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4320 
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