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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [coregen.cgp] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba
# Date: Mon Mar 26 13:31:46 2012
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Structural
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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SET workingdirectory = .\tmp\
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# CRC: f536b513

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