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                    Core Name: Xilinx LogiCORE FIFO Generator
                    Version: 8.3
                    Release Date: October 19, 2011
 
 
================================================================================
 
This document contains the following sections:
 
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
 
================================================================================
 
1. INTRODUCTION
 
For installation instructions for this release, please go to:
 
   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
 
For system requirements:
 
   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
 
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2
solution. For the latest core updates, see the product page at:
 
   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
 
 
2. NEW FEATURES
 
   - ISE 13.3 software support
   - QVirtex-6L device support
 
3. SUPPORTED DEVICES
 
   The following device families are supported by the core for this release.
 
   - Zynq-7000*
 
   - Virtex-7
   - Virtex-7 XT (7vx485t)
   - Virtex-7 -2L
 
   - Kintex-7
   - Kintex-7 -2L
 
   - Artix-7*
 
   - Virtex-6 XC CXT/LXT/SXT/HXT
   - Virtex-6 XQ LXT/SXT
   - Virtex-6 -1L XC LXT/SXT
 
   - Spartan-6 XC LX/LXT
   - Spartan-6 XA
   - Spartan-6 XQ LX/LXT
   - Spartan-6 -1L XC LX
 
   - Virtex-5 XC LX/LXT/SXT/TXT/FXT
   - Virtex-5 XQ LX/ LXT/SXT/FXT
 
   - Virtex-4 XC LX/SX/FX
   - Virtex-4 XQ LX/SX/FX
   - Virtex-4 XQR LX/SX/FX
 
   - Spartan-3 XC
   - Spartan-3 XA
   - Spartan-3A XC 3A / 3A DSP / 3AN DSP
   - Spartan-3A XA 3A / 3A DSP
   - Spartan-3E XC
   - Spartan-3E XA
 
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
 
4. RESOLVED ISSUES
 
 
5. KNOWN ISSUES
 
   The following are known issues for v8.2 of this core at time of release:
 
   - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
     into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
     page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
     - CR 467240
     - AR 31379
 
   - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
     correct behavior of the FIFO status flags cannot be guaranteed after the first write.
 
     Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
     For more information and additional workaround see Answer Record 41099.
 
 
   The most recent information, including known issues, workarounds, and
   resolutions for this version is provided in the IP Release Notes User Guide
   located at
 
   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
 
 
6. TECHNICAL SUPPORT
 
   To obtain technical support, create a WebCase at www.xilinx.com/support.
   Questions are routed to a team with expertise using this product.
 
   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.
 
 
7. CORE RELEASE HISTORY
 
Date        By            Version      Description
================================================================================
09/28/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L and QSpartan-6 device support
06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
================================================================================
 
8. Legal Disclaimer
 
 (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
 
 This file contains confidential and proprietary information
 of Xilinx, Inc. and is protected under U.S. and
 international copyright and other intellectual property
 laws.
 
 DISCLAIMER
 This disclaimer is not a license and does not grant any
 rights to the materials distributed herewith. Except as
 otherwise provided in a valid license issued to you by
 Xilinx, and to the maximum extent permitted by applicable
 law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 (2) Xilinx shall not be liable (whether in contract or tort,
 including negligence, or under any other theory of
 liability) for any loss or damage of any kind or nature
 related to, arising under or in connection with these
 materials, including for any direct, or any indirect,
 special, incidental, or consequential loss or damage
 (including loss of data, profits, goodwill, or any type of
 loss or damage suffered as a result of any action brought
 by a third party) even if such damage or loss was
 reasonably foreseeable or Xilinx had been advised of the
 possibility of the same.
 
 CRITICAL APPLICATIONS
 Xilinx products are not designed or intended to be fail-
 safe, or for use in any application requiring fail-safe
 performance, such as life-support or safety devices or
 systems, Class III medical devices, nuclear facilities,
 applications related to the deployment of airbags, or any
 other applications that could lead to death, personal
 injury, or severe property or environmental damage
 (individually and collectively, "Critical
 Applications"). Customer assumes the sole risk and
 liability of any use of Xilinx products in Critical
 Applications, subject only to applicable laws and
 regulations governing limitations on product liability.
 
 THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 PART OF THIS FILE AT ALL TIMES.

Line No.	Rev	Author	Line
1	13	barabba	`Core Name: Xilinx LogiCORE FIFO Generator`
2			`Version: 8.3`
3			`Release Date: October 19, 2011`
4
5
6			`================================================================================`
7
8			`This document contains the following sections:`
9
10			`1. Introduction`
11			`2. New Features`
12			`3. Supported Devices`
13			`4. Resolved Issues`
14			`5. Known Issues`
15			`6. Technical Support`
16			`7. Core Release History`
17			`8. Legal Disclaimer`
18
19			`================================================================================`
20
21			`1. INTRODUCTION`
22
23			`For installation instructions for this release, please go to:`
24
25			`http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm`
26
27			`For system requirements:`
28
29			`http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm`
30
31			`This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2`
32			`solution. For the latest core updates, see the product page at:`
33
34			`http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm`
35
36
37			`2. NEW FEATURES`
38
39			`- ISE 13.3 software support`
40			`- QVirtex-6L device support`
41
42			`3. SUPPORTED DEVICES`
43
44			`The following device families are supported by the core for this release.`
45
46			`- Zynq-7000*`
47
48			`- Virtex-7`
49			`- Virtex-7 XT (7vx485t)`
50			`- Virtex-7 -2L`
51
52			`- Kintex-7`
53			`- Kintex-7 -2L`
54
55			`- Artix-7*`
56
57			`- Virtex-6 XC CXT/LXT/SXT/HXT`
58			`- Virtex-6 XQ LXT/SXT`
59			`- Virtex-6 -1L XC LXT/SXT`
60
61			`- Spartan-6 XC LX/LXT`
62			`- Spartan-6 XA`
63			`- Spartan-6 XQ LX/LXT`
64			`- Spartan-6 -1L XC LX`
65
66			`- Virtex-5 XC LX/LXT/SXT/TXT/FXT`
67			`- Virtex-5 XQ LX/ LXT/SXT/FXT`
68
69			`- Virtex-4 XC LX/SX/FX`
70			`- Virtex-4 XQ LX/SX/FX`
71			`- Virtex-4 XQR LX/SX/FX`
72
73			`- Spartan-3 XC`
74			`- Spartan-3 XA`
75			`- Spartan-3A XC 3A / 3A DSP / 3AN DSP`
76			`- Spartan-3A XA 3A / 3A DSP`
77			`- Spartan-3E XC`
78			`- Spartan-3E XA`
79
80			`*To access these devices in the ISE Design Suite, contact your Xilinx FAE.`
81
82			`4. RESOLVED ISSUES`
83
84
85			`5. KNOWN ISSUES`
86
87			`The following are known issues for v8.2 of this core at time of release:`
88
89			`- In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)`
90			`into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,`
91			`page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.`
92			`- CR 467240`
93			`- AR 31379`
94
95			`- When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,`
96			`correct behavior of the FIFO status flags cannot be guaranteed after the first write.`
97
98			`Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.`
99			`For more information and additional workaround see Answer Record 41099.`
100
101
102			`The most recent information, including known issues, workarounds, and`
103			`resolutions for this version is provided in the IP Release Notes User Guide`
104			`located at`
105
106			`www.xilinx.com/support/documentation/user_guides/xtp025.pdf`
107
108
109			`6. TECHNICAL SUPPORT`
110
111			`To obtain technical support, create a WebCase at www.xilinx.com/support.`
112			`Questions are routed to a team with expertise using this product.`
113
114			`Xilinx provides technical support for use of this product when used`
115			`according to the guidelines described in the core documentation, and`
116			`cannot guarantee timing, functionality, or support of this product for`
117			`designs that do not follow specified guidelines.`
118
119
120			`7. CORE RELEASE HISTORY`
121
122			`Date By Version Description`
123			`================================================================================`
124			`09/28/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L and QSpartan-6 device support`
125			`06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support`
126			`03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support`
127			`10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support`
128			`09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support`
129			`07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support`
130			`06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support`
131			`04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support`
132			`12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support`
133			`09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support`
134			`06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support`
135			`04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support`
136			`09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes`
137			`03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes`
138			`10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs`
139			`08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO`
140			`04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support`
141			`09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support`
142			`07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support`
143			`01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3`
144			`08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2`
145			`04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1`
146			`11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0`
147			`05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support`
148			`04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release`
149			`================================================================================`
150
151			`8. Legal Disclaimer`
152
153			`(c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.`
154
155			`This file contains confidential and proprietary information`
156			`of Xilinx, Inc. and is protected under U.S. and`
157			`international copyright and other intellectual property`
158			`laws.`
159
160			`DISCLAIMER`
161			`This disclaimer is not a license and does not grant any`
162			`rights to the materials distributed herewith. Except as`
163			`otherwise provided in a valid license issued to you by`
164			`Xilinx, and to the maximum extent permitted by applicable`
165			`law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
166			`WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
167			`AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
168			`BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
169			`INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
170			`(2) Xilinx shall not be liable (whether in contract or tort,`
171			`including negligence, or under any other theory of`
172			`liability) for any loss or damage of any kind or nature`
173			`related to, arising under or in connection with these`
174			`materials, including for any direct, or any indirect,`
175			`special, incidental, or consequential loss or damage`
176			`(including loss of data, profits, goodwill, or any type of`
177			`loss or damage suffered as a result of any action brought`
178			`by a third party) even if such damage or loss was`
179			`reasonably foreseeable or Xilinx had been advised of the`
180			`possibility of the same.`
181
182			`CRITICAL APPLICATIONS`
183			`Xilinx products are not designed or intended to be fail-`
184			`safe, or for use in any application requiring fail-safe`
185			`performance, such as life-support or safety devices or`
186			`systems, Class III medical devices, nuclear facilities,`
187			`applications related to the deployment of airbags, or any`
188			`other applications that could lead to death, personal`
189			`injury, or severe property or environmental damage`
190			`(individually and collectively, "Critical`
191			`Applications"). Customer assumes the sole risk and`
192			`liability of any use of Xilinx products in Critical`
193			`Applications, subject only to applicable laws and`
194			`regulations governing limitations on product liability.`
195
196			`THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
197			`PART OF THIS FILE AT ALL TIMES.`

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [fifo_generator_v8_3_readme.txt] - Blame information for rev 13