URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [tmp/] [_xmsgs/] [netgen.xmsgs] - Blame information for rev 13

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1	13	barabba
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8			`The generated VHDL netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM library for correct compilation and simulation.`
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