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-------------------------------------------------------------------------------

-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : EP_MEM.vhd

-- Version    : 1.7

--

-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.

--              Block RAM Port A: Read Port

--              Block RAM Port B: Write Port

--

--------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity EP_MEM is port (

  clk_i : in std_logic ;

  a_rd_a_i_0 : in std_logic_vector(8 downto 0);

  a_rd_d_o_0 : out std_logic_vector(31 downto 0);

  a_rd_en_i_0 : in std_logic ;

  b_wr_a_i_0 : in std_logic_vector(8 downto 0);

  b_wr_d_i_0 : in std_logic_vector(31 downto 0);

  b_wr_en_i_0 : in std_logic ;

  b_rd_d_o_0 : out std_logic_vector(31 downto 0);

  b_rd_en_i_0 : in std_logic ;

  a_rd_a_i_1 : in std_logic_vector(8 downto 0);

  a_rd_d_o_1 : out std_logic_vector(31 downto 0);

  a_rd_en_i_1 : in std_logic ;

  b_wr_a_i_1 : in std_logic_vector(8 downto 0);

  b_wr_d_i_1 : in std_logic_vector(31 downto 0);

  b_wr_en_i_1 : in std_logic ;

  b_rd_d_o_1 : out std_logic_vector(31 downto 0);

  b_rd_en_i_1 : in std_logic ;

  a_rd_a_i_2 : in std_logic_vector(8 downto 0);

  a_rd_d_o_2 : out std_logic_vector(31 downto 0);

  a_rd_en_i_2 : in std_logic ;

  b_wr_a_i_2 : in std_logic_vector(8 downto 0);

  b_wr_d_i_2 : in std_logic_vector(31 downto 0);

  b_wr_en_i_2 : in std_logic ;

  b_rd_d_o_2 : out std_logic_vector(31 downto 0);

  b_rd_en_i_2 : in std_logic ;

  a_rd_a_i_3 : in std_logic_vector(8 downto 0);

  a_rd_d_o_3 : out std_logic_vector(31 downto 0);

  a_rd_en_i_3 : in std_logic ;

  b_wr_a_i_3 : in std_logic_vector(8 downto 0);

  b_wr_d_i_3 : in std_logic_vector(31 downto 0);

  b_wr_en_i_3 : in std_logic ;

  b_rd_d_o_3 : out std_logic_vector(31 downto 0);

  b_rd_en_i_3 : in std_logic

);

end EP_MEM;

architecture rtl of EP_MEM is

begin

------------------------------------------------------------------

--

--  4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)

--

------------------------------------------------------------------

ep_mem_0 : RAMB16_S36_S36

generic map (

  SIM_COLLISION_CHECK => "NONE"

)

port map (

  CLKA =>  clk_i,

  SSRA  => '0',

  ADDRA =>  a_rd_a_i_0,

  DIA =>   X"00000000",

  DIPA =>  X"0",

  DOA =>   a_rd_d_o_0,

  DOPA =>  open,

  ENA =>   a_rd_en_i_0,

  WEA =>   '0',

  CLKB =>  clk_i,

  SSRB =>  '0',

  ADDRB => b_wr_a_i_0,

  DIB  =>  b_wr_d_i_0,

  DIPB =>  X"0",

  DOB  =>  b_rd_d_o_0,

  DOPB =>  open,

  ENB  =>  b_rd_en_i_0,

  WEB   => b_wr_en_i_0

);

ep_mem_1 : RAMB16_S36_S36

generic map (

  SIM_COLLISION_CHECK => "NONE"

)

port map (

  CLKA =>  clk_i,

  SSRA =>  '0',

  ADDRA => a_rd_a_i_1,

  DIA  =>  X"00000000",

  DIPA =>  X"0",

  DOA  =>  a_rd_d_o_1,

  DOPA =>  open,

  ENA  =>  a_rd_en_i_1,

  WEA =>   '0',

  CLKB =>  clk_i,

  SSRB =>  '0',

  ADDRB => b_wr_a_i_1,

  DIB  =>  b_wr_d_i_1,

  DIPB =>  X"0",

  DOB  =>  b_rd_d_o_1,

  DOPB =>  open,

  ENB  =>  b_rd_en_i_1,

  WEB  =>  b_wr_en_i_1

);

ep_mem_2 : RAMB16_S36_S36

generic map (

  SIM_COLLISION_CHECK => "NONE"

)

port map (

  CLKA =>  clk_i,

  SSRA =>  '0',

  ADDRA => a_rd_a_i_2,

  DIA  =>  X"00000000",

  DIPA =>  X"0",

  DOA =>   a_rd_d_o_2,

  DOPA =>  open,

  ENA =>   a_rd_en_i_2,

  WEA  =>  '0',

  CLKB =>  clk_i,

  SSRB =>  '0',

  ADDRB => b_wr_a_i_2,

  DIB =>   b_wr_d_i_2,

  DIPB =>  X"0",

  DOB  =>  b_rd_d_o_2,

  DOPB =>  open,

  ENB =>   b_rd_en_i_2,

  WEB =>   b_wr_en_i_2

);

ep_mem_3 : RAMB16_S36_S36

generic map (

  SIM_COLLISION_CHECK => "NONE"

)

port map (

  CLKA  => clk_i,

  SSRA =>  '0',

  ADDRA => a_rd_a_i_3,

  DIA =>   X"00000000",

  DIPA =>  X"0",

  DOA  =>  a_rd_d_o_3,

  DOPA =>  open,

  ENA  =>  a_rd_en_i_3,

  WEA  =>  '0',

  CLKB =>  clk_i,

  SSRB =>  '0',

  ADDRB => b_wr_a_i_3,

  DIB => b_wr_d_i_3,

  DIPB =>  X"0",

  DOB  =>  b_rd_d_o_3,

  DOPB =>  open,

  ENB  =>  b_rd_en_i_3 ,

  WEB  =>  b_wr_en_i_3

);

end; -- EP_MEM