Subversion Repositories pcie_sg_dma

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## Project    : Virtex-6 Integrated Block for PCI Express

## File       : xilinx_pcie_2_0_ep_v6_04_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf

## Version    : 1.7

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# Define Device, Package And Speed Grade

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CONFIG PART = xc6vlx240t-ff1156-1;

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# User Time Names / User Time Groups / Time Specs

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# User Physical Constraints

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# Pinout and Related I/O Constraints

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#

# SYS reset (input) signal.  The sys_reset_n signal should be

# obtained from the PCI Express interface if possible.  For

# slot based form factors, a system reset signal is usually

# present on the connector.  For cable based form factors, a

# system reset signal may not be available.  In this case, the

# system reset signal must be generated locally by some form of

# supervisory circuit.  You may change the IOSTANDARD and LOC

# to suit your requirements and VCCO voltage banking rules.

#

NET "sys_reset_n" TIG;

NET "sys_reset_n" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#

#

# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n

# signals are the PCI Express reference clock. Virtex-6 GT

# Transceiver architecture requires the use of a dedicated clock

# resources (FPGA input pins) associated with each GT Transceiver.

# To use these pins an IBUFDS primitive (refclk_ibuf) is

# instantiated in user's design.

# Please refer to the Virtex-6 GT Transceiver User Guide

# (UG) for guidelines regarding clock resource selection.

#

#NET "sys_clk_p" LOC = P6;

#NET "sys_clk_n" LOC = P5;

INST "refclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;

#

# Transceiver instance placement.  This constraint selects the

# transceivers to be used, which also dictates the pinout for the

# transmit and receive differential pairs.  Please refer to the

# Virtex-6 GT Transceiver User Guide (UG) for more information.

#

# PCIe Lane 0

INST "core*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;

# PCIe Lane 1

INST "core*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX" LOC = GTXE1_X0Y14;

# PCIe Lane 2

INST "core*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX" LOC = GTXE1_X0Y13;

# PCIe Lane 3

INST "core*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX" LOC = GTXE1_X0Y12;

#

# PCI Express Block placement. This constraint selects the PCI Express

# Block to be used.

#

INST "core*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;

#NET  "led_0"           LOC = "AC22"   ;

#NET  "led_1"           LOC = "AC24"   ;

#NET  "led_2"           LOC = "AE22"  ;

#

# MMCM Placment. This constraint selects the MMCM Placement

#

INST "core*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;

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# Timing Constraints

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#

# Timing requirements and related constraints.

#

NET "sys_clk_c" TNM_NET = "SYSCLK" ;

NET "core*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;

NET "core*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";

TIMESPEC "TS_SYSCLK"  = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ;

TIMESPEC "TS_CLK_125"  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ;

TIMESPEC "TS_TXOUTCLKBUFG"  = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ;

PIN "core*/trn_reset_n_int_i.CLR" TIG ;

PIN "core*/trn_reset_n_i.CLR" TIG ;

PIN "core*/pcie_clocking_i/mmcm_adv_i.RST" TIG ;

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# Physical Constraints

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# End

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