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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_6/] [simulation/] [dsport/] [pci_exp_usrapp_rx.v] - Blame information for rev 13

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//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project    : Virtex-6 Integrated Block for PCI Express
// File       : pci_exp_usrapp_rx.v
// Version    : 1.7
//--
//--------------------------------------------------------------------------------
 
`include "board_common.v"
 
`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
module pci_exp_usrapp_rx                   (
 
                                           trn_rdst_rdy_n,
                                           trn_rnp_ok_n,
 
                                           trn_rd,
                                           trn_rrem_n,
                                           trn_rsof_n,
                                           trn_reof_n,
                                           trn_rsrc_rdy_n,
                                           trn_rsrc_dsc_n,
                                           trn_rerrfwd_n,
                                           trn_rbar_hit_n,
 
                                           trn_clk,
                                           trn_reset_n,
                                           trn_lnk_up_n
 
                                           );
 
output                                     trn_rdst_rdy_n;
output                                     trn_rnp_ok_n;
 
input    [(64 - 1):0]                      trn_rd;
input    [(8 - 1):0]                       trn_rrem_n;
input                                      trn_rsof_n;
input                                      trn_reof_n;
input                                      trn_rsrc_rdy_n;
input                                      trn_rsrc_dsc_n;
input                                      trn_rerrfwd_n;
input  [(7 - 1):0]                         trn_rbar_hit_n;
 
input                                      trn_clk;
input                                      trn_reset_n;
input                                      trn_lnk_up_n;
 
parameter                                   Tcq = 1;
 
/* Output variables */
 
reg               trn_rdst_rdy_n, next_trn_rdst_rdy_n;
reg               trn_rnp_ok_n, next_trn_rnp_ok_n;
 
/* Local variables */
 
reg     [4:0]     trn_rx_state, next_trn_rx_state;
reg               trn_rx_in_frame, next_trn_rx_in_frame;
reg               trn_rx_in_channel, next_trn_rx_in_channel;
 
reg     [31:0]    next_trn_rx_timeout;
 
/* State variables */
 
`define           TRN_RX_RESET    5'b00001
`define           TRN_RX_DOWN     5'b00010
`define           TRN_RX_IDLE     5'b00100
`define           TRN_RX_ACTIVE   5'b01000
`define           TRN_RX_SRC_DSC  5'b10000
 
 
/* Transaction Receive User Interface State Machine */
 
 
always @(posedge trn_clk or negedge trn_reset_n) begin
 
  if (trn_reset_n == 1'b0) begin
 
    trn_rx_state     <= #(Tcq)  `TRN_RX_RESET;
 
  end else begin
 
  case (trn_rx_state)
 
    `TRN_RX_RESET :  begin
 
      if (trn_reset_n == 1'b0)
 
        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
 
      else
 
        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
    end
 
    `TRN_RX_DOWN : begin
 
      if (trn_lnk_up_n == 1'b1)
 
        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
 
      else begin
 
        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
      end
 
    end
 
    `TRN_RX_IDLE : begin
 
      if (trn_reset_n == 1'b0)
 
        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
 
      else if (trn_lnk_up_n == 1'b1)
 
        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
 
      else begin
 
        if (  (trn_rsof_n == 1'b0) &&
              (trn_rsrc_rdy_n == 1'b0) &&
               (trn_rdst_rdy_n == 1'b0)  ) begin
 
          board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
 
          trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
 
        end else begin
 
          trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
 
        end
      end
 
    end
 
    `TRN_RX_ACTIVE : begin
 
      if (trn_reset_n == 1'b0)
 
        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
 
      else if (trn_lnk_up_n == 1'b1)
 
        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
 
      else if (  (trn_rsrc_rdy_n == 1'b0) &&
                (trn_reof_n == 1'b0) &&
                 (trn_rdst_rdy_n == 1'b0)  ) begin
 
        board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
        board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
 
        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
 
      end else if (  (trn_rsrc_rdy_n == 1'b0) &&
                     (trn_rdst_rdy_n == 1'b0)  ) begin
 
        board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
 
        trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
 
      end else if (  (trn_rsrc_rdy_n == 1'b0) &&
          (trn_reof_n == 1'b0) &&
          (trn_rsrc_dsc_n == 1'b0)  ) begin
 
        board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
        board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
 
        trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
 
      end else begin
 
        trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
      end
 
    end
 
    `TRN_RX_SRC_DSC : begin
 
      if (trn_reset_n == 1'b0)
 
        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
 
      else if (trn_lnk_up_n == 1'b1)
 
        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
 
      else begin
 
        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
 
      end
    end
 
  endcase
 
   end
 
end
 
reg [1:0]   trn_rdst_rdy_toggle_count;
reg [8:0]   trn_rnp_ok_toggle_count;
 
always @(posedge trn_clk or negedge trn_reset_n) begin
 
   if (trn_reset_n == 1'b0) begin
 
    trn_rnp_ok_n        <= #(Tcq)   1'b0;
    trn_rdst_rdy_n      <= #(Tcq)       1'b0;
    trn_rdst_rdy_toggle_count <= #(Tcq) $random;
    trn_rnp_ok_toggle_count <=  #(Tcq)     $random;
 
   end else begin
 
    if (trn_rnp_ok_toggle_count == 0) begin
 
        trn_rnp_ok_n        <= #(Tcq)   !trn_rnp_ok_n;
        trn_rnp_ok_toggle_count <=  #(Tcq)     $random;
 
    end else begin
 
        //trn_rnp_ok_toggle_count   <=  #(Tcq)     trn_rnp_ok_toggle_count - 1;
 
    end
 
    if (trn_rdst_rdy_toggle_count == 0) begin
 
        //trn_rdst_rdy_n      <= #(Tcq)       !trn_rdst_rdy_n;
        trn_rdst_rdy_toggle_count <= #(Tcq) $random;
 
    end else begin
 
        //trn_rdst_rdy_toggle_count <= trn_rdst_rdy_toggle_count - 1;
    end
 
   end
 
end
 
reg [31:0] sim_timeout;
initial
begin
  sim_timeout = `TRN_RX_TIMEOUT;
end
 
/* Transaction Receive Timeout */
 
always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin
 
    if (next_trn_rx_timeout == 0) begin
        if(!`EXPECT_FINISH_CHECK)
          $display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
 
        $finish(2);
    end
 
    if ((trn_rsof_n == 1'b0) && (trn_rsrc_rdy_n == 1'b0)) begin
 
        next_trn_rx_timeout = sim_timeout;
 
    end else begin
 
        if (trn_lnk_up_n == 1'b0)
 
            next_trn_rx_timeout = next_trn_rx_timeout - 1'b1;
 
    end
 
end
 
endmodule // pci_exp_usrapp_rx
 

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_6/] [simulation/] [dsport/] [pci_exp_usrapp_rx.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	barabba
2			`//-----------------------------------------------------------------------------`
3			`//`
4			`// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.`
5			`//`
6			`// This file contains confidential and proprietary information`
7			`// of Xilinx, Inc. and is protected under U.S. and`
8			`// international copyright and other intellectual property`
9			`// laws.`
10			`//`
11			`// DISCLAIMER`
12			`// This disclaimer is not a license and does not grant any`
13			`// rights to the materials distributed herewith. Except as`
14			`// otherwise provided in a valid license issued to you by`
15			`// Xilinx, and to the maximum extent permitted by applicable`
16			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
17			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
18			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
19			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
20			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
21			`// (2) Xilinx shall not be liable (whether in contract or tort,`
22			`// including negligence, or under any other theory of`
23			`// liability) for any loss or damage of any kind or nature`
24			`// related to, arising under or in connection with these`
25			`// materials, including for any direct, or any indirect,`
26			`// special, incidental, or consequential loss or damage`
27			`// (including loss of data, profits, goodwill, or any type of`
28			`// loss or damage suffered as a result of any action brought`
29			`// by a third party) even if such damage or loss was`
30			`// reasonably foreseeable or Xilinx had been advised of the`
31			`// possibility of the same.`
32			`//`
33			`// CRITICAL APPLICATIONS`
34			`// Xilinx products are not designed or intended to be fail-`
35			`// safe, or for use in any application requiring fail-safe`
36			`// performance, such as life-support or safety devices or`
37			`// systems, Class III medical devices, nuclear facilities,`
38			`// applications related to the deployment of airbags, or any`
39			`// other applications that could lead to death, personal`
40			`// injury, or severe property or environmental damage`
41			`// (individually and collectively, "Critical`
42			`// Applications"). Customer assumes the sole risk and`
43			`// liability of any use of Xilinx products in Critical`
44			`// Applications, subject only to applicable laws and`
45			`// regulations governing limitations on product liability.`
46			`//`
47			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
48			`// PART OF THIS FILE AT ALL TIMES.`
49			`//`
50			`//-----------------------------------------------------------------------------`
51			`// Project : Virtex-6 Integrated Block for PCI Express`
52			`// File : pci_exp_usrapp_rx.v`
53			`// Version : 1.7`
54			`//--`
55			`//--------------------------------------------------------------------------------`
56
57			`include "board_common.v"
58
59			`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
60			`module pci_exp_usrapp_rx (`
61
62			`trn_rdst_rdy_n,`
63			`trn_rnp_ok_n,`
64
65			`trn_rd,`
66			`trn_rrem_n,`
67			`trn_rsof_n,`
68			`trn_reof_n,`
69			`trn_rsrc_rdy_n,`
70			`trn_rsrc_dsc_n,`
71			`trn_rerrfwd_n,`
72			`trn_rbar_hit_n,`
73
74			`trn_clk,`
75			`trn_reset_n,`
76			`trn_lnk_up_n`
77
78			`);`
79
80			`output trn_rdst_rdy_n;`
81			`output trn_rnp_ok_n;`
82
83			`input [(64 - 1):0] trn_rd;`
84			`input [(8 - 1):0] trn_rrem_n;`
85			`input trn_rsof_n;`
86			`input trn_reof_n;`
87			`input trn_rsrc_rdy_n;`
88			`input trn_rsrc_dsc_n;`
89			`input trn_rerrfwd_n;`
90			`input [(7 - 1):0] trn_rbar_hit_n;`
91
92			`input trn_clk;`
93			`input trn_reset_n;`
94			`input trn_lnk_up_n;`
95
96			`parameter Tcq = 1;`
97
98			`/* Output variables */`
99
100			`reg trn_rdst_rdy_n, next_trn_rdst_rdy_n;`
101			`reg trn_rnp_ok_n, next_trn_rnp_ok_n;`
102
103			`/* Local variables */`
104
105			`reg [4:0] trn_rx_state, next_trn_rx_state;`
106			`reg trn_rx_in_frame, next_trn_rx_in_frame;`
107			`reg trn_rx_in_channel, next_trn_rx_in_channel;`
108
109			`reg [31:0] next_trn_rx_timeout;`
110
111			`/* State variables */`
112
113			`define TRN_RX_RESET 5'b00001
114			`define TRN_RX_DOWN 5'b00010
115			`define TRN_RX_IDLE 5'b00100
116			`define TRN_RX_ACTIVE 5'b01000
117			`define TRN_RX_SRC_DSC 5'b10000
118
119
120			`/* Transaction Receive User Interface State Machine */`
121
122
123			`always @(posedge trn_clk or negedge trn_reset_n) begin`
124
125			`if (trn_reset_n == 1'b0) begin`
126
127			trn_rx_state <= #(Tcq) `TRN_RX_RESET;
128
129			`end else begin`
130
131			`case (trn_rx_state)`
132
133			`TRN_RX_RESET : begin
134
135			`if (trn_reset_n == 1'b0)`
136
137			trn_rx_state <= #(Tcq) `TRN_RX_RESET;
138
139			`else`
140
141			trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
142			`end`
143
144			`TRN_RX_DOWN : begin
145
146			`if (trn_lnk_up_n == 1'b1)`
147
148			trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
149
150			`else begin`
151
152			trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
153			`end`
154
155			`end`
156
157			`TRN_RX_IDLE : begin
158
159			`if (trn_reset_n == 1'b0)`
160
161			trn_rx_state <= #(Tcq) `TRN_RX_RESET;
162
163			`else if (trn_lnk_up_n == 1'b1)`
164
165			trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
166
167			`else begin`
168
169			`if ( (trn_rsof_n == 1'b0) &&`
170			`(trn_rsrc_rdy_n == 1'b0) &&`
171			`(trn_rdst_rdy_n == 1'b0) ) begin`
172
173			board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
174
175			trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
176
177			`end else begin`
178
179			trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
180
181			`end`
182			`end`
183
184			`end`
185
186			`TRN_RX_ACTIVE : begin
187
188			`if (trn_reset_n == 1'b0)`
189
190			trn_rx_state <= #(Tcq) `TRN_RX_RESET;
191
192			`else if (trn_lnk_up_n == 1'b1)`
193
194			trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
195
196			`else if ( (trn_rsrc_rdy_n == 1'b0) &&`
197			`(trn_reof_n == 1'b0) &&`
198			`(trn_rdst_rdy_n == 1'b0) ) begin`
199
200			board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
201			board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
202
203			trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
204
205			`end else if ( (trn_rsrc_rdy_n == 1'b0) &&`
206			`(trn_rdst_rdy_n == 1'b0) ) begin`
207
208			board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
209
210			trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
211
212			`end else if ( (trn_rsrc_rdy_n == 1'b0) &&`
213			`(trn_reof_n == 1'b0) &&`
214			`(trn_rsrc_dsc_n == 1'b0) ) begin`
215
216			board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
217			board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
218
219			trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
220
221			`end else begin`
222
223			trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
224			`end`
225
226			`end`
227
228			`TRN_RX_SRC_DSC : begin
229
230			`if (trn_reset_n == 1'b0)`
231
232			trn_rx_state <= #(Tcq) `TRN_RX_RESET;
233
234			`else if (trn_lnk_up_n == 1'b1)`
235
236			trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
237
238			`else begin`
239
240			trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
241
242			`end`
243			`end`
244
245			`endcase`
246
247			`end`
248
249			`end`
250
251			`reg [1:0] trn_rdst_rdy_toggle_count;`
252			`reg [8:0] trn_rnp_ok_toggle_count;`
253
254			`always @(posedge trn_clk or negedge trn_reset_n) begin`
255
256			`if (trn_reset_n == 1'b0) begin`
257
258			`trn_rnp_ok_n <= #(Tcq) 1'b0;`
259			`trn_rdst_rdy_n <= #(Tcq) 1'b0;`
260			`trn_rdst_rdy_toggle_count <= #(Tcq) $random;`
261			`trn_rnp_ok_toggle_count <= #(Tcq) $random;`
262
263			`end else begin`
264
265			`if (trn_rnp_ok_toggle_count == 0) begin`
266
267			`trn_rnp_ok_n <= #(Tcq) !trn_rnp_ok_n;`
268			`trn_rnp_ok_toggle_count <= #(Tcq) $random;`
269
270			`end else begin`
271
272			`//trn_rnp_ok_toggle_count <= #(Tcq) trn_rnp_ok_toggle_count - 1;`
273
274			`end`
275
276			`if (trn_rdst_rdy_toggle_count == 0) begin`
277
278			`//trn_rdst_rdy_n <= #(Tcq) !trn_rdst_rdy_n;`
279			`trn_rdst_rdy_toggle_count <= #(Tcq) $random;`
280
281			`end else begin`
282
283			`//trn_rdst_rdy_toggle_count <= trn_rdst_rdy_toggle_count - 1;`
284			`end`
285
286			`end`
287
288			`end`
289
290			`reg [31:0] sim_timeout;`
291			`initial`
292			`begin`
293			sim_timeout = `TRN_RX_TIMEOUT;
294			`end`
295
296			`/* Transaction Receive Timeout */`
297
298			`always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin`
299
300			`if (next_trn_rx_timeout == 0) begin`
301			if(!`EXPECT_FINISH_CHECK)
302			`$display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);`
303
304			`$finish(2);`
305			`end`
306
307			`if ((trn_rsof_n == 1'b0) && (trn_rsrc_rdy_n == 1'b0)) begin`
308
309			`next_trn_rx_timeout = sim_timeout;`
310
311			`end else begin`
312
313			`if (trn_lnk_up_n == 1'b0)`
314
315			`next_trn_rx_timeout = next_trn_rx_timeout - 1'b1;`
316
317			`end`
318
319			`end`
320
321			`endmodule // pci_exp_usrapp_rx`
322