Subversion Repositories pcie_sg_dma

-------------------------------------------------------------------------------

--

-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.

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-------------------------------------------------------------------------------

-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : pcie_2_0_rport_v6.vhd

-- Version    : 1.7

-- Description: Virtex6 solution wrapper : Root Port for PCI Express

--

--

--

--------------------------------------------------------------------------------

library ieee;

   use ieee.std_logic_1164.all;

   use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;

entity pcie_2_0_rport_v6 is

   generic (

     REF_CLK_FREQ : integer := 0;                -- 0 - 100MHz, 1 - 125 MHz, 2 - 250 MHz

     PIPE_PIPELINE_STAGES : integer := 0;                -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages

     PCIE_DRP_ENABLE : boolean := FALSE;

     DS_PORT_HOT_RST : boolean := FALSE;               -- FALSE - for ROOT PORT(default), TRUE - for DOWNSTREAM PORT 

     LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;

     LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";

     AER_BASE_PTR : bit_vector := X"128";

     AER_CAP_ECRC_CHECK_CAPABLE : boolean := FALSE;

     AER_CAP_ECRC_GEN_CAPABLE : boolean := FALSE;

     AER_CAP_ID : bit_vector := X"1111";

     AER_CAP_INT_MSG_NUM_MSI : bit_vector := X"0A";

     AER_CAP_INT_MSG_NUM_MSIX : bit_vector := X"15";

     AER_CAP_NEXTPTR : bit_vector := X"160";

     AER_CAP_ON : boolean := FALSE;

     AER_CAP_PERMIT_ROOTERR_UPDATE : boolean := TRUE;

     AER_CAP_VERSION : bit_vector := X"1";

     ALLOW_X8_GEN2 : boolean := FALSE;

     BAR0 : bit_vector := X"00000000";          -- Memory aperture disabled

     BAR1 : bit_vector := X"00000000";          -- Memory aperture disabled

     BAR2 : bit_vector := X"00FFFFFF";          -- Constant for rport 

     BAR3 : bit_vector := X"FFFF0000";          -- IO Limit/Base Registers not implemented

     BAR4 : bit_vector := X"FFF0FFF0";          -- Constant for rport

     BAR5 : bit_vector := X"FFF1FFF1";          -- Prefetchable Memory Limit/Base Registers implemented

     CAPABILITIES_PTR : bit_vector := X"40";

     CARDBUS_CIS_POINTER : bit_vector := X"00000000";

     CLASS_CODE : bit_vector := X"060400";

     CMD_INTX_IMPLEMENTED : boolean := TRUE;

     CPL_TIMEOUT_DISABLE_SUPPORTED : boolean := FALSE;

     CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";

     CRM_MODULE_RSTS : bit_vector := X"00";

     DEVICE_ID : bit_vector := X"0007";

     DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : boolean := TRUE;

     DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : boolean := TRUE;

     DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;

     DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;

     DEV_CAP_EXT_TAG_SUPPORTED : boolean := TRUE;

     DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : boolean := FALSE;

     DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;

     DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;

     DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;

     DEV_CAP_RSVD_14_12 : integer := 0;

     DEV_CAP_RSVD_17_16 : integer := 0;

     DEV_CAP_RSVD_31_29 : integer := 0;

     DEV_CONTROL_AUX_POWER_SUPPORTED : boolean := FALSE;

     DISABLE_ASPM_L1_TIMER : boolean := FALSE;

     DISABLE_BAR_FILTERING : boolean := TRUE;

     DISABLE_ID_CHECK : boolean := TRUE;

     DISABLE_LANE_REVERSAL : boolean := FALSE;

     DISABLE_RX_TC_FILTER : boolean := TRUE;

     DISABLE_SCRAMBLING : boolean := FALSE;

     DNSTREAM_LINK_NUM : bit_vector := X"00";

     DSN_BASE_PTR : bit_vector := X"100";

     DSN_CAP_ID : bit_vector := X"0003";

     DSN_CAP_NEXTPTR : bit_vector := X"01C";

     DSN_CAP_ON : boolean := TRUE;

     DSN_CAP_VERSION : bit_vector := X"1";

     ENABLE_MSG_ROUTE : bit_vector := X"000";

     ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;

     ENTER_RVRY_EI_L0 : boolean := TRUE;

     EXIT_LOOPBACK_ON_EI : boolean := TRUE;

     EXPANSION_ROM : bit_vector := X"00000000";         -- Memory aperture disabled

     EXT_CFG_CAP_PTR : bit_vector := X"3F";

     EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";

     HEADER_TYPE : bit_vector := X"01";

     INFER_EI : bit_vector := X"0C";

     INTERRUPT_PIN : bit_vector := X"01";

     IS_SWITCH : boolean := FALSE;

     LAST_CONFIG_DWORD : bit_vector := X"042";

     LINK_CAP_ASPM_SUPPORT : integer := 1;

     LINK_CAP_CLOCK_POWER_MANAGEMENT : boolean := FALSE;

     LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : boolean := FALSE;

     LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;

     LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;

     LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;

     LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;

     LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;

     LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;

     LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;

     LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;

     LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean := FALSE;

     LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";

     LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";

     LINK_CAP_RSVD_23_22 : integer := 0;

     LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : boolean := FALSE;

     LINK_CONTROL_RCB : integer := 0;

     LINK_CTRL2_DEEMPHASIS : boolean := FALSE;

     LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : boolean := FALSE;

     LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";

     LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := TRUE;

     LL_ACK_TIMEOUT : bit_vector := X"0000";

     LL_ACK_TIMEOUT_EN : boolean := FALSE;

     LL_ACK_TIMEOUT_FUNC : integer := 0;

     LL_REPLAY_TIMEOUT : bit_vector := X"0000";

     LL_REPLAY_TIMEOUT_EN : boolean := FALSE;

     LL_REPLAY_TIMEOUT_FUNC : integer := 0;

     MSIX_BASE_PTR : bit_vector := X"9C";

     MSIX_CAP_ID : bit_vector := X"11";

     MSIX_CAP_NEXTPTR : bit_vector := X"00";

     MSIX_CAP_ON : boolean := TRUE;

     MSIX_CAP_PBA_BIR : integer := 0;

     MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";

     MSIX_CAP_TABLE_BIR : integer := 0;

     MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";

     MSIX_CAP_TABLE_SIZE : bit_vector := X"000";

     MSI_BASE_PTR : bit_vector := X"48";

     MSI_CAP_64_BIT_ADDR_CAPABLE : boolean := TRUE;

     MSI_CAP_ID : bit_vector := X"05";

     MSI_CAP_MULTIMSGCAP : integer := 0;

     MSI_CAP_MULTIMSG_EXTENSION : integer := 0;

     MSI_CAP_NEXTPTR : bit_vector := X"60";

     MSI_CAP_ON : boolean := TRUE;

     MSI_CAP_PER_VECTOR_MASKING_CAPABLE : boolean := TRUE;

     N_FTS_COMCLK_GEN1 : integer := 255;

     N_FTS_COMCLK_GEN2 : integer := 255;

     N_FTS_GEN1 : integer := 255;

     N_FTS_GEN2 : integer := 255;

     PCIE_BASE_PTR : bit_vector := X"60";

     PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";

     PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";

     PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"4";

     PCIE_CAP_INT_MSG_NUM : bit_vector := X"00";

     PCIE_CAP_NEXTPTR : bit_vector := X"9C";

     PCIE_CAP_ON : boolean := TRUE;

     PCIE_CAP_RSVD_15_14 : integer := 0;

     PCIE_CAP_SLOT_IMPLEMENTED : boolean := TRUE;

     PCIE_REVISION : integer := 2;

     PGL0_LANE : integer := 0;

     PGL1_LANE : integer := 1;

     PGL2_LANE : integer := 2;

     PGL3_LANE : integer := 3;

     PGL4_LANE : integer := 4;

     PGL5_LANE : integer := 5;

     PGL6_LANE : integer := 6;

     PGL7_LANE : integer := 7;

     PL_AUTO_CONFIG : integer := 0;

     PL_FAST_TRAIN : boolean := FALSE;

     PM_BASE_PTR : bit_vector := X"40";

     PM_CAP_AUXCURRENT : integer := 0;

     PM_CAP_D1SUPPORT : boolean := TRUE;

     PM_CAP_D2SUPPORT : boolean := TRUE;

     PM_CAP_DSI : boolean := FALSE;

     PM_CAP_ID : bit_vector := X"11";

     PM_CAP_NEXTPTR : bit_vector := X"48";

     PM_CAP_ON : boolean := TRUE;

     PM_CAP_PMESUPPORT : bit_vector := X"0F";

     PM_CAP_PME_CLOCK : boolean := FALSE;

     PM_CAP_RSVD_04 : integer := 0;

     PM_CAP_VERSION : integer := 3;

     PM_CSR_B2B3 : boolean := FALSE;

     PM_CSR_BPCCEN : boolean := FALSE;

     PM_CSR_NOSOFTRST : boolean := TRUE;

     PM_DATA0 : bit_vector := X"01";

     PM_DATA1 : bit_vector := X"01";

     PM_DATA2 : bit_vector := X"01";

     PM_DATA3 : bit_vector := X"01";

     PM_DATA4 : bit_vector := X"01";

     PM_DATA5 : bit_vector := X"01";

     PM_DATA6 : bit_vector := X"01";

     PM_DATA7 : bit_vector := X"01";

     PM_DATA_SCALE0 : bit_vector := X"1";

     PM_DATA_SCALE1 : bit_vector := X"1";

     PM_DATA_SCALE2 : bit_vector := X"1";

     PM_DATA_SCALE3 : bit_vector := X"1";

     PM_DATA_SCALE4 : bit_vector := X"1";

     PM_DATA_SCALE5 : bit_vector := X"1";

     PM_DATA_SCALE6 : bit_vector := X"1";

     PM_DATA_SCALE7 : bit_vector := X"1";

     RECRC_CHK : integer := 0;

     RECRC_CHK_TRIM : boolean := FALSE;

     REVISION_ID : bit_vector := X"00";

     ROOT_CAP_CRS_SW_VISIBILITY : boolean := FALSE;

     SELECT_DLL_IF : boolean := FALSE;

     SIM_VERSION : string := "1.0";

     SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;

     SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;

     SLOT_CAP_ELEC_INTERLOCK_PRESENT : boolean := FALSE;

     SLOT_CAP_HOTPLUG_CAPABLE : boolean := FALSE;

     SLOT_CAP_HOTPLUG_SURPRISE : boolean := FALSE;

     SLOT_CAP_MRL_SENSOR_PRESENT : boolean := FALSE;

     SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : boolean := FALSE;

     SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";

     SLOT_CAP_POWER_CONTROLLER_PRESENT : boolean := FALSE;

     SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;

     SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;

     SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";

     SPARE_BIT0 : integer := 0;

     SPARE_BIT1 : integer := 0;

     SPARE_BIT2 : integer := 0;

     SPARE_BIT3 : integer := 0;

     SPARE_BIT4 : integer := 0;

     SPARE_BIT5 : integer := 0;

     SPARE_BIT6 : integer := 0;

     SPARE_BIT7 : integer := 0;

     SPARE_BIT8 : integer := 0;

     SPARE_BYTE0 : bit_vector := X"00";

     SPARE_BYTE1 : bit_vector := X"00";

     SPARE_BYTE2 : bit_vector := X"00";

     SPARE_BYTE3 : bit_vector := X"00";

     SPARE_WORD0 : bit_vector := X"00000000";

     SPARE_WORD1 : bit_vector := X"00000000";

     SPARE_WORD2 : bit_vector := X"00000000";

     SPARE_WORD3 : bit_vector := X"00000000";

     SUBSYSTEM_ID : bit_vector := X"0007";

     SUBSYSTEM_VENDOR_ID : bit_vector := X"10EE";

     TL_RBYPASS : boolean := FALSE;

     TL_RX_RAM_RADDR_LATENCY : integer := 0;

     TL_RX_RAM_RDATA_LATENCY : integer := 2;

     TL_RX_RAM_WRITE_LATENCY : integer := 0;

     TL_TFC_DISABLE : boolean := FALSE;

     TL_TX_CHECKS_DISABLE : boolean := FALSE;

     TL_TX_RAM_RADDR_LATENCY : integer := 0;

     TL_TX_RAM_RDATA_LATENCY : integer := 2;

     TL_TX_RAM_WRITE_LATENCY : integer := 0;

     UPCONFIG_CAPABLE : boolean := TRUE;

     UPSTREAM_FACING : boolean := FALSE;

     UR_INV_REQ : boolean := TRUE;

     USER_CLK_FREQ : integer := 3;

     VC0_CPL_INFINITE : boolean := TRUE;

     VC0_RX_RAM_LIMIT : bit_vector := X"03FF";

     VC0_TOTAL_CREDITS_CD : integer := 127;

     VC0_TOTAL_CREDITS_CH : integer := 31;

     VC0_TOTAL_CREDITS_NPH : integer := 12;

     VC0_TOTAL_CREDITS_PD : integer := 288;

     VC0_TOTAL_CREDITS_PH : integer := 32;

     VC0_TX_LASTPACKET : integer := 31;

     VC_BASE_PTR : bit_vector := X"10C";

     VC_CAP_ID : bit_vector := X"0002";

     VC_CAP_NEXTPTR : bit_vector := X"128";

     VC_CAP_ON : boolean := TRUE;

     VC_CAP_REJECT_SNOOP_TRANSACTIONS : boolean := FALSE;

     VC_CAP_VERSION : bit_vector := X"1";

     VENDOR_ID : bit_vector := X"10EE";

     VSEC_BASE_PTR : bit_vector := X"160";

     VSEC_CAP_HDR_ID : bit_vector := X"1234";

     VSEC_CAP_HDR_LENGTH : bit_vector := X"018";

     VSEC_CAP_HDR_REVISION : bit_vector := X"1";

     VSEC_CAP_ID : bit_vector := X"000B";

     VSEC_CAP_IS_LINK_VISIBLE : boolean := TRUE;

     VSEC_CAP_NEXTPTR : bit_vector := X"000";

     VSEC_CAP_ON : boolean := TRUE;

     VSEC_CAP_VERSION : bit_vector := X"1"

   );

   port (

      ---------------------------------------------------------

      -- 1. PCI Express (pci_exp) Interface

      ---------------------------------------------------------

      -- Tx

      pci_exp_txp                                  : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);

      pci_exp_txn                                  : out std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);

      -- Rx

      pci_exp_rxp                                  : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);

      pci_exp_rxn                                  : in std_logic_vector(LINK_CAP_MAX_LINK_WIDTH_int - 1 downto 0);

      ---------------------------------------------------------

      -- 2. Transaction (TRN) Interface

      ---------------------------------------------------------

      -- Common

      trn_clk                                      : out std_logic;

      trn_reset_n                                  : out std_logic;

      trn_lnk_up_n                                 : out std_logic;

      -- Tx

      trn_tbuf_av                                  : out std_logic_vector(5 downto 0);

      trn_tcfg_req_n                               : out std_logic;

      trn_terr_drop_n                              : out std_logic;

      trn_tdst_rdy_n                               : out std_logic;

      trn_td                                       : in std_logic_vector(63 downto 0);

      trn_trem_n                                   : in std_logic;

      trn_tsof_n                                   : in std_logic;

      trn_teof_n                                   : in std_logic;

      trn_tsrc_rdy_n                               : in std_logic;

      trn_tsrc_dsc_n                               : in std_logic;

      trn_terrfwd_n                                : in std_logic;

      trn_tcfg_gnt_n                               : in std_logic;

      trn_tstr_n                                   : in std_logic;

      -- Rx

      trn_rd                                       : out std_logic_vector(63 downto 0);

      trn_rrem_n                                   : out std_logic;

      trn_rsof_n                                   : out std_logic;

      trn_reof_n                                   : out std_logic;

      trn_rsrc_rdy_n                               : out std_logic;

      trn_rsrc_dsc_n                               : out std_logic;

      trn_rerrfwd_n                                : out std_logic;

      trn_rbar_hit_n                               : out std_logic_vector(6 downto 0);

      trn_rdst_rdy_n                               : in std_logic;

      trn_rnp_ok_n                                 : in std_logic;

      trn_recrc_err_n                              : out std_logic;

      -- Flow Control

      trn_fc_cpld                                  : out std_logic_vector(11 downto 0);

      trn_fc_cplh                                  : out std_logic_vector(7 downto 0);

      trn_fc_npd                                   : out std_logic_vector(11 downto 0);

      trn_fc_nph                                   : out std_logic_vector(7 downto 0);

      trn_fc_pd                                    : out std_logic_vector(11 downto 0);

      trn_fc_ph                                    : out std_logic_vector(7 downto 0);

      trn_fc_sel                                   : in std_logic_vector(2 downto 0);

      ---------------------------------------------------------

      -- 3. Configuration (CFG) Interface

      ---------------------------------------------------------

      cfg_do                                       : out std_logic_vector(31 downto 0);

      cfg_rd_wr_done_n                             : out std_logic;

      cfg_di                                       : in std_logic_vector(31 downto 0);

      cfg_byte_en_n                                : in std_logic_vector(3 downto 0);

      cfg_dwaddr                                   : in std_logic_vector(9 downto 0);

      cfg_wr_en_n                                  : in std_logic;

      cfg_wr_rw1c_as_rw_n                          : in std_logic;

      cfg_rd_en_n                                  : in std_logic;

      cfg_err_cor_n                                : in std_logic;

      cfg_err_ur_n                                 : in std_logic;

      cfg_err_ecrc_n                               : in std_logic;

      cfg_err_cpl_timeout_n                        : in std_logic;

      cfg_err_cpl_abort_n                          : in std_logic;

      cfg_err_cpl_unexpect_n                       : in std_logic;

      cfg_err_posted_n                             : in std_logic;

      cfg_err_locked_n                             : in std_logic;

      cfg_err_tlp_cpl_header                       : in std_logic_vector(47 downto 0);

      cfg_err_cpl_rdy_n                            : out std_logic;

      cfg_interrupt_n                              : in std_logic;

      cfg_interrupt_rdy_n                          : out std_logic;

      cfg_interrupt_assert_n                       : in std_logic;

      cfg_interrupt_di                             : in std_logic_vector(7 downto 0);

      cfg_interrupt_do                             : out std_logic_vector(7 downto 0);

      cfg_interrupt_mmenable                       : out std_logic_vector(2 downto 0);

      cfg_interrupt_msienable                      : out std_logic;

      cfg_interrupt_msixenable                     : out std_logic;

      cfg_interrupt_msixfm                         : out std_logic;

      cfg_trn_pending_n                            : in std_logic;

      cfg_pm_send_pme_to_n                         : in std_logic;

      cfg_status                                   : out std_logic_vector(15 downto 0);

      cfg_command                                  : out std_logic_vector(15 downto 0);

      cfg_dstatus                                  : out std_logic_vector(15 downto 0);

      cfg_dcommand                                 : out std_logic_vector(15 downto 0);

      cfg_lstatus                                  : out std_logic_vector(15 downto 0);

      cfg_lcommand                                 : out std_logic_vector(15 downto 0);

      cfg_dcommand2                                : out std_logic_vector(15 downto 0);

      cfg_pcie_link_state_n                        : out std_logic_vector(2 downto 0);

      cfg_dsn                                      : in std_logic_vector(63 downto 0);

      cfg_pmcsr_pme_en                             : out std_logic;

      cfg_pmcsr_pme_status                         : out std_logic;

      cfg_pmcsr_powerstate                         : out std_logic_vector(1 downto 0);

      cfg_msg_received                             : out std_logic;

      cfg_msg_data                                 : out std_logic_vector(15 downto 0);

      cfg_msg_received_err_cor                     : out std_logic;

      cfg_msg_received_err_non_fatal               : out std_logic;

      cfg_msg_received_err_fatal                   : out std_logic;

      cfg_msg_received_pme_to_ack                  : out std_logic;

      cfg_msg_received_assert_inta                 : out std_logic;

      cfg_msg_received_assert_intb                 : out std_logic;

      cfg_msg_received_assert_intc                 : out std_logic;

      cfg_msg_received_assert_intd                 : out std_logic;

      cfg_msg_received_deassert_inta               : out std_logic;

      cfg_msg_received_deassert_intb               : out std_logic;

      cfg_msg_received_deassert_intc               : out std_logic;

      cfg_msg_received_deassert_intd               : out std_logic;

      cfg_ds_bus_number                            : in std_logic_vector(7 downto 0);

      cfg_ds_device_number                         : in std_logic_vector(4 downto 0);

      ---------------------------------------------------------

      -- 4. Physical Layer Control and Status (PL) Interface

      ---------------------------------------------------------

      pl_initial_link_width                        : out std_logic_vector(2 downto 0);

      pl_lane_reversal_mode                        : out std_logic_vector(1 downto 0);

      pl_link_gen2_capable                         : out std_logic;

      pl_link_partner_gen2_supported               : out std_logic;

      pl_link_upcfg_capable                        : out std_logic;

      pl_ltssm_state                               : out std_logic_vector(5 downto 0);

      pl_sel_link_rate                             : out std_logic;

      pl_sel_link_width                            : out std_logic_vector(1 downto 0);

      pl_directed_link_auton                       : in std_logic;

      pl_directed_link_change                      : in std_logic_vector(1 downto 0);

      pl_directed_link_speed                       : in std_logic;

      pl_directed_link_width                       : in std_logic_vector(1 downto 0);

      pl_upstream_prefer_deemph                    : in std_logic;

      pl_transmit_hot_rst                          : in std_logic;

      ---------------------------------------------------------

      -- 5. PCIe DRP (PCIe DRP) Interface

      ---------------------------------------------------------

      pcie_drp_clk                              : in std_logic;

      pcie_drp_den                              : in std_logic;

      pcie_drp_dwe                              : in std_logic;

      pcie_drp_daddr                            : in std_logic_vector(8 downto 0);

      pcie_drp_di                               : in std_logic_vector(15 downto 0);

      pcie_drp_do                               : out std_logic_vector(15 downto 0);

      pcie_drp_drdy                             : out std_logic;

      ---------------------------------------------------------

      -- 6. System  (SYS) Interface

      ---------------------------------------------------------

      sys_clk                                      : in std_logic;

      sys_reset_n                                  : in std_logic

   );

end pcie_2_0_rport_v6;

architecture v6_pcie of pcie_2_0_rport_v6 is

  component pcie_reset_delay_v6

    generic (

      PL_FAST_TRAIN : boolean;

      REF_CLK_FREQ  : integer);

    port (

      ref_clk             : in  std_logic;

      sys_reset_n         : in  std_logic;

      delayed_sys_reset_n : out std_logic);

  end component;

  component pcie_clocking_v6

    generic (

      IS_ENDPOINT    : boolean;

      CAP_LINK_WIDTH : integer;

      CAP_LINK_SPEED : integer;

      REF_CLK_FREQ   : integer;

      USER_CLK_FREQ  : integer);

    port (

      sys_clk       : in  std_logic;

      gt_pll_lock   : in  std_logic;

      sel_lnk_rate  : in  std_logic;

      sel_lnk_width : in  std_logic_vector(1 downto 0);

      sys_clk_bufg  : out std_logic;

      pipe_clk      : out std_logic;

      user_clk      : out std_logic;

      block_clk     : out std_logic;

      drp_clk       : out std_logic;

      clock_locked  : out std_logic);

  end component;

  component pcie_2_0_v6_rp

    generic (

      REF_CLK_FREQ                             : integer;

      PIPE_PIPELINE_STAGES                     : integer;

      LINK_CAP_MAX_LINK_WIDTH_int              : integer;

      AER_BASE_PTR                             : bit_vector;

      AER_CAP_ECRC_CHECK_CAPABLE               : boolean;

      AER_CAP_ECRC_GEN_CAPABLE                 : boolean;

      AER_CAP_ID                               : bit_vector;

      AER_CAP_INT_MSG_NUM_MSI                  : bit_vector;

      AER_CAP_INT_MSG_NUM_MSIX                 : bit_vector;

      AER_CAP_NEXTPTR                          : bit_vector;

      AER_CAP_ON                               : boolean;

      AER_CAP_PERMIT_ROOTERR_UPDATE            : boolean;

      AER_CAP_VERSION                          : bit_vector;

      ALLOW_X8_GEN2                            : boolean;

      BAR0                                     : bit_vector;

      BAR1                                     : bit_vector;

      BAR2                                     : bit_vector;

      BAR3                                     : bit_vector;

      BAR4                                     : bit_vector;

      BAR5                                     : bit_vector;

      CAPABILITIES_PTR                         : bit_vector;

      CARDBUS_CIS_POINTER                      : bit_vector;

      CLASS_CODE                               : bit_vector;

      CMD_INTX_IMPLEMENTED                     : boolean;

      CPL_TIMEOUT_DISABLE_SUPPORTED            : boolean;

      CPL_TIMEOUT_RANGES_SUPPORTED             : bit_vector;

      CRM_MODULE_RSTS                          : bit_vector;

      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE      : boolean;

      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE      : boolean;

      DEV_CAP_ENDPOINT_L0S_LATENCY             : integer;

      DEV_CAP_ENDPOINT_L1_LATENCY              : integer;

      DEV_CAP_EXT_TAG_SUPPORTED                : boolean;

      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE     : boolean;

      DEV_CAP_MAX_PAYLOAD_SUPPORTED            : integer;

      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT        : integer;

      DEV_CAP_ROLE_BASED_ERROR                 : boolean;

      DEV_CAP_RSVD_14_12                       : integer;

      DEV_CAP_RSVD_17_16                       : integer;

      DEV_CAP_RSVD_31_29                       : integer;

      DEV_CONTROL_AUX_POWER_SUPPORTED          : boolean;

      DEVICE_ID                                : bit_vector;

      DISABLE_ASPM_L1_TIMER                    : boolean;

      DISABLE_BAR_FILTERING                    : boolean;

      DISABLE_ID_CHECK                         : boolean;

      DISABLE_LANE_REVERSAL                    : boolean;

      DISABLE_RX_TC_FILTER                     : boolean;

      DISABLE_SCRAMBLING                       : boolean;

      DNSTREAM_LINK_NUM                        : bit_vector;

      DSN_BASE_PTR                             : bit_vector;

      DSN_CAP_ID                               : bit_vector;

      DSN_CAP_NEXTPTR                          : bit_vector;

      DSN_CAP_ON                               : boolean;

      DSN_CAP_VERSION                          : bit_vector;

      ENABLE_MSG_ROUTE                         : bit_vector;

      ENABLE_RX_TD_ECRC_TRIM                   : boolean;

      ENTER_RVRY_EI_L0                         : boolean;

      EXPANSION_ROM                            : bit_vector;

      EXT_CFG_CAP_PTR                          : bit_vector;

      EXT_CFG_XP_CAP_PTR                       : bit_vector;

      HEADER_TYPE                              : bit_vector;

      INFER_EI                                 : bit_vector;

      INTERRUPT_PIN                            : bit_vector;

      IS_SWITCH                                : boolean;

      LAST_CONFIG_DWORD                        : bit_vector;

      LINK_CAP_ASPM_SUPPORT                    : integer;

      LINK_CAP_CLOCK_POWER_MANAGEMENT          : boolean;

      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP   : boolean;

      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1    : integer;

      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2    : integer;

      LINK_CAP_L0S_EXIT_LATENCY_GEN1           : integer;

      LINK_CAP_L0S_EXIT_LATENCY_GEN2           : integer;

      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1     : integer;

      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2     : integer;

      LINK_CAP_L1_EXIT_LATENCY_GEN1            : integer;

      LINK_CAP_L1_EXIT_LATENCY_GEN2            : integer;

      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : boolean;

      LINK_CAP_MAX_LINK_SPEED                  : bit_vector;

      LINK_CAP_MAX_LINK_WIDTH                  : bit_vector;

      LINK_CAP_RSVD_23_22                      : integer;

      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE     : boolean;

      LINK_CONTROL_RCB                         : integer;

      LINK_CTRL2_DEEMPHASIS                    : boolean;

      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE   : boolean;

      LINK_CTRL2_TARGET_LINK_SPEED             : bit_vector;

      LINK_STATUS_SLOT_CLOCK_CONFIG            : boolean;

      LL_ACK_TIMEOUT                           : bit_vector;

      LL_ACK_TIMEOUT_EN                        : boolean;

      LL_ACK_TIMEOUT_FUNC                      : integer;

      LL_REPLAY_TIMEOUT                        : bit_vector;

      LL_REPLAY_TIMEOUT_EN                     : boolean;

      LL_REPLAY_TIMEOUT_FUNC                   : integer;

      LTSSM_MAX_LINK_WIDTH                     : bit_vector;

      MSI_BASE_PTR                             : bit_vector;

      MSI_CAP_ID                               : bit_vector;

      MSI_CAP_MULTIMSGCAP                      : integer;

      MSI_CAP_MULTIMSG_EXTENSION               : integer;

      MSI_CAP_NEXTPTR                          : bit_vector;