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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_2_0_v6.v
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// Version : 1.7
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//-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ps/1ps
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module pcie_2_0_v6 #(
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parameter TCQ = 1,
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parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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parameter AER_BASE_PTR = 12'h128,
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parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
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parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
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parameter AER_CAP_ID = 16'h0001,
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parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
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parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
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parameter AER_CAP_NEXTPTR = 12'h160,
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parameter AER_CAP_ON = "FALSE",
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parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
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parameter AER_CAP_VERSION = 4'h1,
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parameter ALLOW_X8_GEN2 = "TRUE",
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parameter BAR0 = 32'hffffff00,
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parameter BAR1 = 32'hffff0000,
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parameter BAR2 = 32'hffff000c,
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parameter BAR3 = 32'hffffffff,
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parameter BAR4 = 32'h00000000,
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parameter BAR5 = 32'h00000000,
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parameter CAPABILITIES_PTR = 8'h40,
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parameter CARDBUS_CIS_POINTER = 32'h00000000,
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parameter CLASS_CODE = 24'h000000,
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parameter CMD_INTX_IMPLEMENTED = "TRUE",
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parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
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parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
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parameter CRM_MODULE_RSTS = 7'h00,
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parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
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parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
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parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
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parameter DEV_CAP_ENDPOINT_L1_LATENCY = 0,
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parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
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parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
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parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
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parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
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parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
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parameter DEV_CAP_RSVD_14_12 = 0,
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parameter DEV_CAP_RSVD_17_16 = 0,
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parameter DEV_CAP_RSVD_31_29 = 0,
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parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
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parameter DEVICE_ID = 16'h0007,
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parameter DISABLE_ASPM_L1_TIMER = "FALSE",
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parameter DISABLE_BAR_FILTERING = "FALSE",
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parameter DISABLE_ID_CHECK = "FALSE",
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parameter DISABLE_LANE_REVERSAL = "FALSE",
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parameter DISABLE_RX_TC_FILTER = "FALSE",
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parameter DISABLE_SCRAMBLING = "FALSE",
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parameter DNSTREAM_LINK_NUM = 8'h00,
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parameter DSN_BASE_PTR = 12'h100,
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parameter DSN_CAP_ID = 16'h0003,
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parameter DSN_CAP_NEXTPTR = 12'h000,
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parameter DSN_CAP_ON = "TRUE",
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parameter DSN_CAP_VERSION = 4'h1,
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parameter ENABLE_MSG_ROUTE = 11'h000,
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parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
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parameter ENTER_RVRY_EI_L0 = "TRUE",
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parameter EXPANSION_ROM = 32'hfffff001,
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parameter EXT_CFG_CAP_PTR = 6'h3f,
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parameter EXT_CFG_XP_CAP_PTR = 10'h3ff,
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parameter HEADER_TYPE = 8'h00,
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parameter INFER_EI = 5'h00,
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parameter INTERRUPT_PIN = 8'h01,
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parameter IS_SWITCH = "FALSE",
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parameter LAST_CONFIG_DWORD = 10'h042,
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parameter LINK_CAP_ASPM_SUPPORT = 1,
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parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
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parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
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parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
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parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
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parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
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parameter LINK_CAP_RSVD_23_22 = 0,
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parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
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parameter LINK_CONTROL_RCB = 0,
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parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
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parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
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parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
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parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
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parameter LL_ACK_TIMEOUT = 15'h0204,
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parameter LL_ACK_TIMEOUT_EN = "FALSE",
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parameter LL_ACK_TIMEOUT_FUNC = 0,
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parameter LL_REPLAY_TIMEOUT = 15'h060d,
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parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
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parameter LL_REPLAY_TIMEOUT_FUNC = 0,
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parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
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parameter MSI_BASE_PTR = 8'h48,
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parameter MSI_CAP_ID = 8'h05,
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parameter MSI_CAP_MULTIMSGCAP = 0,
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parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
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parameter MSI_CAP_NEXTPTR = 8'h60,
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parameter MSI_CAP_ON = "FALSE",
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parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
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parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
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parameter MSIX_BASE_PTR = 8'h9c,
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parameter MSIX_CAP_ID = 8'h11,
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parameter MSIX_CAP_NEXTPTR = 8'h00,
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parameter MSIX_CAP_ON = "FALSE",
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parameter MSIX_CAP_PBA_BIR = 0,
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parameter MSIX_CAP_PBA_OFFSET = 29'h00000050,
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parameter MSIX_CAP_TABLE_BIR = 0,
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parameter MSIX_CAP_TABLE_OFFSET = 29'h00000040,
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parameter MSIX_CAP_TABLE_SIZE = 11'h000,
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parameter N_FTS_COMCLK_GEN1 = 255,
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parameter N_FTS_COMCLK_GEN2 = 255,
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parameter N_FTS_GEN1 = 255,
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parameter N_FTS_GEN2 = 255,
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parameter PCIE_BASE_PTR = 8'h60,
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parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
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parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
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parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
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parameter PCIE_CAP_INT_MSG_NUM = 5'h00,
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parameter PCIE_CAP_NEXTPTR = 8'h00,
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parameter PCIE_CAP_ON = "TRUE",
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parameter PCIE_CAP_RSVD_15_14 = 0,
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parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
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parameter PCIE_REVISION = 2,
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parameter PGL0_LANE = 0,
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parameter PGL1_LANE = 1,
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parameter PGL2_LANE = 2,
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parameter PGL3_LANE = 3,
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parameter PGL4_LANE = 4,
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parameter PGL5_LANE = 5,
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parameter PGL6_LANE = 6,
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parameter PGL7_LANE = 7,
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parameter PL_AUTO_CONFIG = 0,
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parameter PL_FAST_TRAIN = "FALSE",
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parameter PM_BASE_PTR = 8'h40,
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parameter PM_CAP_AUXCURRENT = 0,
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parameter PM_CAP_DSI = "FALSE",
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parameter PM_CAP_D1SUPPORT = "TRUE",
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parameter PM_CAP_D2SUPPORT = "TRUE",
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parameter PM_CAP_ID = 8'h01,
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parameter PM_CAP_NEXTPTR = 8'h48,
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parameter PM_CAP_ON = "TRUE",
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parameter PM_CAP_PME_CLOCK = "FALSE",
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parameter PM_CAP_PMESUPPORT = 5'h0f,
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parameter PM_CAP_RSVD_04 = 0,
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parameter PM_CAP_VERSION = 3,
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parameter PM_CSR_BPCCEN = "FALSE",
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parameter PM_CSR_B2B3 = "FALSE",
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parameter PM_CSR_NOSOFTRST = "TRUE",
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parameter PM_DATA_SCALE0 = 2'h1,
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parameter PM_DATA_SCALE1 = 2'h1,
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parameter PM_DATA_SCALE2 = 2'h1,
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parameter PM_DATA_SCALE3 = 2'h1,
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parameter PM_DATA_SCALE4 = 2'h1,
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parameter PM_DATA_SCALE5 = 2'h1,
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parameter PM_DATA_SCALE6 = 2'h1,
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parameter PM_DATA_SCALE7 = 2'h1,
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parameter PM_DATA0 = 8'h01,
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parameter PM_DATA1 = 8'h01,
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parameter PM_DATA2 = 8'h01,
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parameter PM_DATA3 = 8'h01,
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parameter PM_DATA4 = 8'h01,
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parameter PM_DATA5 = 8'h01,
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parameter PM_DATA6 = 8'h01,
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parameter PM_DATA7 = 8'h01,
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parameter RECRC_CHK = 0,
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parameter RECRC_CHK_TRIM = "FALSE",
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parameter REVISION_ID = 8'h00,
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parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
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parameter SELECT_DLL_IF = "FALSE",
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parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
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parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
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parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
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parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
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parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
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parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
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parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
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parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
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parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
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parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
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parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
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parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
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parameter SPARE_BIT0 = 0,
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parameter SPARE_BIT1 = 0,
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parameter SPARE_BIT2 = 0,
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parameter SPARE_BIT3 = 0,
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parameter SPARE_BIT4 = 0,
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parameter SPARE_BIT5 = 0,
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parameter SPARE_BIT6 = 0,
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parameter SPARE_BIT7 = 0,
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parameter SPARE_BIT8 = 0,
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parameter SPARE_BYTE0 = 8'h00,
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parameter SPARE_BYTE1 = 8'h00,
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parameter SPARE_BYTE2 = 8'h00,
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parameter SPARE_BYTE3 = 8'h00,
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parameter SPARE_WORD0 = 32'h00000000,
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parameter SPARE_WORD1 = 32'h00000000,
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parameter SPARE_WORD2 = 32'h00000000,
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parameter SPARE_WORD3 = 32'h00000000,
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parameter SUBSYSTEM_ID = 16'h0007,
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parameter SUBSYSTEM_VENDOR_ID = 16'h10ee,
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parameter TL_RBYPASS = "FALSE",
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parameter TL_RX_RAM_RADDR_LATENCY = 0,
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parameter TL_RX_RAM_RDATA_LATENCY = 2,
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parameter TL_RX_RAM_WRITE_LATENCY = 0,
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parameter TL_TFC_DISABLE = "FALSE",
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parameter TL_TX_CHECKS_DISABLE = "FALSE",
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parameter TL_TX_RAM_RADDR_LATENCY = 0,
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parameter TL_TX_RAM_RDATA_LATENCY = 2,
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parameter TL_TX_RAM_WRITE_LATENCY = 0,
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parameter UPCONFIG_CAPABLE = "TRUE",
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parameter UPSTREAM_FACING = "TRUE",
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parameter EXIT_LOOPBACK_ON_EI = "TRUE",
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parameter UR_INV_REQ = "TRUE",
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parameter USER_CLK_FREQ = 3,
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parameter VC_BASE_PTR = 12'h10c,
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parameter VC_CAP_ID = 16'h0002,
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parameter VC_CAP_NEXTPTR = 12'h000,
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parameter VC_CAP_ON = "FALSE",
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parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
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parameter VC_CAP_VERSION = 4'h1,
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parameter VC0_CPL_INFINITE = "TRUE",
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parameter VC0_RX_RAM_LIMIT = 13'h03ff,
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parameter VC0_TOTAL_CREDITS_CD = 127,
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parameter VC0_TOTAL_CREDITS_CH = 31,
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parameter VC0_TOTAL_CREDITS_NPH = 12,
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parameter VC0_TOTAL_CREDITS_PD = 288,
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parameter VC0_TOTAL_CREDITS_PH = 32,
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parameter VC0_TX_LASTPACKET = 31,
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|
|
parameter VENDOR_ID = 16'h10ee,
|
290 |
|
|
parameter VSEC_BASE_PTR = 12'h160,
|
291 |
|
|
parameter VSEC_CAP_HDR_ID = 16'h1234,
|
292 |
|
|
parameter VSEC_CAP_HDR_LENGTH = 12'h018,
|
293 |
|
|
parameter VSEC_CAP_HDR_REVISION = 4'h1,
|
294 |
|
|
parameter VSEC_CAP_ID = 16'h000b,
|
295 |
|
|
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
|
296 |
|
|
parameter VSEC_CAP_NEXTPTR = 12'h000,
|
297 |
|
|
parameter VSEC_CAP_ON = "FALSE",
|
298 |
|
|
parameter VSEC_CAP_VERSION = 4'h1
|
299 |
|
|
|
300 |
|
|
)
|
301 |
|
|
(
|
302 |
|
|
|
303 |
|
|
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXN,
|
304 |
|
|
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXP,
|
305 |
|
|
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXN,
|
306 |
|
|
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXP,
|
307 |
|
|
|
308 |
|
|
input SYSCLK,
|
309 |
|
|
input FUNDRSTN,
|
310 |
|
|
|
311 |
|
|
output TRNLNKUPN,
|
312 |
|
|
output TRNCLK,
|
313 |
|
|
|
314 |
|
|
output PHYRDYN,
|
315 |
|
|
output USERRSTN,
|
316 |
|
|
output RECEIVEDFUNCLVLRSTN,
|
317 |
|
|
output LNKCLKEN,
|
318 |
|
|
input SYSRSTN,
|
319 |
|
|
input PLRSTN,
|
320 |
|
|
input DLRSTN,
|
321 |
|
|
input TLRSTN,
|
322 |
|
|
input FUNCLVLRSTN,
|
323 |
|
|
input CMRSTN,
|
324 |
|
|
input CMSTICKYRSTN,
|
325 |
|
|
|
326 |
|
|
output [6:0] TRNRBARHITN,
|
327 |
|
|
output [63:0] TRNRD,
|
328 |
|
|
output TRNRECRCERRN,
|
329 |
|
|
output TRNREOFN,
|
330 |
|
|
output TRNRERRFWDN,
|
331 |
|
|
output TRNRREMN,
|
332 |
|
|
output TRNRSOFN,
|
333 |
|
|
output TRNRSRCDSCN,
|
334 |
|
|
output TRNRSRCRDYN,
|
335 |
|
|
input TRNRDSTRDYN,
|
336 |
|
|
input TRNRNPOKN,
|
337 |
|
|
|
338 |
|
|
output [5:0] TRNTBUFAV,
|
339 |
|
|
output TRNTCFGREQN,
|
340 |
|
|
|
341 |
|
|
output TRNTDLLPDSTRDYN,
|
342 |
|
|
output TRNTDSTRDYN,
|
343 |
|
|
output TRNTERRDROPN,
|
344 |
|
|
|
345 |
|
|
input TRNTCFGGNTN,
|
346 |
|
|
|
347 |
|
|
input [63:0] TRNTD,
|
348 |
|
|
input [31:0] TRNTDLLPDATA,
|
349 |
|
|
input TRNTDLLPSRCRDYN,
|
350 |
|
|
input TRNTECRCGENN,
|
351 |
|
|
input TRNTEOFN,
|
352 |
|
|
input TRNTERRFWDN,
|
353 |
|
|
input TRNTREMN,
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
input TRNTSOFN,
|
357 |
|
|
input TRNTSRCDSCN,
|
358 |
|
|
input TRNTSRCRDYN,
|
359 |
|
|
input TRNTSTRN,
|
360 |
|
|
|
361 |
|
|
output [11:0] TRNFCCPLD,
|
362 |
|
|
output [7:0] TRNFCCPLH,
|
363 |
|
|
output [11:0] TRNFCNPD,
|
364 |
|
|
output [7:0] TRNFCNPH,
|
365 |
|
|
output [11:0] TRNFCPD,
|
366 |
|
|
output [7:0] TRNFCPH,
|
367 |
|
|
input [2:0] TRNFCSEL,
|
368 |
|
|
|
369 |
|
|
output CFGAERECRCCHECKEN,
|
370 |
|
|
output CFGAERECRCGENEN,
|
371 |
|
|
output CFGCOMMANDBUSMASTERENABLE,
|
372 |
|
|
output CFGCOMMANDINTERRUPTDISABLE,
|
373 |
|
|
output CFGCOMMANDIOENABLE,
|
374 |
|
|
output CFGCOMMANDMEMENABLE,
|
375 |
|
|
output CFGCOMMANDSERREN,
|
376 |
|
|
output CFGDEVCONTROLAUXPOWEREN,
|
377 |
|
|
output CFGDEVCONTROLCORRERRREPORTINGEN,
|
378 |
|
|
output CFGDEVCONTROLENABLERO,
|
379 |
|
|
output CFGDEVCONTROLEXTTAGEN,
|
380 |
|
|
output CFGDEVCONTROLFATALERRREPORTINGEN,
|
381 |
|
|
output [2:0] CFGDEVCONTROLMAXPAYLOAD,
|
382 |
|
|
output [2:0] CFGDEVCONTROLMAXREADREQ,
|
383 |
|
|
output CFGDEVCONTROLNONFATALREPORTINGEN,
|
384 |
|
|
output CFGDEVCONTROLNOSNOOPEN,
|
385 |
|
|
output CFGDEVCONTROLPHANTOMEN,
|
386 |
|
|
output CFGDEVCONTROLURERRREPORTINGEN,
|
387 |
|
|
output CFGDEVCONTROL2CPLTIMEOUTDIS,
|
388 |
|
|
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,
|
389 |
|
|
output CFGDEVSTATUSCORRERRDETECTED,
|
390 |
|
|
output CFGDEVSTATUSFATALERRDETECTED,
|
391 |
|
|
output CFGDEVSTATUSNONFATALERRDETECTED,
|
392 |
|
|
output CFGDEVSTATUSURDETECTED,
|
393 |
|
|
output [31:0] CFGDO,
|
394 |
|
|
output CFGERRAERHEADERLOGSETN,
|
395 |
|
|
output CFGERRCPLRDYN,
|
396 |
|
|
output [7:0] CFGINTERRUPTDO,
|
397 |
|
|
output [2:0] CFGINTERRUPTMMENABLE,
|
398 |
|
|
output CFGINTERRUPTMSIENABLE,
|
399 |
|
|
output CFGINTERRUPTMSIXENABLE,
|
400 |
|
|
output CFGINTERRUPTMSIXFM,
|
401 |
|
|
output CFGINTERRUPTRDYN,
|
402 |
|
|
output CFGLINKCONTROLRCB,
|
403 |
|
|
output [1:0] CFGLINKCONTROLASPMCONTROL,
|
404 |
|
|
output CFGLINKCONTROLAUTOBANDWIDTHINTEN,
|
405 |
|
|
output CFGLINKCONTROLBANDWIDTHINTEN,
|
406 |
|
|
output CFGLINKCONTROLCLOCKPMEN,
|
407 |
|
|
output CFGLINKCONTROLCOMMONCLOCK,
|
408 |
|
|
output CFGLINKCONTROLEXTENDEDSYNC,
|
409 |
|
|
output CFGLINKCONTROLHWAUTOWIDTHDIS,
|
410 |
|
|
output CFGLINKCONTROLLINKDISABLE,
|
411 |
|
|
output CFGLINKCONTROLRETRAINLINK,
|
412 |
|
|
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
|
413 |
|
|
output CFGLINKSTATUSBANDWITHSTATUS,
|
414 |
|
|
output [1:0] CFGLINKSTATUSCURRENTSPEED,
|
415 |
|
|
output CFGLINKSTATUSDLLACTIVE,
|
416 |
|
|
output CFGLINKSTATUSLINKTRAINING,
|
417 |
|
|
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,
|
418 |
|
|
output [15:0] CFGMSGDATA,
|
419 |
|
|
output CFGMSGRECEIVED,
|
420 |
|
|
output CFGMSGRECEIVEDASSERTINTA,
|
421 |
|
|
output CFGMSGRECEIVEDASSERTINTB,
|
422 |
|
|
output CFGMSGRECEIVEDASSERTINTC,
|
423 |
|
|
output CFGMSGRECEIVEDASSERTINTD,
|
424 |
|
|
output CFGMSGRECEIVEDDEASSERTINTA,
|
425 |
|
|
output CFGMSGRECEIVEDDEASSERTINTB,
|
426 |
|
|
output CFGMSGRECEIVEDDEASSERTINTC,
|
427 |
|
|
output CFGMSGRECEIVEDDEASSERTINTD,
|
428 |
|
|
output CFGMSGRECEIVEDERRCOR,
|
429 |
|
|
output CFGMSGRECEIVEDERRFATAL,
|
430 |
|
|
output CFGMSGRECEIVEDERRNONFATAL,
|
431 |
|
|
output CFGMSGRECEIVEDPMASNAK,
|
432 |
|
|
output CFGMSGRECEIVEDPMETO,
|
433 |
|
|
output CFGMSGRECEIVEDPMETOACK,
|
434 |
|
|
output CFGMSGRECEIVEDPMPME,
|
435 |
|
|
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
|
436 |
|
|
output CFGMSGRECEIVEDUNLOCK,
|
437 |
|
|
output [2:0] CFGPCIELINKSTATE,
|
438 |
|
|
output CFGPMCSRPMEEN,
|
439 |
|
|
output CFGPMCSRPMESTATUS,
|
440 |
|
|
output [1:0] CFGPMCSRPOWERSTATE,
|
441 |
|
|
output CFGPMRCVASREQL1N,
|
442 |
|
|
output CFGPMRCVENTERL1N,
|
443 |
|
|
output CFGPMRCVENTERL23N,
|
444 |
|
|
output CFGPMRCVREQACKN,
|
445 |
|
|
output CFGRDWRDONEN,
|
446 |
|
|
output CFGSLOTCONTROLELECTROMECHILCTLPULSE,
|
447 |
|
|
output CFGTRANSACTION,
|
448 |
|
|
output [6:0] CFGTRANSACTIONADDR,
|
449 |
|
|
output CFGTRANSACTIONTYPE,
|
450 |
|
|
output [6:0] CFGVCTCVCMAP,
|
451 |
|
|
input [3:0] CFGBYTEENN,
|
452 |
|
|
input [31:0] CFGDI,
|
453 |
|
|
input [7:0] CFGDSBUSNUMBER,
|
454 |
|
|
input [4:0] CFGDSDEVICENUMBER,
|
455 |
|
|
input [2:0] CFGDSFUNCTIONNUMBER,
|
456 |
|
|
input [63:0] CFGDSN,
|
457 |
|
|
input [9:0] CFGDWADDR,
|
458 |
|
|
input CFGERRACSN,
|
459 |
|
|
input [127:0] CFGERRAERHEADERLOG,
|
460 |
|
|
input CFGERRCORN,
|
461 |
|
|
input CFGERRCPLABORTN,
|
462 |
|
|
input CFGERRCPLTIMEOUTN,
|
463 |
|
|
input CFGERRCPLUNEXPECTN,
|
464 |
|
|
input CFGERRECRCN,
|
465 |
|
|
input CFGERRLOCKEDN,
|
466 |
|
|
input CFGERRPOSTEDN,
|
467 |
|
|
input [47:0] CFGERRTLPCPLHEADER,
|
468 |
|
|
input CFGERRURN,
|
469 |
|
|
input CFGINTERRUPTASSERTN,
|
470 |
|
|
input [7:0] CFGINTERRUPTDI,
|
471 |
|
|
input CFGINTERRUPTN,
|
472 |
|
|
input CFGPMDIRECTASPML1N,
|
473 |
|
|
input CFGPMSENDPMACKN,
|
474 |
|
|
input CFGPMSENDPMETON,
|
475 |
|
|
input CFGPMSENDPMNAKN,
|
476 |
|
|
input CFGPMTURNOFFOKN,
|
477 |
|
|
input CFGPMWAKEN,
|
478 |
|
|
input [7:0] CFGPORTNUMBER,
|
479 |
|
|
input CFGRDENN,
|
480 |
|
|
input CFGTRNPENDINGN,
|
481 |
|
|
input CFGWRENN,
|
482 |
|
|
input CFGWRREADONLYN,
|
483 |
|
|
input CFGWRRW1CASRWN,
|
484 |
|
|
|
485 |
|
|
output [2:0] PLINITIALLINKWIDTH,
|
486 |
|
|
output [1:0] PLLANEREVERSALMODE,
|
487 |
|
|
output PLLINKGEN2CAP,
|
488 |
|
|
output PLLINKPARTNERGEN2SUPPORTED,
|
489 |
|
|
output PLLINKUPCFGCAP,
|
490 |
|
|
output [5:0] PLLTSSMSTATE,
|
491 |
|
|
output PLPHYLNKUPN,
|
492 |
|
|
output PLRECEIVEDHOTRST,
|
493 |
|
|
output [1:0] PLRXPMSTATE,
|
494 |
|
|
output PLSELLNKRATE,
|
495 |
|
|
output [1:0] PLSELLNKWIDTH,
|
496 |
|
|
output [2:0] PLTXPMSTATE,
|
497 |
|
|
input PLDIRECTEDLINKAUTON,
|
498 |
|
|
input [1:0] PLDIRECTEDLINKCHANGE,
|
499 |
|
|
input PLDIRECTEDLINKSPEED,
|
500 |
|
|
input [1:0] PLDIRECTEDLINKWIDTH,
|
501 |
|
|
input PLDOWNSTREAMDEEMPHSOURCE,
|
502 |
|
|
input PLUPSTREAMPREFERDEEMPH,
|
503 |
|
|
input PLTRANSMITHOTRST,
|
504 |
|
|
|
505 |
|
|
output DBGSCLRA,
|
506 |
|
|
output DBGSCLRB,
|
507 |
|
|
output DBGSCLRC,
|
508 |
|
|
output DBGSCLRD,
|
509 |
|
|
output DBGSCLRE,
|
510 |
|
|
output DBGSCLRF,
|
511 |
|
|
output DBGSCLRG,
|
512 |
|
|
output DBGSCLRH,
|
513 |
|
|
output DBGSCLRI,
|
514 |
|
|
output DBGSCLRJ,
|
515 |
|
|
output DBGSCLRK,
|
516 |
|
|
output [63:0] DBGVECA,
|
517 |
|
|
output [63:0] DBGVECB,
|
518 |
|
|
output [11:0] DBGVECC,
|
519 |
|
|
output [11:0] PLDBGVEC,
|
520 |
|
|
input [1:0] DBGMODE,
|
521 |
|
|
input DBGSUBMODE,
|
522 |
|
|
input [2:0] PLDBGMODE,
|
523 |
|
|
output [15:0] PCIEDRPDO,
|
524 |
|
|
output PCIEDRPDRDY,
|
525 |
|
|
input PCIEDRPCLK,
|
526 |
|
|
input [8:0] PCIEDRPDADDR,
|
527 |
|
|
input PCIEDRPDEN,
|
528 |
|
|
input [15:0] PCIEDRPDI,
|
529 |
|
|
input PCIEDRPDWE,
|
530 |
|
|
|
531 |
|
|
output GTPLLLOCK,
|
532 |
|
|
input PIPECLK,
|
533 |
|
|
input USERCLK,
|
534 |
|
|
input DRPCLK,
|
535 |
|
|
input CLOCKLOCKED,
|
536 |
|
|
output TxOutClk
|
537 |
|
|
|
538 |
|
|
|
539 |
|
|
);
|
540 |
|
|
|
541 |
|
|
// wire declarations
|
542 |
|
|
|
543 |
|
|
wire LL2BADDLLPERRN;
|
544 |
|
|
wire LL2BADTLPERRN;
|
545 |
|
|
wire LL2PROTOCOLERRN;
|
546 |
|
|
wire LL2REPLAYROERRN;
|
547 |
|
|
wire LL2REPLAYTOERRN;
|
548 |
|
|
wire LL2SUSPENDOKN;
|
549 |
|
|
wire LL2TFCINIT1SEQN;
|
550 |
|
|
wire LL2TFCINIT2SEQN;
|
551 |
|
|
wire [12:0] MIMRXRADDR;
|
552 |
|
|
wire MIMRXRCE;
|
553 |
|
|
wire MIMRXREN;
|
554 |
|
|
wire [12:0] MIMRXWADDR;
|
555 |
|
|
wire [67:0] MIMRXWDATA;
|
556 |
|
|
wire MIMRXWEN;
|
557 |
|
|
wire [12:0] MIMTXRADDR;
|
558 |
|
|
wire MIMTXRCE;
|
559 |
|
|
wire MIMTXREN;
|
560 |
|
|
wire [12:0] MIMTXWADDR;
|
561 |
|
|
wire [68:0] MIMTXWDATA;
|
562 |
|
|
wire MIMTXWEN;
|
563 |
|
|
wire PIPERX0POLARITY;
|
564 |
|
|
wire PIPERX1POLARITY;
|
565 |
|
|
wire PIPERX2POLARITY;
|
566 |
|
|
wire PIPERX3POLARITY;
|
567 |
|
|
wire PIPERX4POLARITY;
|
568 |
|
|
wire PIPERX5POLARITY;
|
569 |
|
|
wire PIPERX6POLARITY;
|
570 |
|
|
wire PIPERX7POLARITY;
|
571 |
|
|
wire PIPETXDEEMPH;
|
572 |
|
|
wire [2:0] PIPETXMARGIN;
|
573 |
|
|
wire PIPETXRATE;
|
574 |
|
|
wire PIPETXRCVRDET;
|
575 |
|
|
wire PIPETXRESET;
|
576 |
|
|
wire [1:0] PIPETX0CHARISK;
|
577 |
|
|
wire PIPETX0COMPLIANCE;
|
578 |
|
|
wire [15:0] PIPETX0DATA;
|
579 |
|
|
wire PIPETX0ELECIDLE;
|
580 |
|
|
wire [1:0] PIPETX0POWERDOWN;
|
581 |
|
|
wire [1:0] PIPETX1CHARISK;
|
582 |
|
|
wire PIPETX1COMPLIANCE;
|
583 |
|
|
wire [15:0] PIPETX1DATA;
|
584 |
|
|
wire PIPETX1ELECIDLE;
|
585 |
|
|
wire [1:0] PIPETX1POWERDOWN;
|
586 |
|
|
wire [1:0] PIPETX2CHARISK;
|
587 |
|
|
wire PIPETX2COMPLIANCE;
|
588 |
|
|
wire [15:0] PIPETX2DATA;
|
589 |
|
|
wire PIPETX2ELECIDLE;
|
590 |
|
|
wire [1:0] PIPETX2POWERDOWN;
|
591 |
|
|
wire [1:0] PIPETX3CHARISK;
|
592 |
|
|
wire PIPETX3COMPLIANCE;
|
593 |
|
|
wire [15:0] PIPETX3DATA;
|
594 |
|
|
wire PIPETX3ELECIDLE;
|
595 |
|
|
wire [1:0] PIPETX3POWERDOWN;
|
596 |
|
|
wire [1:0] PIPETX4CHARISK;
|
597 |
|
|
wire PIPETX4COMPLIANCE;
|
598 |
|
|
wire [15:0] PIPETX4DATA;
|
599 |
|
|
wire PIPETX4ELECIDLE;
|
600 |
|
|
wire [1:0] PIPETX4POWERDOWN;
|
601 |
|
|
wire [1:0] PIPETX5CHARISK;
|
602 |
|
|
wire PIPETX5COMPLIANCE;
|
603 |
|
|
wire [15:0] PIPETX5DATA;
|
604 |
|
|
wire PIPETX5ELECIDLE;
|
605 |
|
|
wire [1:0] PIPETX5POWERDOWN;
|
606 |
|
|
wire [1:0] PIPETX6CHARISK;
|
607 |
|
|
wire PIPETX6COMPLIANCE;
|
608 |
|
|
wire [15:0] PIPETX6DATA;
|
609 |
|
|
wire PIPETX6ELECIDLE;
|
610 |
|
|
wire [1:0] PIPETX6POWERDOWN;
|
611 |
|
|
wire [1:0] PIPETX7CHARISK;
|
612 |
|
|
wire PIPETX7COMPLIANCE;
|
613 |
|
|
wire [15:0] PIPETX7DATA;
|
614 |
|
|
wire PIPETX7ELECIDLE;
|
615 |
|
|
wire [1:0] PIPETX7POWERDOWN;
|
616 |
|
|
wire PL2LINKUPN;
|
617 |
|
|
wire PL2RECEIVERERRN;
|
618 |
|
|
wire PL2RECOVERYN;
|
619 |
|
|
wire PL2RXELECIDLE;
|
620 |
|
|
wire PL2SUSPENDOK;
|
621 |
|
|
wire TL2ASPMSUSPENDCREDITCHECKOKN;
|
622 |
|
|
wire TL2ASPMSUSPENDREQN;
|
623 |
|
|
wire TL2PPMSUSPENDOKN;
|
624 |
|
|
wire LL2SENDASREQL1N = 1'b1;
|
625 |
|
|
wire LL2SENDENTERL1N = 1'b1;
|
626 |
|
|
wire LL2SENDENTERL23N = 1'b1;
|
627 |
|
|
wire LL2SUSPENDNOWN = 1'b1;
|
628 |
|
|
wire LL2TLPRCVN = 1'b1;
|
629 |
|
|
wire [67:0] MIMRXRDATA;
|
630 |
|
|
wire [68:0] MIMTXRDATA;
|
631 |
|
|
wire [4:0] PL2DIRECTEDLSTATE = 5'b0;
|
632 |
|
|
wire TL2ASPMSUSPENDCREDITCHECKN;
|
633 |
|
|
wire TL2PPMSUSPENDREQN;
|
634 |
|
|
wire PIPERX0CHANISALIGNED;
|
635 |
|
|
wire [1:0] PIPERX0CHARISK;
|
636 |
|
|
wire [15:0] PIPERX0DATA;
|
637 |
|
|
wire PIPERX0ELECIDLE;
|
638 |
|
|
wire PIPERX0PHYSTATUS;
|
639 |
|
|
wire [2:0] PIPERX0STATUS;
|
640 |
|
|
wire PIPERX0VALID;
|
641 |
|
|
wire PIPERX1CHANISALIGNED;
|
642 |
|
|
wire [1:0] PIPERX1CHARISK;
|
643 |
|
|
wire [15:0] PIPERX1DATA;
|
644 |
|
|
wire PIPERX1ELECIDLE;
|
645 |
|
|
wire PIPERX1PHYSTATUS;
|
646 |
|
|
wire [2:0] PIPERX1STATUS;
|
647 |
|
|
wire PIPERX1VALID;
|
648 |
|
|
wire PIPERX2CHANISALIGNED;
|
649 |
|
|
wire [1:0] PIPERX2CHARISK;
|
650 |
|
|
wire [15:0] PIPERX2DATA;
|
651 |
|
|
wire PIPERX2ELECIDLE;
|
652 |
|
|
wire PIPERX2PHYSTATUS;
|
653 |
|
|
wire [2:0] PIPERX2STATUS;
|
654 |
|
|
wire PIPERX2VALID;
|
655 |
|
|
wire PIPERX3CHANISALIGNED;
|
656 |
|
|
wire [1:0] PIPERX3CHARISK;
|
657 |
|
|
wire [15:0] PIPERX3DATA;
|
658 |
|
|
wire PIPERX3ELECIDLE;
|
659 |
|
|
wire PIPERX3PHYSTATUS;
|
660 |
|
|
wire [2:0] PIPERX3STATUS;
|
661 |
|
|
wire PIPERX3VALID;
|
662 |
|
|
wire PIPERX4CHANISALIGNED;
|
663 |
|
|
wire [1:0] PIPERX4CHARISK;
|
664 |
|
|
wire [15:0] PIPERX4DATA;
|
665 |
|
|
wire PIPERX4ELECIDLE;
|
666 |
|
|
wire PIPERX4PHYSTATUS;
|
667 |
|
|
wire [2:0] PIPERX4STATUS;
|
668 |
|
|
wire PIPERX4VALID;
|
669 |
|
|
wire PIPERX5CHANISALIGNED;
|
670 |
|
|
wire [1:0] PIPERX5CHARISK;
|
671 |
|
|
wire [15:0] PIPERX5DATA;
|
672 |
|
|
wire PIPERX5ELECIDLE;
|
673 |
|
|
wire PIPERX5PHYSTATUS;
|
674 |
|
|
wire [2:0] PIPERX5STATUS;
|
675 |
|
|
wire PIPERX5VALID;
|
676 |
|
|
wire PIPERX6CHANISALIGNED;
|
677 |
|
|
wire [1:0] PIPERX6CHARISK;
|
678 |
|
|
wire [15:0] PIPERX6DATA;
|
679 |
|
|
wire PIPERX6ELECIDLE;
|
680 |
|
|
wire PIPERX6PHYSTATUS;
|
681 |
|
|
wire [2:0] PIPERX6STATUS;
|
682 |
|
|
wire PIPERX6VALID;
|
683 |
|
|
wire PIPERX7CHANISALIGNED;
|
684 |
|
|
wire [1:0] PIPERX7CHARISK;
|
685 |
|
|
wire [15:0] PIPERX7DATA;
|
686 |
|
|
wire PIPERX7ELECIDLE;
|
687 |
|
|
wire PIPERX7PHYSTATUS;
|
688 |
|
|
wire [2:0] PIPERX7STATUS;
|
689 |
|
|
wire PIPERX7VALID;
|
690 |
|
|
|
691 |
|
|
wire PIPERX0POLARITYGT;
|
692 |
|
|
wire PIPERX1POLARITYGT;
|
693 |
|
|
wire PIPERX2POLARITYGT;
|
694 |
|
|
wire PIPERX3POLARITYGT;
|
695 |
|
|
wire PIPERX4POLARITYGT;
|
696 |
|
|
wire PIPERX5POLARITYGT;
|
697 |
|
|
wire PIPERX6POLARITYGT;
|
698 |
|
|
wire PIPERX7POLARITYGT;
|
699 |
|
|
wire PIPETXDEEMPHGT;
|
700 |
|
|
wire [2:0] PIPETXMARGINGT;
|
701 |
|
|
wire PIPETXRATEGT;
|
702 |
|
|
wire PIPETXRCVRDETGT;
|
703 |
|
|
wire [1:0] PIPETX0CHARISKGT;
|
704 |
|
|
wire PIPETX0COMPLIANCEGT;
|
705 |
|
|
wire [15:0] PIPETX0DATAGT;
|
706 |
|
|
wire PIPETX0ELECIDLEGT;
|
707 |
|
|
wire [1:0] PIPETX0POWERDOWNGT;
|
708 |
|
|
wire [1:0] PIPETX1CHARISKGT;
|
709 |
|
|
wire PIPETX1COMPLIANCEGT;
|
710 |
|
|
wire [15:0] PIPETX1DATAGT;
|
711 |
|
|
wire PIPETX1ELECIDLEGT;
|
712 |
|
|
wire [1:0] PIPETX1POWERDOWNGT;
|
713 |
|
|
wire [1:0] PIPETX2CHARISKGT;
|
714 |
|
|
wire PIPETX2COMPLIANCEGT;
|
715 |
|
|
wire [15:0] PIPETX2DATAGT;
|
716 |
|
|
wire PIPETX2ELECIDLEGT;
|
717 |
|
|
wire [1:0] PIPETX2POWERDOWNGT;
|
718 |
|
|
wire [1:0] PIPETX3CHARISKGT;
|
719 |
|
|
wire PIPETX3COMPLIANCEGT;
|
720 |
|
|
wire [15:0] PIPETX3DATAGT;
|
721 |
|
|
wire PIPETX3ELECIDLEGT;
|
722 |
|
|
wire [1:0] PIPETX3POWERDOWNGT;
|
723 |
|
|
wire [1:0] PIPETX4CHARISKGT;
|
724 |
|
|
wire PIPETX4COMPLIANCEGT;
|
725 |
|
|
wire [15:0] PIPETX4DATAGT;
|
726 |
|
|
wire PIPETX4ELECIDLEGT;
|
727 |
|
|
wire [1:0] PIPETX4POWERDOWNGT;
|
728 |
|
|
wire [1:0] PIPETX5CHARISKGT;
|
729 |
|
|
wire PIPETX5COMPLIANCEGT;
|
730 |
|
|
wire [15:0] PIPETX5DATAGT;
|
731 |
|
|
wire PIPETX5ELECIDLEGT;
|
732 |
|
|
wire [1:0] PIPETX5POWERDOWNGT;
|
733 |
|
|
wire [1:0] PIPETX6CHARISKGT;
|
734 |
|
|
wire PIPETX6COMPLIANCEGT;
|
735 |
|
|
wire [15:0] PIPETX6DATAGT;
|
736 |
|
|
wire PIPETX6ELECIDLEGT;
|
737 |
|
|
wire [1:0] PIPETX6POWERDOWNGT;
|
738 |
|
|
wire [1:0] PIPETX7CHARISKGT;
|
739 |
|
|
wire PIPETX7COMPLIANCEGT;
|
740 |
|
|
wire [15:0] PIPETX7DATAGT;
|
741 |
|
|
wire PIPETX7ELECIDLEGT;
|
742 |
|
|
wire [1:0] PIPETX7POWERDOWNGT;
|
743 |
|
|
|
744 |
|
|
wire PIPERX0CHANISALIGNEDGT;
|
745 |
|
|
wire [1:0] PIPERX0CHARISKGT;
|
746 |
|
|
wire [15:0] PIPERX0DATAGT;
|
747 |
|
|
wire PIPERX0ELECIDLEGT;
|
748 |
|
|
wire PIPERX0PHYSTATUSGT;
|
749 |
|
|
wire [2:0] PIPERX0STATUSGT;
|
750 |
|
|
wire PIPERX0VALIDGT;
|
751 |
|
|
wire PIPERX1CHANISALIGNEDGT;
|
752 |
|
|
wire [1:0] PIPERX1CHARISKGT;
|
753 |
|
|
wire [15:0] PIPERX1DATAGT;
|
754 |
|
|
wire PIPERX1ELECIDLEGT;
|
755 |
|
|
wire PIPERX1PHYSTATUSGT;
|
756 |
|
|
wire [2:0] PIPERX1STATUSGT;
|
757 |
|
|
wire PIPERX1VALIDGT;
|
758 |
|
|
wire PIPERX2CHANISALIGNEDGT;
|
759 |
|
|
wire [1:0] PIPERX2CHARISKGT;
|
760 |
|
|
wire [15:0] PIPERX2DATAGT;
|
761 |
|
|
wire PIPERX2ELECIDLEGT;
|
762 |
|
|
wire PIPERX2PHYSTATUSGT;
|
763 |
|
|
wire [2:0] PIPERX2STATUSGT;
|
764 |
|
|
wire PIPERX2VALIDGT;
|
765 |
|
|
wire PIPERX3CHANISALIGNEDGT;
|
766 |
|
|
wire [1:0] PIPERX3CHARISKGT;
|
767 |
|
|
wire [15:0] PIPERX3DATAGT;
|
768 |
|
|
wire PIPERX3ELECIDLEGT;
|
769 |
|
|
wire PIPERX3PHYSTATUSGT;
|
770 |
|
|
wire [2:0] PIPERX3STATUSGT;
|
771 |
|
|
wire PIPERX3VALIDGT;
|
772 |
|
|
wire PIPERX4CHANISALIGNEDGT;
|
773 |
|
|
wire [1:0] PIPERX4CHARISKGT;
|
774 |
|
|
wire [15:0] PIPERX4DATAGT;
|
775 |
|
|
wire PIPERX4ELECIDLEGT;
|
776 |
|
|
wire PIPERX4PHYSTATUSGT;
|
777 |
|
|
wire [2:0] PIPERX4STATUSGT;
|
778 |
|
|
wire PIPERX4VALIDGT;
|
779 |
|
|
wire PIPERX5CHANISALIGNEDGT;
|
780 |
|
|
wire [1:0] PIPERX5CHARISKGT;
|
781 |
|
|
wire [15:0] PIPERX5DATAGT;
|
782 |
|
|
wire PIPERX5ELECIDLEGT;
|
783 |
|
|
wire PIPERX5PHYSTATUSGT;
|
784 |
|
|
wire [2:0] PIPERX5STATUSGT;
|
785 |
|
|
wire PIPERX5VALIDGT;
|
786 |
|
|
wire PIPERX6CHANISALIGNEDGT;
|
787 |
|
|
wire [1:0] PIPERX6CHARISKGT;
|
788 |
|
|
wire [15:0] PIPERX6DATAGT;
|
789 |
|
|
wire PIPERX6ELECIDLEGT;
|
790 |
|
|
wire PIPERX6PHYSTATUSGT;
|
791 |
|
|
wire [2:0] PIPERX6STATUSGT;
|
792 |
|
|
wire PIPERX6VALIDGT;
|
793 |
|
|
wire PIPERX7CHANISALIGNEDGT;
|
794 |
|
|
wire [1:0] PIPERX7CHARISKGT;
|
795 |
|
|
wire [15:0] PIPERX7DATAGT;
|
796 |
|
|
wire PIPERX7ELECIDLEGT;
|
797 |
|
|
wire PIPERX7PHYSTATUSGT;
|
798 |
|
|
wire [2:0] PIPERX7STATUSGT;
|
799 |
|
|
wire PIPERX7VALIDGT;
|
800 |
|
|
|
801 |
|
|
wire filter_pipe_upconfig_fix_3451;
|
802 |
|
|
|
803 |
|
|
|
804 |
|
|
// Assignments to outputs
|
805 |
|
|
|
806 |
|
|
assign TRNCLK = USERCLK;
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
|
810 |
|
|
|
811 |
|
|
//-------------------------------------------------------
|
812 |
|
|
// Virtex6 PCI Express Block Module
|
813 |
|
|
//-------------------------------------------------------
|
814 |
|
|
PCIE_2_0 #(
|
815 |
|
|
|
816 |
|
|
.AER_BASE_PTR ( AER_BASE_PTR ),
|
817 |
|
|
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
|
818 |
|
|
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
|
819 |
|
|
.AER_CAP_ID ( AER_CAP_ID ),
|
820 |
|
|
.AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
|
821 |
|
|
.AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
|
822 |
|
|
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
|
823 |
|
|
.AER_CAP_ON ( AER_CAP_ON ),
|
824 |
|
|
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
|
825 |
|
|
.AER_CAP_VERSION ( AER_CAP_VERSION ),
|
826 |
|
|
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
|
827 |
|
|
.BAR0 ( BAR0 ),
|
828 |
|
|
.BAR1 ( BAR1 ),
|
829 |
|
|
.BAR2 ( BAR2 ),
|
830 |
|
|
.BAR3 ( BAR3 ),
|
831 |
|
|
.BAR4 ( BAR4 ),
|
832 |
|
|
.BAR5 ( BAR5 ),
|
833 |
|
|
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
|
834 |
|
|
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
|
835 |
|
|
.CLASS_CODE ( CLASS_CODE ),
|
836 |
|
|
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
|
837 |
|
|
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
|
838 |
|
|
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
|
839 |
|
|
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
|
840 |
|
|
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
|
841 |
|
|
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
|
842 |
|
|
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
|
843 |
|
|
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
|
844 |
|
|
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
|
845 |
|
|
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
|
846 |
|
|
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
|
847 |
|
|
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
|
848 |
|
|
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
|
849 |
|
|
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
|
850 |
|
|
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
|
851 |
|
|
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
|
852 |
|
|
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
|
853 |
|
|
.DEVICE_ID ( DEVICE_ID ),
|
854 |
|
|
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
|
855 |
|
|
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
|
856 |
|
|
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
|
857 |
|
|
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
|
858 |
|
|
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
|
859 |
|
|
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
|
860 |
|
|
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
|
861 |
|
|
.DSN_BASE_PTR ( DSN_BASE_PTR ),
|
862 |
|
|
.DSN_CAP_ID ( DSN_CAP_ID ),
|
863 |
|
|
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
|
864 |
|
|
.DSN_CAP_ON ( DSN_CAP_ON ),
|
865 |
|
|
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
|
866 |
|
|
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
|
867 |
|
|
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
|
868 |
|
|
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
|
869 |
|
|
.EXPANSION_ROM ( EXPANSION_ROM ),
|
870 |
|
|
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
|
871 |
|
|
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
|
872 |
|
|
.HEADER_TYPE ( HEADER_TYPE ),
|
873 |
|
|
.INFER_EI ( INFER_EI ),
|
874 |
|
|
.INTERRUPT_PIN ( INTERRUPT_PIN ),
|
875 |
|
|
.IS_SWITCH ( IS_SWITCH ),
|
876 |
|
|
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
|
877 |
|
|
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
|
878 |
|
|
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
|
879 |
|
|
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
|
880 |
|
|
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
|
881 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
|
882 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
|
883 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
|
884 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
|
885 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
|
886 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
|
887 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
|
888 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
|
889 |
|
|
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
|
890 |
|
|
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
|
891 |
|
|
.LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
|
892 |
|
|
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
|
893 |
|
|
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
|
894 |
|
|
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
|
895 |
|
|
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
|
896 |
|
|
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
|
897 |
|
|
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
|
898 |
|
|
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
|
899 |
|
|
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
|
900 |
|
|
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
|
901 |
|
|
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
|
902 |
|
|
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
|
903 |
|
|
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
|
904 |
|
|
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
|
905 |
|
|
.MSI_BASE_PTR ( MSI_BASE_PTR ),
|
906 |
|
|
.MSI_CAP_ID ( MSI_CAP_ID ),
|
907 |
|
|
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
|
908 |
|
|
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
|
909 |
|
|
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
|
910 |
|
|
.MSI_CAP_ON ( MSI_CAP_ON ),
|
911 |
|
|
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
|
912 |
|
|
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
|
913 |
|
|
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
|
914 |
|
|
.MSIX_CAP_ID ( MSIX_CAP_ID ),
|
915 |
|
|
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
|
916 |
|
|
.MSIX_CAP_ON ( MSIX_CAP_ON ),
|
917 |
|
|
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
|
918 |
|
|
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
|
919 |
|
|
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
|
920 |
|
|
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
|
921 |
|
|
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
|
922 |
|
|
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
|
923 |
|
|
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
|
924 |
|
|
.N_FTS_GEN1 ( N_FTS_GEN1 ),
|
925 |
|
|
.N_FTS_GEN2 ( N_FTS_GEN2 ),
|
926 |
|
|
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
|
927 |
|
|
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
|
928 |
|
|
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
|
929 |
|
|
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
|
930 |
|
|
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
|
931 |
|
|
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
|
932 |
|
|
.PCIE_CAP_ON ( PCIE_CAP_ON ),
|
933 |
|
|
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
|
934 |
|
|
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
|
935 |
|
|
.PCIE_REVISION ( PCIE_REVISION ),
|
936 |
|
|
.PGL0_LANE ( PGL0_LANE ),
|
937 |
|
|
.PGL1_LANE ( PGL1_LANE ),
|
938 |
|
|
.PGL2_LANE ( PGL2_LANE ),
|
939 |
|
|
.PGL3_LANE ( PGL3_LANE ),
|
940 |
|
|
.PGL4_LANE ( PGL4_LANE ),
|
941 |
|
|
.PGL5_LANE ( PGL5_LANE ),
|
942 |
|
|
.PGL6_LANE ( PGL6_LANE ),
|
943 |
|
|
.PGL7_LANE ( PGL7_LANE ),
|
944 |
|
|
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
|
945 |
|
|
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
|
946 |
|
|
.PM_BASE_PTR ( PM_BASE_PTR ),
|
947 |
|
|
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
|
948 |
|
|
.PM_CAP_DSI ( PM_CAP_DSI ),
|
949 |
|
|
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
|
950 |
|
|
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
|
951 |
|
|
.PM_CAP_ID ( PM_CAP_ID ),
|
952 |
|
|
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
|
953 |
|
|
.PM_CAP_ON ( PM_CAP_ON ),
|
954 |
|
|
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
|
955 |
|
|
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
|
956 |
|
|
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
|
957 |
|
|
.PM_CAP_VERSION ( PM_CAP_VERSION ),
|
958 |
|
|
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
|
959 |
|
|
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
|
960 |
|
|
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
|
961 |
|
|
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
|
962 |
|
|
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
|
963 |
|
|
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
|
964 |
|
|
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
|
965 |
|
|
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
|
966 |
|
|
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
|
967 |
|
|
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
|
968 |
|
|
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
|
969 |
|
|
.PM_DATA0 ( PM_DATA0 ),
|
970 |
|
|
.PM_DATA1 ( PM_DATA1 ),
|
971 |
|
|
.PM_DATA2 ( PM_DATA2 ),
|
972 |
|
|
.PM_DATA3 ( PM_DATA3 ),
|
973 |
|
|
.PM_DATA4 ( PM_DATA4 ),
|
974 |
|
|
.PM_DATA5 ( PM_DATA5 ),
|
975 |
|
|
.PM_DATA6 ( PM_DATA6 ),
|
976 |
|
|
.PM_DATA7 ( PM_DATA7 ),
|
977 |
|
|
.RECRC_CHK ( RECRC_CHK ),
|
978 |
|
|
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
|
979 |
|
|
.REVISION_ID ( REVISION_ID ),
|
980 |
|
|
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
|
981 |
|
|
.SELECT_DLL_IF ( SELECT_DLL_IF ),
|
982 |
|
|
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
|
983 |
|
|
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
|
984 |
|
|
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
|
985 |
|
|
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
|
986 |
|
|
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
|
987 |
|
|
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
|
988 |
|
|
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
|
989 |
|
|
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
|
990 |
|
|
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
|
991 |
|
|
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
|
992 |
|
|
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
|
993 |
|
|
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
|
994 |
|
|
.SPARE_BIT0 ( SPARE_BIT0 ),
|
995 |
|
|
.SPARE_BIT1 ( SPARE_BIT1 ),
|
996 |
|
|
.SPARE_BIT2 ( SPARE_BIT2 ),
|
997 |
|
|
.SPARE_BIT3 ( SPARE_BIT3 ),
|
998 |
|
|
.SPARE_BIT4 ( SPARE_BIT4 ),
|
999 |
|
|
.SPARE_BIT5 ( SPARE_BIT5 ),
|
1000 |
|
|
.SPARE_BIT6 ( SPARE_BIT6 ),
|
1001 |
|
|
.SPARE_BIT7 ( SPARE_BIT7 ),
|
1002 |
|
|
.SPARE_BIT8 ( SPARE_BIT8 ),
|
1003 |
|
|
.SPARE_BYTE0 ( SPARE_BYTE0 ),
|
1004 |
|
|
.SPARE_BYTE1 ( SPARE_BYTE1 ),
|
1005 |
|
|
.SPARE_BYTE2 ( SPARE_BYTE2 ),
|
1006 |
|
|
.SPARE_BYTE3 ( SPARE_BYTE3 ),
|
1007 |
|
|
.SPARE_WORD0 ( SPARE_WORD0 ),
|
1008 |
|
|
.SPARE_WORD1 ( SPARE_WORD1 ),
|
1009 |
|
|
.SPARE_WORD2 ( SPARE_WORD2 ),
|
1010 |
|
|
.SPARE_WORD3 ( SPARE_WORD3 ),
|
1011 |
|
|
.SUBSYSTEM_ID ( SUBSYSTEM_ID ),
|
1012 |
|
|
.SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
|
1013 |
|
|
.TL_RBYPASS ( TL_RBYPASS ),
|
1014 |
|
|
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
|
1015 |
|
|
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
|
1016 |
|
|
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
|
1017 |
|
|
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
|
1018 |
|
|
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
|
1019 |
|
|
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
|
1020 |
|
|
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
|
1021 |
|
|
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
|
1022 |
|
|
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
|
1023 |
|
|
.UPSTREAM_FACING ( UPSTREAM_FACING ),
|
1024 |
|
|
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
|
1025 |
|
|
.UR_INV_REQ ( UR_INV_REQ ),
|
1026 |
|
|
.USER_CLK_FREQ ( USER_CLK_FREQ ),
|
1027 |
|
|
.VC_BASE_PTR ( VC_BASE_PTR ),
|
1028 |
|
|
.VC_CAP_ID ( VC_CAP_ID ),
|
1029 |
|
|
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
|
1030 |
|
|
.VC_CAP_ON ( VC_CAP_ON ),
|
1031 |
|
|
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
|
1032 |
|
|
.VC_CAP_VERSION ( VC_CAP_VERSION ),
|
1033 |
|
|
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
|
1034 |
|
|
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
|
1035 |
|
|
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
|
1036 |
|
|
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
|
1037 |
|
|
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
|
1038 |
|
|
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
|
1039 |
|
|
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
|
1040 |
|
|
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
|
1041 |
|
|
.VENDOR_ID ( VENDOR_ID ),
|
1042 |
|
|
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
|
1043 |
|
|
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
|
1044 |
|
|
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
|
1045 |
|
|
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
|
1046 |
|
|
.VSEC_CAP_ID ( VSEC_CAP_ID ),
|
1047 |
|
|
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
|
1048 |
|
|
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
|
1049 |
|
|
.VSEC_CAP_ON ( VSEC_CAP_ON ),
|
1050 |
|
|
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
|
1051 |
|
|
|
1052 |
|
|
)
|
1053 |
|
|
pcie_block_i (
|
1054 |
|
|
|
1055 |
|
|
.CFGAERECRCCHECKEN ( CFGAERECRCCHECKEN ),
|
1056 |
|
|
.CFGAERECRCGENEN ( CFGAERECRCGENEN ),
|
1057 |
|
|
.CFGCOMMANDBUSMASTERENABLE ( CFGCOMMANDBUSMASTERENABLE ),
|
1058 |
|
|
.CFGCOMMANDINTERRUPTDISABLE ( CFGCOMMANDINTERRUPTDISABLE ),
|
1059 |
|
|
.CFGCOMMANDIOENABLE ( CFGCOMMANDIOENABLE ),
|
1060 |
|
|
.CFGCOMMANDMEMENABLE ( CFGCOMMANDMEMENABLE ),
|
1061 |
|
|
.CFGCOMMANDSERREN ( CFGCOMMANDSERREN ),
|
1062 |
|
|
.CFGDEVCONTROLAUXPOWEREN ( CFGDEVCONTROLAUXPOWEREN ),
|
1063 |
|
|
.CFGDEVCONTROLCORRERRREPORTINGEN ( CFGDEVCONTROLCORRERRREPORTINGEN ),
|
1064 |
|
|
.CFGDEVCONTROLENABLERO ( CFGDEVCONTROLENABLERO ),
|
1065 |
|
|
.CFGDEVCONTROLEXTTAGEN ( CFGDEVCONTROLEXTTAGEN ),
|
1066 |
|
|
.CFGDEVCONTROLFATALERRREPORTINGEN ( CFGDEVCONTROLFATALERRREPORTINGEN ),
|
1067 |
|
|
.CFGDEVCONTROLMAXPAYLOAD ( CFGDEVCONTROLMAXPAYLOAD ),
|
1068 |
|
|
.CFGDEVCONTROLMAXREADREQ ( CFGDEVCONTROLMAXREADREQ ),
|
1069 |
|
|
.CFGDEVCONTROLNONFATALREPORTINGEN ( CFGDEVCONTROLNONFATALREPORTINGEN ),
|
1070 |
|
|
.CFGDEVCONTROLNOSNOOPEN ( CFGDEVCONTROLNOSNOOPEN ),
|
1071 |
|
|
.CFGDEVCONTROLPHANTOMEN ( CFGDEVCONTROLPHANTOMEN ),
|
1072 |
|
|
.CFGDEVCONTROLURERRREPORTINGEN ( CFGDEVCONTROLURERRREPORTINGEN ),
|
1073 |
|
|
.CFGDEVCONTROL2CPLTIMEOUTDIS ( CFGDEVCONTROL2CPLTIMEOUTDIS ),
|
1074 |
|
|
.CFGDEVCONTROL2CPLTIMEOUTVAL ( CFGDEVCONTROL2CPLTIMEOUTVAL ),
|
1075 |
|
|
.CFGDEVSTATUSCORRERRDETECTED ( CFGDEVSTATUSCORRERRDETECTED ),
|
1076 |
|
|
.CFGDEVSTATUSFATALERRDETECTED ( CFGDEVSTATUSFATALERRDETECTED ),
|
1077 |
|
|
.CFGDEVSTATUSNONFATALERRDETECTED ( CFGDEVSTATUSNONFATALERRDETECTED ),
|
1078 |
|
|
.CFGDEVSTATUSURDETECTED ( CFGDEVSTATUSURDETECTED ),
|
1079 |
|
|
.CFGDO ( CFGDO ),
|
1080 |
|
|
.CFGERRAERHEADERLOGSETN ( CFGERRAERHEADERLOGSETN ),
|
1081 |
|
|
|
1082 |
|
|
.CFGERRCPLRDYN ( CFGERRCPLRDYN ),
|
1083 |
|
|
.CFGINTERRUPTDO ( CFGINTERRUPTDO ),
|
1084 |
|
|
.CFGINTERRUPTMMENABLE ( CFGINTERRUPTMMENABLE ),
|
1085 |
|
|
.CFGINTERRUPTMSIENABLE ( CFGINTERRUPTMSIENABLE ),
|
1086 |
|
|
.CFGINTERRUPTMSIXENABLE ( CFGINTERRUPTMSIXENABLE ),
|
1087 |
|
|
.CFGINTERRUPTMSIXFM ( CFGINTERRUPTMSIXFM ),
|
1088 |
|
|
.CFGINTERRUPTRDYN ( CFGINTERRUPTRDYN ),
|
1089 |
|
|
.CFGLINKCONTROLRCB ( CFGLINKCONTROLRCB ),
|
1090 |
|
|
.CFGLINKCONTROLASPMCONTROL ( CFGLINKCONTROLASPMCONTROL ),
|
1091 |
|
|
.CFGLINKCONTROLAUTOBANDWIDTHINTEN ( CFGLINKCONTROLAUTOBANDWIDTHINTEN ),
|
1092 |
|
|
.CFGLINKCONTROLBANDWIDTHINTEN ( CFGLINKCONTROLBANDWIDTHINTEN ),
|
1093 |
|
|
.CFGLINKCONTROLCLOCKPMEN ( CFGLINKCONTROLCLOCKPMEN ),
|
1094 |
|
|
.CFGLINKCONTROLCOMMONCLOCK ( CFGLINKCONTROLCOMMONCLOCK ),
|
1095 |
|
|
.CFGLINKCONTROLEXTENDEDSYNC ( CFGLINKCONTROLEXTENDEDSYNC ),
|
1096 |
|
|
.CFGLINKCONTROLHWAUTOWIDTHDIS ( CFGLINKCONTROLHWAUTOWIDTHDIS ),
|
1097 |
|
|
.CFGLINKCONTROLLINKDISABLE ( CFGLINKCONTROLLINKDISABLE ),
|
1098 |
|
|
.CFGLINKCONTROLRETRAINLINK ( CFGLINKCONTROLRETRAINLINK ),
|
1099 |
|
|
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS ( CFGLINKSTATUSAUTOBANDWIDTHSTATUS ),
|
1100 |
|
|
.CFGLINKSTATUSBANDWITHSTATUS ( CFGLINKSTATUSBANDWITHSTATUS ),
|
1101 |
|
|
.CFGLINKSTATUSCURRENTSPEED ( CFGLINKSTATUSCURRENTSPEED ),
|
1102 |
|
|
.CFGLINKSTATUSDLLACTIVE ( CFGLINKSTATUSDLLACTIVE ),
|
1103 |
|
|
.CFGLINKSTATUSLINKTRAINING ( CFGLINKSTATUSLINKTRAINING ),
|
1104 |
|
|
.CFGLINKSTATUSNEGOTIATEDWIDTH ( CFGLINKSTATUSNEGOTIATEDWIDTH ),
|
1105 |
|
|
.CFGMSGDATA ( CFGMSGDATA ),
|
1106 |
|
|
.CFGMSGRECEIVED ( CFGMSGRECEIVED ),
|
1107 |
|
|
|
1108 |
|
|
.CFGMSGRECEIVEDASSERTINTA ( CFGMSGRECEIVEDASSERTINTA ),
|
1109 |
|
|
.CFGMSGRECEIVEDASSERTINTB ( CFGMSGRECEIVEDASSERTINTB ),
|
1110 |
|
|
.CFGMSGRECEIVEDASSERTINTC ( CFGMSGRECEIVEDASSERTINTC ),
|
1111 |
|
|
.CFGMSGRECEIVEDASSERTINTD ( CFGMSGRECEIVEDASSERTINTD ),
|
1112 |
|
|
.CFGMSGRECEIVEDDEASSERTINTA ( CFGMSGRECEIVEDDEASSERTINTA ),
|
1113 |
|
|
.CFGMSGRECEIVEDDEASSERTINTB ( CFGMSGRECEIVEDDEASSERTINTB ),
|
1114 |
|
|
.CFGMSGRECEIVEDDEASSERTINTC ( CFGMSGRECEIVEDDEASSERTINTC ),
|
1115 |
|
|
.CFGMSGRECEIVEDDEASSERTINTD ( CFGMSGRECEIVEDDEASSERTINTD ),
|
1116 |
|
|
.CFGMSGRECEIVEDERRCOR ( CFGMSGRECEIVEDERRCOR ),
|
1117 |
|
|
.CFGMSGRECEIVEDERRFATAL ( CFGMSGRECEIVEDERRFATAL ),
|
1118 |
|
|
.CFGMSGRECEIVEDERRNONFATAL ( CFGMSGRECEIVEDERRNONFATAL ),
|
1119 |
|
|
|
1120 |
|
|
.CFGMSGRECEIVEDPMASNAK ( CFGMSGRECEIVEDPMASNAK ),
|
1121 |
|
|
.CFGMSGRECEIVEDPMETO ( CFGMSGRECEIVEDPMETO ),
|
1122 |
|
|
|
1123 |
|
|
|
1124 |
|
|
.CFGMSGRECEIVEDPMETOACK ( CFGMSGRECEIVEDPMETOACK ),
|
1125 |
|
|
.CFGMSGRECEIVEDPMPME ( CFGMSGRECEIVEDPMPME ),
|
1126 |
|
|
|
1127 |
|
|
|
1128 |
|
|
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT ( CFGMSGRECEIVEDSETSLOTPOWERLIMIT ),
|
1129 |
|
|
.CFGMSGRECEIVEDUNLOCK ( CFGMSGRECEIVEDUNLOCK ),
|
1130 |
|
|
.CFGPCIELINKSTATE ( CFGPCIELINKSTATE ),
|
1131 |
|
|
|
1132 |
|
|
|
1133 |
|
|
.CFGPMRCVASREQL1N ( CFGPMRCVASREQL1N ),
|
1134 |
|
|
.CFGPMRCVENTERL1N ( CFGPMRCVENTERL1N ),
|
1135 |
|
|
.CFGPMRCVENTERL23N ( CFGPMRCVENTERL23N ),
|
1136 |
|
|
|
1137 |
|
|
.CFGPMRCVREQACKN ( CFGPMRCVREQACKN ),
|
1138 |
|
|
.CFGPMCSRPMEEN( CFGPMCSRPMEEN ),
|
1139 |
|
|
.CFGPMCSRPMESTATUS( CFGPMCSRPMESTATUS ),
|
1140 |
|
|
.CFGPMCSRPOWERSTATE( CFGPMCSRPOWERSTATE ),
|
1141 |
|
|
.CFGRDWRDONEN ( CFGRDWRDONEN ),
|
1142 |
|
|
|
1143 |
|
|
.CFGSLOTCONTROLELECTROMECHILCTLPULSE ( CFGSLOTCONTROLELECTROMECHILCTLPULSE ),
|
1144 |
|
|
|
1145 |
|
|
.CFGTRANSACTION ( CFGTRANSACTION ),
|
1146 |
|
|
.CFGTRANSACTIONADDR ( CFGTRANSACTIONADDR ),
|
1147 |
|
|
.CFGTRANSACTIONTYPE ( CFGTRANSACTIONTYPE ),
|
1148 |
|
|
|
1149 |
|
|
.CFGVCTCVCMAP ( CFGVCTCVCMAP ),
|
1150 |
|
|
.DBGSCLRA ( DBGSCLRA ),
|
1151 |
|
|
.DBGSCLRB ( DBGSCLRB ),
|
1152 |
|
|
.DBGSCLRC ( DBGSCLRC ),
|
1153 |
|
|
.DBGSCLRD ( DBGSCLRD ),
|
1154 |
|
|
.DBGSCLRE ( DBGSCLRE ),
|
1155 |
|
|
.DBGSCLRF ( DBGSCLRF ),
|
1156 |
|
|
.DBGSCLRG ( DBGSCLRG ),
|
1157 |
|
|
.DBGSCLRH ( DBGSCLRH ),
|
1158 |
|
|
.DBGSCLRI ( DBGSCLRI ),
|
1159 |
|
|
.DBGSCLRJ ( DBGSCLRJ ),
|
1160 |
|
|
.DBGSCLRK ( DBGSCLRK ),
|
1161 |
|
|
.DBGVECA ( DBGVECA ),
|
1162 |
|
|
.DBGVECB ( DBGVECB ),
|
1163 |
|
|
.DBGVECC ( DBGVECC ),
|
1164 |
|
|
.DRPDO ( PCIEDRPDO ),
|
1165 |
|
|
.DRPDRDY ( PCIEDRPDRDY ),
|
1166 |
|
|
.LL2BADDLLPERRN ( LL2BADDLLPERRN ),
|
1167 |
|
|
.LL2BADTLPERRN ( LL2BADTLPERRN ),
|
1168 |
|
|
.LL2PROTOCOLERRN ( LL2PROTOCOLERRN ),
|
1169 |
|
|
.LL2REPLAYROERRN ( LL2REPLAYROERRN ),
|
1170 |
|
|
.LL2REPLAYTOERRN ( LL2REPLAYTOERRN ),
|
1171 |
|
|
.LL2SUSPENDOKN ( LL2SUSPENDOKN ),
|
1172 |
|
|
.LL2TFCINIT1SEQN ( LL2TFCINIT1SEQN ),
|
1173 |
|
|
.LL2TFCINIT2SEQN ( LL2TFCINIT2SEQN ),
|
1174 |
|
|
.MIMRXRADDR ( MIMRXRADDR ),
|
1175 |
|
|
.MIMRXRCE ( MIMRXRCE ),
|
1176 |
|
|
.MIMRXREN ( MIMRXREN ),
|
1177 |
|
|
.MIMRXWADDR ( MIMRXWADDR ),
|
1178 |
|
|
.MIMRXWDATA ( MIMRXWDATA ),
|
1179 |
|
|
.MIMRXWEN ( MIMRXWEN ),
|
1180 |
|
|
.MIMTXRADDR ( MIMTXRADDR ),
|
1181 |
|
|
.MIMTXRCE ( MIMTXRCE ),
|
1182 |
|
|
.MIMTXREN ( MIMTXREN ),
|
1183 |
|
|
.MIMTXWADDR ( MIMTXWADDR ),
|
1184 |
|
|
.MIMTXWDATA ( MIMTXWDATA ),
|
1185 |
|
|
.MIMTXWEN ( MIMTXWEN ),
|
1186 |
|
|
.PIPERX0POLARITY ( PIPERX0POLARITY ),
|
1187 |
|
|
.PIPERX1POLARITY ( PIPERX1POLARITY ),
|
1188 |
|
|
.PIPERX2POLARITY ( PIPERX2POLARITY ),
|
1189 |
|
|
.PIPERX3POLARITY ( PIPERX3POLARITY ),
|
1190 |
|
|
.PIPERX4POLARITY ( PIPERX4POLARITY ),
|
1191 |
|
|
.PIPERX5POLARITY ( PIPERX5POLARITY ),
|
1192 |
|
|
.PIPERX6POLARITY ( PIPERX6POLARITY ),
|
1193 |
|
|
.PIPERX7POLARITY ( PIPERX7POLARITY ),
|
1194 |
|
|
.PIPETXDEEMPH ( PIPETXDEEMPH ),
|
1195 |
|
|
.PIPETXMARGIN ( PIPETXMARGIN ),
|
1196 |
|
|
.PIPETXRATE ( PIPETXRATE ),
|
1197 |
|
|
.PIPETXRCVRDET ( PIPETXRCVRDET ),
|
1198 |
|
|
.PIPETXRESET ( PIPETXRESET ),
|
1199 |
|
|
.PIPETX0CHARISK ( PIPETX0CHARISK ),
|
1200 |
|
|
.PIPETX0COMPLIANCE ( PIPETX0COMPLIANCE ),
|
1201 |
|
|
.PIPETX0DATA ( PIPETX0DATA ),
|
1202 |
|
|
.PIPETX0ELECIDLE ( PIPETX0ELECIDLE ),
|
1203 |
|
|
.PIPETX0POWERDOWN ( PIPETX0POWERDOWN ),
|
1204 |
|
|
.PIPETX1CHARISK ( PIPETX1CHARISK ),
|
1205 |
|
|
.PIPETX1COMPLIANCE ( PIPETX1COMPLIANCE ),
|
1206 |
|
|
.PIPETX1DATA ( PIPETX1DATA ),
|
1207 |
|
|
.PIPETX1ELECIDLE ( PIPETX1ELECIDLE ),
|
1208 |
|
|
.PIPETX1POWERDOWN ( PIPETX1POWERDOWN ),
|
1209 |
|
|
.PIPETX2CHARISK ( PIPETX2CHARISK ),
|
1210 |
|
|
.PIPETX2COMPLIANCE ( PIPETX2COMPLIANCE ),
|
1211 |
|
|
.PIPETX2DATA ( PIPETX2DATA ),
|
1212 |
|
|
.PIPETX2ELECIDLE ( PIPETX2ELECIDLE ),
|
1213 |
|
|
.PIPETX2POWERDOWN ( PIPETX2POWERDOWN ),
|
1214 |
|
|
.PIPETX3CHARISK ( PIPETX3CHARISK ),
|
1215 |
|
|
.PIPETX3COMPLIANCE ( PIPETX3COMPLIANCE ),
|
1216 |
|
|
.PIPETX3DATA ( PIPETX3DATA ),
|
1217 |
|
|
.PIPETX3ELECIDLE ( PIPETX3ELECIDLE ),
|
1218 |
|
|
.PIPETX3POWERDOWN ( PIPETX3POWERDOWN ),
|
1219 |
|
|
.PIPETX4CHARISK ( PIPETX4CHARISK ),
|
1220 |
|
|
.PIPETX4COMPLIANCE ( PIPETX4COMPLIANCE ),
|
1221 |
|
|
.PIPETX4DATA ( PIPETX4DATA ),
|
1222 |
|
|
.PIPETX4ELECIDLE ( PIPETX4ELECIDLE ),
|
1223 |
|
|
.PIPETX4POWERDOWN ( PIPETX4POWERDOWN ),
|
1224 |
|
|
.PIPETX5CHARISK ( PIPETX5CHARISK ),
|
1225 |
|
|
.PIPETX5COMPLIANCE ( PIPETX5COMPLIANCE ),
|
1226 |
|
|
.PIPETX5DATA ( PIPETX5DATA ),
|
1227 |
|
|
.PIPETX5ELECIDLE ( PIPETX5ELECIDLE ),
|
1228 |
|
|
.PIPETX5POWERDOWN ( PIPETX5POWERDOWN ),
|
1229 |
|
|
.PIPETX6CHARISK ( PIPETX6CHARISK ),
|
1230 |
|
|
.PIPETX6COMPLIANCE ( PIPETX6COMPLIANCE ),
|
1231 |
|
|
.PIPETX6DATA ( PIPETX6DATA ),
|
1232 |
|
|
.PIPETX6ELECIDLE ( PIPETX6ELECIDLE ),
|
1233 |
|
|
.PIPETX6POWERDOWN ( PIPETX6POWERDOWN ),
|
1234 |
|
|
.PIPETX7CHARISK ( PIPETX7CHARISK ),
|
1235 |
|
|
.PIPETX7COMPLIANCE ( PIPETX7COMPLIANCE ),
|
1236 |
|
|
.PIPETX7DATA ( PIPETX7DATA ),
|
1237 |
|
|
.PIPETX7ELECIDLE ( PIPETX7ELECIDLE ),
|
1238 |
|
|
.PIPETX7POWERDOWN ( PIPETX7POWERDOWN ),
|
1239 |
|
|
.PLDBGVEC ( PLDBGVEC ),
|
1240 |
|
|
.PLINITIALLINKWIDTH ( PLINITIALLINKWIDTH ),
|
1241 |
|
|
.PLLANEREVERSALMODE ( PLLANEREVERSALMODE ),
|
1242 |
|
|
.PLLINKGEN2CAP ( PLLINKGEN2CAP ),
|
1243 |
|
|
.PLLINKPARTNERGEN2SUPPORTED ( PLLINKPARTNERGEN2SUPPORTED ),
|
1244 |
|
|
.PLLINKUPCFGCAP ( PLLINKUPCFGCAP ),
|
1245 |
|
|
.PLLTSSMSTATE ( PLLTSSMSTATE ),
|
1246 |
|
|
.PLPHYLNKUPN ( PLPHYLNKUPN ),
|
1247 |
|
|
.PLRECEIVEDHOTRST ( PLRECEIVEDHOTRST ),
|
1248 |
|
|
.PLRXPMSTATE ( PLRXPMSTATE ),
|
1249 |
|
|
.PLSELLNKRATE ( PLSELLNKRATE ),
|
1250 |
|
|
.PLSELLNKWIDTH ( PLSELLNKWIDTH ),
|
1251 |
|
|
.PLTXPMSTATE ( PLTXPMSTATE ),
|
1252 |
|
|
.PL2LINKUPN ( PL2LINKUPN ),
|
1253 |
|
|
.PL2RECEIVERERRN ( PL2RECEIVERERRN ),
|
1254 |
|
|
.PL2RECOVERYN ( PL2RECOVERYN ),
|
1255 |
|
|
.PL2RXELECIDLE ( PL2RXELECIDLE ),
|
1256 |
|
|
.PL2SUSPENDOK ( PL2SUSPENDOK ),
|
1257 |
|
|
.RECEIVEDFUNCLVLRSTN ( RECEIVEDFUNCLVLRSTN ),
|
1258 |
|
|
.LNKCLKEN ( LNKCLKEN ),
|
1259 |
|
|
.TL2ASPMSUSPENDCREDITCHECKOKN ( TL2ASPMSUSPENDCREDITCHECKOKN ),
|
1260 |
|
|
.TL2ASPMSUSPENDREQN ( TL2ASPMSUSPENDREQN ),
|
1261 |
|
|
.TL2PPMSUSPENDOKN ( TL2PPMSUSPENDOKN ),
|
1262 |
|
|
.TRNFCCPLD ( TRNFCCPLD ),
|
1263 |
|
|
.TRNFCCPLH ( TRNFCCPLH ),
|
1264 |
|
|
.TRNFCNPD ( TRNFCNPD ),
|
1265 |
|
|
.TRNFCNPH ( TRNFCNPH ),
|
1266 |
|
|
.TRNFCPD ( TRNFCPD ),
|
1267 |
|
|
.TRNFCPH ( TRNFCPH ),
|
1268 |
|
|
.TRNLNKUPN ( TRNLNKUPN ),
|
1269 |
|
|
.TRNRBARHITN ( TRNRBARHITN ),
|
1270 |
|
|
.TRNRD ( TRNRD ),
|
1271 |
|
|
|
1272 |
|
|
.TRNRDLLPDATA ( ),
|
1273 |
|
|
.TRNRDLLPSRCRDYN ( TRNRDLLPSRCRDYN ),
|
1274 |
|
|
.TRNRECRCERRN ( TRNRECRCERRN ),
|
1275 |
|
|
.TRNREOFN ( TRNREOFN ),
|
1276 |
|
|
.TRNRERRFWDN ( TRNRERRFWDN ),
|
1277 |
|
|
.TRNRREMN ( TRNRREMN ),
|
1278 |
|
|
.TRNRSOFN ( TRNRSOFN ),
|
1279 |
|
|
.TRNRSRCDSCN ( TRNRSRCDSCN ),
|
1280 |
|
|
.TRNRSRCRDYN ( TRNRSRCRDYN ),
|
1281 |
|
|
.TRNTBUFAV ( TRNTBUFAV ),
|
1282 |
|
|
.TRNTCFGREQN ( TRNTCFGREQN ),
|
1283 |
|
|
.TRNTDLLPDSTRDYN ( TRNTDLLPDSTRDYN ),
|
1284 |
|
|
.TRNTDSTRDYN ( TRNTDSTRDYN ),
|
1285 |
|
|
.TRNTERRDROPN ( TRNTERRDROPN ),
|
1286 |
|
|
.USERRSTN ( USERRSTN ),
|
1287 |
|
|
.CFGBYTEENN ( CFGBYTEENN ),
|
1288 |
|
|
.CFGDI ( CFGDI ),
|
1289 |
|
|
.CFGDSBUSNUMBER ( CFGDSBUSNUMBER ),
|
1290 |
|
|
.CFGDSDEVICENUMBER ( CFGDSDEVICENUMBER ),
|
1291 |
|
|
.CFGDSFUNCTIONNUMBER ( CFGDSFUNCTIONNUMBER ),
|
1292 |
|
|
.CFGDSN ( CFGDSN ),
|
1293 |
|
|
.CFGDWADDR ( CFGDWADDR ),
|
1294 |
|
|
.CFGERRACSN ( CFGERRACSN ),
|
1295 |
|
|
.CFGERRAERHEADERLOG ( CFGERRAERHEADERLOG ),
|
1296 |
|
|
.CFGERRCORN ( CFGERRCORN ),
|
1297 |
|
|
.CFGERRCPLABORTN ( CFGERRCPLABORTN ),
|
1298 |
|
|
.CFGERRCPLTIMEOUTN ( CFGERRCPLTIMEOUTN ),
|
1299 |
|
|
.CFGERRCPLUNEXPECTN ( CFGERRCPLUNEXPECTN ),
|
1300 |
|
|
.CFGERRECRCN ( CFGERRECRCN ),
|
1301 |
|
|
.CFGERRLOCKEDN ( CFGERRLOCKEDN ),
|
1302 |
|
|
.CFGERRPOSTEDN ( CFGERRPOSTEDN ),
|
1303 |
|
|
.CFGERRTLPCPLHEADER ( CFGERRTLPCPLHEADER ),
|
1304 |
|
|
.CFGERRURN ( CFGERRURN ),
|
1305 |
|
|
.CFGINTERRUPTASSERTN ( CFGINTERRUPTASSERTN ),
|
1306 |
|
|
.CFGINTERRUPTDI ( CFGINTERRUPTDI ),
|
1307 |
|
|
.CFGINTERRUPTN ( CFGINTERRUPTN ),
|
1308 |
|
|
.CFGPMDIRECTASPML1N ( CFGPMDIRECTASPML1N ),
|
1309 |
|
|
.CFGPMSENDPMACKN ( CFGPMSENDPMACKN ),
|
1310 |
|
|
.CFGPMSENDPMETON ( CFGPMSENDPMETON ),
|
1311 |
|
|
.CFGPMSENDPMNAKN ( CFGPMSENDPMNAKN ),
|
1312 |
|
|
.CFGPMTURNOFFOKN ( CFGPMTURNOFFOKN ),
|
1313 |
|
|
.CFGPMWAKEN ( CFGPMWAKEN ),
|
1314 |
|
|
.CFGPORTNUMBER ( CFGPORTNUMBER ),
|
1315 |
|
|
.CFGRDENN ( CFGRDENN ),
|
1316 |
|
|
.CFGTRNPENDINGN ( CFGTRNPENDINGN ),
|
1317 |
|
|
.CFGWRENN ( CFGWRENN ),
|
1318 |
|
|
.CFGWRREADONLYN ( CFGWRREADONLYN ),
|
1319 |
|
|
.CFGWRRW1CASRWN ( CFGWRRW1CASRWN ),
|
1320 |
|
|
.CMRSTN ( CMRSTN ),
|
1321 |
|
|
.CMSTICKYRSTN ( CMSTICKYRSTN ),
|
1322 |
|
|
.DBGMODE ( DBGMODE ),
|
1323 |
|
|
.DBGSUBMODE ( DBGSUBMODE ),
|
1324 |
|
|
.DLRSTN ( DLRSTN ),
|
1325 |
|
|
.DRPCLK ( PCIEDRPCLK ),
|
1326 |
|
|
.DRPDADDR ( PCIEDRPDADDR ),
|
1327 |
|
|
.DRPDEN ( PCIEDRPDEN ),
|
1328 |
|
|
.DRPDI ( PCIEDRPDI ),
|
1329 |
|
|
.DRPDWE ( PCIEDRPDWE ),
|
1330 |
|
|
.FUNCLVLRSTN ( FUNCLVLRSTN ),
|
1331 |
|
|
.LL2SENDASREQL1N ( LL2SENDASREQL1N ),
|
1332 |
|
|
.LL2SENDENTERL1N ( LL2SENDENTERL1N ),
|
1333 |
|
|
.LL2SENDENTERL23N ( LL2SENDENTERL23N ),
|
1334 |
|
|
.LL2SUSPENDNOWN ( LL2SUSPENDNOWN ),
|
1335 |
|
|
.LL2TLPRCVN ( LL2TLPRCVN ),
|
1336 |
|
|
.MIMRXRDATA ( MIMRXRDATA ),
|
1337 |
|
|
.MIMTXRDATA ( MIMTXRDATA ),
|
1338 |
|
|
.PIPECLK ( PIPECLK ),
|
1339 |
|
|
.PIPERX0CHANISALIGNED ( PIPERX0CHANISALIGNED ),
|
1340 |
|
|
.PIPERX0CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX0CHARISK ),
|
1341 |
|
|
.PIPERX0DATA ( PIPERX0DATA ),
|
1342 |
|
|
.PIPERX0ELECIDLE ( PIPERX0ELECIDLE ),
|
1343 |
|
|
.PIPERX0PHYSTATUS ( PIPERX0PHYSTATUS ),
|
1344 |
|
|
.PIPERX0STATUS ( PIPERX0STATUS ),
|
1345 |
|
|
.PIPERX0VALID ( PIPERX0VALID ),
|
1346 |
|
|
.PIPERX1CHANISALIGNED ( PIPERX1CHANISALIGNED ),
|
1347 |
|
|
.PIPERX1CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX1CHARISK ),
|
1348 |
|
|
.PIPERX1DATA ( PIPERX1DATA ),
|
1349 |
|
|
.PIPERX1ELECIDLE ( PIPERX1ELECIDLE ),
|
1350 |
|
|
.PIPERX1PHYSTATUS ( PIPERX1PHYSTATUS ),
|
1351 |
|
|
.PIPERX1STATUS ( PIPERX1STATUS ),
|
1352 |
|
|
.PIPERX1VALID ( PIPERX1VALID ),
|
1353 |
|
|
.PIPERX2CHANISALIGNED ( PIPERX2CHANISALIGNED ),
|
1354 |
|
|
.PIPERX2CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX2CHARISK ),
|
1355 |
|
|
.PIPERX2DATA ( PIPERX2DATA ),
|
1356 |
|
|
.PIPERX2ELECIDLE ( PIPERX2ELECIDLE ),
|
1357 |
|
|
.PIPERX2PHYSTATUS ( PIPERX2PHYSTATUS ),
|
1358 |
|
|
.PIPERX2STATUS ( PIPERX2STATUS ),
|
1359 |
|
|
.PIPERX2VALID ( PIPERX2VALID ),
|
1360 |
|
|
.PIPERX3CHANISALIGNED ( PIPERX3CHANISALIGNED ),
|
1361 |
|
|
.PIPERX3CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX3CHARISK ),
|
1362 |
|
|
.PIPERX3DATA ( PIPERX3DATA ),
|
1363 |
|
|
.PIPERX3ELECIDLE ( PIPERX3ELECIDLE ),
|
1364 |
|
|
.PIPERX3PHYSTATUS ( PIPERX3PHYSTATUS ),
|
1365 |
|
|
.PIPERX3STATUS ( PIPERX3STATUS ),
|
1366 |
|
|
.PIPERX3VALID ( PIPERX3VALID ),
|
1367 |
|
|
.PIPERX4CHANISALIGNED ( PIPERX4CHANISALIGNED ),
|
1368 |
|
|
.PIPERX4CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX4CHARISK ),
|
1369 |
|
|
.PIPERX4DATA ( PIPERX4DATA ),
|
1370 |
|
|
.PIPERX4ELECIDLE ( PIPERX4ELECIDLE ),
|
1371 |
|
|
.PIPERX4PHYSTATUS ( PIPERX4PHYSTATUS ),
|
1372 |
|
|
.PIPERX4STATUS ( PIPERX4STATUS ),
|
1373 |
|
|
.PIPERX4VALID ( PIPERX4VALID ),
|
1374 |
|
|
.PIPERX5CHANISALIGNED ( PIPERX5CHANISALIGNED ),
|
1375 |
|
|
.PIPERX5CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX5CHARISK ),
|
1376 |
|
|
.PIPERX5DATA ( PIPERX5DATA ),
|
1377 |
|
|
.PIPERX5ELECIDLE ( PIPERX5ELECIDLE ),
|
1378 |
|
|
.PIPERX5PHYSTATUS ( PIPERX5PHYSTATUS ),
|
1379 |
|
|
.PIPERX5STATUS ( PIPERX5STATUS ),
|
1380 |
|
|
.PIPERX5VALID ( PIPERX5VALID ),
|
1381 |
|
|
.PIPERX6CHANISALIGNED ( PIPERX6CHANISALIGNED ),
|
1382 |
|
|
.PIPERX6CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX6CHARISK ),
|
1383 |
|
|
.PIPERX6DATA ( PIPERX6DATA ),
|
1384 |
|
|
.PIPERX6ELECIDLE ( PIPERX6ELECIDLE ),
|
1385 |
|
|
.PIPERX6PHYSTATUS ( PIPERX6PHYSTATUS ),
|
1386 |
|
|
.PIPERX6STATUS ( PIPERX6STATUS ),
|
1387 |
|
|
.PIPERX6VALID ( PIPERX6VALID ),
|
1388 |
|
|
.PIPERX7CHANISALIGNED ( PIPERX7CHANISALIGNED ),
|
1389 |
|
|
.PIPERX7CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX7CHARISK ),
|
1390 |
|
|
.PIPERX7DATA ( PIPERX7DATA ),
|
1391 |
|
|
.PIPERX7ELECIDLE ( PIPERX7ELECIDLE ),
|
1392 |
|
|
.PIPERX7PHYSTATUS ( PIPERX7PHYSTATUS ),
|
1393 |
|
|
.PIPERX7STATUS ( PIPERX7STATUS ),
|
1394 |
|
|
.PIPERX7VALID ( PIPERX7VALID ),
|
1395 |
|
|
.PLDBGMODE ( PLDBGMODE ),
|
1396 |
|
|
.PLDIRECTEDLINKAUTON ( PLDIRECTEDLINKAUTON ),
|
1397 |
|
|
.PLDIRECTEDLINKCHANGE ( PLDIRECTEDLINKCHANGE ),
|
1398 |
|
|
.PLDIRECTEDLINKSPEED ( PLDIRECTEDLINKSPEED ),
|
1399 |
|
|
.PLDIRECTEDLINKWIDTH ( PLDIRECTEDLINKWIDTH ),
|
1400 |
|
|
.PLDOWNSTREAMDEEMPHSOURCE ( PLDOWNSTREAMDEEMPHSOURCE ),
|
1401 |
|
|
.PLRSTN ( PLRSTN ),
|
1402 |
|
|
.PLTRANSMITHOTRST ( PLTRANSMITHOTRST ),
|
1403 |
|
|
.PLUPSTREAMPREFERDEEMPH ( PLUPSTREAMPREFERDEEMPH ),
|
1404 |
|
|
.PL2DIRECTEDLSTATE ( PL2DIRECTEDLSTATE ),
|
1405 |
|
|
.SYSRSTN ( SYSRSTN ),
|
1406 |
|
|
.TLRSTN ( TLRSTN ),
|
1407 |
|
|
.TL2ASPMSUSPENDCREDITCHECKN ( 1'b1),
|
1408 |
|
|
.TL2PPMSUSPENDREQN ( 1'b1 ),
|
1409 |
|
|
.TRNFCSEL ( TRNFCSEL ),
|
1410 |
|
|
.TRNRDSTRDYN ( TRNRDSTRDYN ),
|
1411 |
|
|
.TRNRNPOKN ( TRNRNPOKN ),
|
1412 |
|
|
.TRNTCFGGNTN ( TRNTCFGGNTN ),
|
1413 |
|
|
.TRNTD ( TRNTD ),
|
1414 |
|
|
.TRNTDLLPDATA ( TRNTDLLPDATA ),
|
1415 |
|
|
.TRNTDLLPSRCRDYN ( TRNTDLLPSRCRDYN ),
|
1416 |
|
|
.TRNTECRCGENN ( TRNTECRCGENN ),
|
1417 |
|
|
.TRNTEOFN ( TRNTEOFN ),
|
1418 |
|
|
.TRNTERRFWDN ( TRNTERRFWDN ),
|
1419 |
|
|
.TRNTREMN ( TRNTREMN ),
|
1420 |
|
|
.TRNTSOFN ( TRNTSOFN ),
|
1421 |
|
|
.TRNTSRCDSCN ( TRNTSRCDSCN ),
|
1422 |
|
|
.TRNTSRCRDYN ( TRNTSRCRDYN ),
|
1423 |
|
|
.TRNTSTRN ( TRNTSTRN ),
|
1424 |
|
|
.USERCLK ( USERCLK )
|
1425 |
|
|
|
1426 |
|
|
);
|
1427 |
|
|
|
1428 |
|
|
//-------------------------------------------------------
|
1429 |
|
|
// Virtex6 PIPE Module
|
1430 |
|
|
//-------------------------------------------------------
|
1431 |
|
|
|
1432 |
|
|
pcie_pipe_v6 # (
|
1433 |
|
|
|
1434 |
|
|
.NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
|
1435 |
|
|
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
|
1436 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
1437 |
|
|
|
1438 |
|
|
)
|
1439 |
|
|
pcie_pipe_i (
|
1440 |
|
|
|
1441 |
|
|
// Pipe Per-Link Signals
|
1442 |
|
|
.pipe_tx_rcvr_det_i (PIPETXRCVRDET),
|
1443 |
|
|
.pipe_tx_reset_i (PIPETXRESET),
|
1444 |
|
|
.pipe_tx_rate_i (PIPETXRATE),
|
1445 |
|
|
.pipe_tx_deemph_i (PIPETXDEEMPH),
|
1446 |
|
|
.pipe_tx_margin_i (PIPETXMARGIN),
|
1447 |
|
|
.pipe_tx_swing_i (1'b0),
|
1448 |
|
|
|
1449 |
|
|
.pipe_tx_rcvr_det_o (PIPETXRCVRDETGT),
|
1450 |
|
|
.pipe_tx_reset_o ( ),
|
1451 |
|
|
.pipe_tx_rate_o (PIPETXRATEGT),
|
1452 |
|
|
.pipe_tx_deemph_o (PIPETXDEEMPHGT),
|
1453 |
|
|
.pipe_tx_margin_o (PIPETXMARGINGT),
|
1454 |
|
|
.pipe_tx_swing_o ( ),
|
1455 |
|
|
|
1456 |
|
|
// Pipe Per-Lane Signals - Lane 0
|
1457 |
|
|
.pipe_rx0_char_is_k_o (PIPERX0CHARISK ),
|
1458 |
|
|
.pipe_rx0_data_o (PIPERX0DATA ),
|
1459 |
|
|
.pipe_rx0_valid_o (PIPERX0VALID ),
|
1460 |
|
|
.pipe_rx0_chanisaligned_o (PIPERX0CHANISALIGNED ),
|
1461 |
|
|
.pipe_rx0_status_o (PIPERX0STATUS ),
|
1462 |
|
|
.pipe_rx0_phy_status_o (PIPERX0PHYSTATUS ),
|
1463 |
|
|
.pipe_rx0_elec_idle_i (PIPERX0ELECIDLEGT ),
|
1464 |
|
|
.pipe_rx0_polarity_i (PIPERX0POLARITY ),
|
1465 |
|
|
.pipe_tx0_compliance_i (PIPETX0COMPLIANCE ),
|
1466 |
|
|
.pipe_tx0_char_is_k_i (PIPETX0CHARISK ),
|
1467 |
|
|
.pipe_tx0_data_i (PIPETX0DATA ),
|
1468 |
|
|
.pipe_tx0_elec_idle_i (PIPETX0ELECIDLE ),
|
1469 |
|
|
.pipe_tx0_powerdown_i (PIPETX0POWERDOWN ),
|
1470 |
|
|
|
1471 |
|
|
.pipe_rx0_char_is_k_i (PIPERX0CHARISKGT ),
|
1472 |
|
|
.pipe_rx0_data_i (PIPERX0DATAGT ),
|
1473 |
|
|
.pipe_rx0_valid_i (PIPERX0VALIDGT ),
|
1474 |
|
|
.pipe_rx0_chanisaligned_i (PIPERX0CHANISALIGNEDGT ),
|
1475 |
|
|
.pipe_rx0_status_i (PIPERX0STATUSGT ),
|
1476 |
|
|
.pipe_rx0_phy_status_i (PIPERX0PHYSTATUSGT ),
|
1477 |
|
|
.pipe_rx0_elec_idle_o (PIPERX0ELECIDLE ),
|
1478 |
|
|
.pipe_rx0_polarity_o (PIPERX0POLARITYGT ),
|
1479 |
|
|
.pipe_tx0_compliance_o (PIPETX0COMPLIANCEGT ),
|
1480 |
|
|
.pipe_tx0_char_is_k_o (PIPETX0CHARISKGT ),
|
1481 |
|
|
.pipe_tx0_data_o (PIPETX0DATAGT ),
|
1482 |
|
|
.pipe_tx0_elec_idle_o (PIPETX0ELECIDLEGT ),
|
1483 |
|
|
.pipe_tx0_powerdown_o (PIPETX0POWERDOWNGT ),
|
1484 |
|
|
|
1485 |
|
|
// Pipe Per-Lane Signals - Lane 1
|
1486 |
|
|
.pipe_rx1_char_is_k_o (PIPERX1CHARISK ),
|
1487 |
|
|
.pipe_rx1_data_o (PIPERX1DATA ),
|
1488 |
|
|
.pipe_rx1_valid_o (PIPERX1VALID ),
|
1489 |
|
|
.pipe_rx1_chanisaligned_o (PIPERX1CHANISALIGNED ),
|
1490 |
|
|
.pipe_rx1_status_o (PIPERX1STATUS ),
|
1491 |
|
|
.pipe_rx1_phy_status_o (PIPERX1PHYSTATUS ),
|
1492 |
|
|
.pipe_rx1_elec_idle_i (PIPERX1ELECIDLEGT ),
|
1493 |
|
|
.pipe_rx1_polarity_i (PIPERX1POLARITY ),
|
1494 |
|
|
.pipe_tx1_compliance_i (PIPETX1COMPLIANCE ),
|
1495 |
|
|
.pipe_tx1_char_is_k_i (PIPETX1CHARISK ),
|
1496 |
|
|
.pipe_tx1_data_i (PIPETX1DATA ),
|
1497 |
|
|
.pipe_tx1_elec_idle_i (PIPETX1ELECIDLE ),
|
1498 |
|
|
.pipe_tx1_powerdown_i (PIPETX1POWERDOWN ),
|
1499 |
|
|
|
1500 |
|
|
.pipe_rx1_char_is_k_i (PIPERX1CHARISKGT ),
|
1501 |
|
|
.pipe_rx1_data_i (PIPERX1DATAGT ),
|
1502 |
|
|
.pipe_rx1_valid_i (PIPERX1VALIDGT ),
|
1503 |
|
|
.pipe_rx1_chanisaligned_i (PIPERX1CHANISALIGNEDGT ),
|
1504 |
|
|
.pipe_rx1_status_i (PIPERX1STATUSGT ),
|
1505 |
|
|
.pipe_rx1_phy_status_i (PIPERX1PHYSTATUSGT ),
|
1506 |
|
|
.pipe_rx1_elec_idle_o (PIPERX1ELECIDLE ),
|
1507 |
|
|
.pipe_rx1_polarity_o (PIPERX1POLARITYGT ),
|
1508 |
|
|
.pipe_tx1_compliance_o (PIPETX1COMPLIANCEGT ),
|
1509 |
|
|
.pipe_tx1_char_is_k_o (PIPETX1CHARISKGT ),
|
1510 |
|
|
.pipe_tx1_data_o (PIPETX1DATAGT ),
|
1511 |
|
|
.pipe_tx1_elec_idle_o (PIPETX1ELECIDLEGT ),
|
1512 |
|
|
.pipe_tx1_powerdown_o (PIPETX1POWERDOWNGT ),
|
1513 |
|
|
|
1514 |
|
|
// Pipe Per-Lane Signals - Lane 2
|
1515 |
|
|
.pipe_rx2_char_is_k_o (PIPERX2CHARISK ),
|
1516 |
|
|
.pipe_rx2_data_o (PIPERX2DATA ),
|
1517 |
|
|
.pipe_rx2_valid_o (PIPERX2VALID ),
|
1518 |
|
|
.pipe_rx2_chanisaligned_o (PIPERX2CHANISALIGNED ),
|
1519 |
|
|
.pipe_rx2_status_o (PIPERX2STATUS ),
|
1520 |
|
|
.pipe_rx2_phy_status_o (PIPERX2PHYSTATUS ),
|
1521 |
|
|
.pipe_rx2_elec_idle_i (PIPERX2ELECIDLEGT ),
|
1522 |
|
|
.pipe_rx2_polarity_i (PIPERX2POLARITY ),
|
1523 |
|
|
.pipe_tx2_compliance_i (PIPETX2COMPLIANCE ),
|
1524 |
|
|
.pipe_tx2_char_is_k_i (PIPETX2CHARISK ),
|
1525 |
|
|
.pipe_tx2_data_i (PIPETX2DATA ),
|
1526 |
|
|
.pipe_tx2_elec_idle_i (PIPETX2ELECIDLE ),
|
1527 |
|
|
.pipe_tx2_powerdown_i (PIPETX2POWERDOWN ),
|
1528 |
|
|
|
1529 |
|
|
.pipe_rx2_char_is_k_i (PIPERX2CHARISKGT ),
|
1530 |
|
|
.pipe_rx2_data_i (PIPERX2DATAGT ),
|
1531 |
|
|
.pipe_rx2_valid_i (PIPERX2VALIDGT ),
|
1532 |
|
|
.pipe_rx2_chanisaligned_i (PIPERX2CHANISALIGNEDGT ),
|
1533 |
|
|
.pipe_rx2_status_i (PIPERX2STATUSGT ),
|
1534 |
|
|
.pipe_rx2_phy_status_i (PIPERX2PHYSTATUSGT ),
|
1535 |
|
|
.pipe_rx2_elec_idle_o (PIPERX2ELECIDLE ),
|
1536 |
|
|
.pipe_rx2_polarity_o (PIPERX2POLARITYGT ),
|
1537 |
|
|
.pipe_tx2_compliance_o (PIPETX2COMPLIANCEGT ),
|
1538 |
|
|
.pipe_tx2_char_is_k_o (PIPETX2CHARISKGT ),
|
1539 |
|
|
.pipe_tx2_data_o (PIPETX2DATAGT ),
|
1540 |
|
|
.pipe_tx2_elec_idle_o (PIPETX2ELECIDLEGT ),
|
1541 |
|
|
.pipe_tx2_powerdown_o (PIPETX2POWERDOWNGT ),
|
1542 |
|
|
|
1543 |
|
|
// Pipe Per-Lane Signals - Lane 3
|
1544 |
|
|
.pipe_rx3_char_is_k_o (PIPERX3CHARISK ),
|
1545 |
|
|
.pipe_rx3_data_o (PIPERX3DATA ),
|
1546 |
|
|
.pipe_rx3_valid_o (PIPERX3VALID ),
|
1547 |
|
|
.pipe_rx3_chanisaligned_o (PIPERX3CHANISALIGNED ),
|
1548 |
|
|
.pipe_rx3_status_o (PIPERX3STATUS ),
|
1549 |
|
|
.pipe_rx3_phy_status_o (PIPERX3PHYSTATUS ),
|
1550 |
|
|
.pipe_rx3_elec_idle_i (PIPERX3ELECIDLEGT ),
|
1551 |
|
|
.pipe_rx3_polarity_i (PIPERX3POLARITY ),
|
1552 |
|
|
.pipe_tx3_compliance_i (PIPETX3COMPLIANCE ),
|
1553 |
|
|
.pipe_tx3_char_is_k_i (PIPETX3CHARISK ),
|
1554 |
|
|
.pipe_tx3_data_i (PIPETX3DATA ),
|
1555 |
|
|
.pipe_tx3_elec_idle_i (PIPETX3ELECIDLE ),
|
1556 |
|
|
.pipe_tx3_powerdown_i (PIPETX3POWERDOWN ),
|
1557 |
|
|
|
1558 |
|
|
.pipe_rx3_char_is_k_i (PIPERX3CHARISKGT ),
|
1559 |
|
|
.pipe_rx3_data_i (PIPERX3DATAGT ),
|
1560 |
|
|
.pipe_rx3_valid_i (PIPERX3VALIDGT ),
|
1561 |
|
|
.pipe_rx3_chanisaligned_i (PIPERX3CHANISALIGNEDGT ),
|
1562 |
|
|
.pipe_rx3_status_i (PIPERX3STATUSGT ),
|
1563 |
|
|
.pipe_rx3_phy_status_i (PIPERX3PHYSTATUSGT ),
|
1564 |
|
|
.pipe_rx3_elec_idle_o (PIPERX3ELECIDLE ),
|
1565 |
|
|
.pipe_rx3_polarity_o (PIPERX3POLARITYGT ),
|
1566 |
|
|
.pipe_tx3_compliance_o (PIPETX3COMPLIANCEGT ),
|
1567 |
|
|
.pipe_tx3_char_is_k_o (PIPETX3CHARISKGT ),
|
1568 |
|
|
.pipe_tx3_data_o (PIPETX3DATAGT ),
|
1569 |
|
|
.pipe_tx3_elec_idle_o (PIPETX3ELECIDLEGT ),
|
1570 |
|
|
.pipe_tx3_powerdown_o (PIPETX3POWERDOWNGT ),
|
1571 |
|
|
|
1572 |
|
|
// Pipe Per-Lane Signals - Lane 4
|
1573 |
|
|
.pipe_rx4_char_is_k_o (PIPERX4CHARISK ),
|
1574 |
|
|
.pipe_rx4_data_o (PIPERX4DATA ),
|
1575 |
|
|
.pipe_rx4_valid_o (PIPERX4VALID ),
|
1576 |
|
|
.pipe_rx4_chanisaligned_o (PIPERX4CHANISALIGNED ),
|
1577 |
|
|
.pipe_rx4_status_o (PIPERX4STATUS ),
|
1578 |
|
|
.pipe_rx4_phy_status_o (PIPERX4PHYSTATUS ),
|
1579 |
|
|
.pipe_rx4_elec_idle_i (PIPERX4ELECIDLEGT ),
|
1580 |
|
|
.pipe_rx4_polarity_i (PIPERX4POLARITY ),
|
1581 |
|
|
.pipe_tx4_compliance_i (PIPETX4COMPLIANCE ),
|
1582 |
|
|
.pipe_tx4_char_is_k_i (PIPETX4CHARISK ),
|
1583 |
|
|
.pipe_tx4_data_i (PIPETX4DATA ),
|
1584 |
|
|
.pipe_tx4_elec_idle_i (PIPETX4ELECIDLE ),
|
1585 |
|
|
.pipe_tx4_powerdown_i (PIPETX4POWERDOWN ),
|
1586 |
|
|
|
1587 |
|
|
.pipe_rx4_char_is_k_i (PIPERX4CHARISKGT ),
|
1588 |
|
|
.pipe_rx4_data_i (PIPERX4DATAGT ),
|
1589 |
|
|
.pipe_rx4_valid_i (PIPERX4VALIDGT ),
|
1590 |
|
|
.pipe_rx4_chanisaligned_i (PIPERX4CHANISALIGNEDGT ),
|
1591 |
|
|
.pipe_rx4_status_i (PIPERX4STATUSGT ),
|
1592 |
|
|
.pipe_rx4_phy_status_i (PIPERX4PHYSTATUSGT ),
|
1593 |
|
|
.pipe_rx4_elec_idle_o (PIPERX4ELECIDLE ),
|
1594 |
|
|
.pipe_rx4_polarity_o (PIPERX4POLARITYGT ),
|
1595 |
|
|
.pipe_tx4_compliance_o (PIPETX4COMPLIANCEGT ),
|
1596 |
|
|
.pipe_tx4_char_is_k_o (PIPETX4CHARISKGT ),
|
1597 |
|
|
.pipe_tx4_data_o (PIPETX4DATAGT ),
|
1598 |
|
|
.pipe_tx4_elec_idle_o (PIPETX4ELECIDLEGT ),
|
1599 |
|
|
.pipe_tx4_powerdown_o (PIPETX4POWERDOWNGT ),
|
1600 |
|
|
|
1601 |
|
|
// Pipe Per-Lane Signals - Lane 5
|
1602 |
|
|
.pipe_rx5_char_is_k_o (PIPERX5CHARISK ),
|
1603 |
|
|
.pipe_rx5_data_o (PIPERX5DATA ),
|
1604 |
|
|
.pipe_rx5_valid_o (PIPERX5VALID ),
|
1605 |
|
|
.pipe_rx5_chanisaligned_o (PIPERX5CHANISALIGNED ),
|
1606 |
|
|
.pipe_rx5_status_o (PIPERX5STATUS ),
|
1607 |
|
|
.pipe_rx5_phy_status_o (PIPERX5PHYSTATUS ),
|
1608 |
|
|
.pipe_rx5_elec_idle_i (PIPERX5ELECIDLEGT ),
|
1609 |
|
|
.pipe_rx5_polarity_i (PIPERX5POLARITY ),
|
1610 |
|
|
.pipe_tx5_compliance_i (PIPETX5COMPLIANCE ),
|
1611 |
|
|
.pipe_tx5_char_is_k_i (PIPETX5CHARISK ),
|
1612 |
|
|
.pipe_tx5_data_i (PIPETX5DATA ),
|
1613 |
|
|
.pipe_tx5_elec_idle_i (PIPETX5ELECIDLE ),
|
1614 |
|
|
.pipe_tx5_powerdown_i (PIPETX5POWERDOWN ),
|
1615 |
|
|
|
1616 |
|
|
.pipe_rx5_char_is_k_i (PIPERX5CHARISKGT ),
|
1617 |
|
|
.pipe_rx5_data_i (PIPERX5DATAGT ),
|
1618 |
|
|
.pipe_rx5_valid_i (PIPERX5VALIDGT ),
|
1619 |
|
|
.pipe_rx5_chanisaligned_i (PIPERX5CHANISALIGNEDGT ),
|
1620 |
|
|
.pipe_rx5_status_i (PIPERX5STATUSGT ),
|
1621 |
|
|
.pipe_rx5_phy_status_i (PIPERX5PHYSTATUSGT ),
|
1622 |
|
|
.pipe_rx5_elec_idle_o (PIPERX5ELECIDLE ),
|
1623 |
|
|
.pipe_rx5_polarity_o (PIPERX5POLARITYGT ),
|
1624 |
|
|
.pipe_tx5_compliance_o (PIPETX5COMPLIANCEGT ),
|
1625 |
|
|
.pipe_tx5_char_is_k_o (PIPETX5CHARISKGT ),
|
1626 |
|
|
.pipe_tx5_data_o (PIPETX5DATAGT ),
|
1627 |
|
|
.pipe_tx5_elec_idle_o (PIPETX5ELECIDLEGT ),
|
1628 |
|
|
.pipe_tx5_powerdown_o (PIPETX5POWERDOWNGT ),
|
1629 |
|
|
|
1630 |
|
|
// Pipe Per-Lane Signals - Lane 6
|
1631 |
|
|
.pipe_rx6_char_is_k_o (PIPERX6CHARISK ),
|
1632 |
|
|
.pipe_rx6_data_o (PIPERX6DATA ),
|
1633 |
|
|
.pipe_rx6_valid_o (PIPERX6VALID ),
|
1634 |
|
|
.pipe_rx6_chanisaligned_o (PIPERX6CHANISALIGNED ),
|
1635 |
|
|
.pipe_rx6_status_o (PIPERX6STATUS ),
|
1636 |
|
|
.pipe_rx6_phy_status_o (PIPERX6PHYSTATUS ),
|
1637 |
|
|
.pipe_rx6_elec_idle_i (PIPERX6ELECIDLEGT ),
|
1638 |
|
|
.pipe_rx6_polarity_i (PIPERX6POLARITY ),
|
1639 |
|
|
.pipe_tx6_compliance_i (PIPETX6COMPLIANCE ),
|
1640 |
|
|
.pipe_tx6_char_is_k_i (PIPETX6CHARISK ),
|
1641 |
|
|
.pipe_tx6_data_i (PIPETX6DATA ),
|
1642 |
|
|
.pipe_tx6_elec_idle_i (PIPETX6ELECIDLE ),
|
1643 |
|
|
.pipe_tx6_powerdown_i (PIPETX6POWERDOWN ),
|
1644 |
|
|
|
1645 |
|
|
.pipe_rx6_char_is_k_i (PIPERX6CHARISKGT ),
|
1646 |
|
|
.pipe_rx6_data_i (PIPERX6DATAGT ),
|
1647 |
|
|
.pipe_rx6_valid_i (PIPERX6VALIDGT ),
|
1648 |
|
|
.pipe_rx6_chanisaligned_i (PIPERX6CHANISALIGNEDGT ),
|
1649 |
|
|
.pipe_rx6_status_i (PIPERX6STATUSGT ),
|
1650 |
|
|
.pipe_rx6_phy_status_i (PIPERX6PHYSTATUSGT ),
|
1651 |
|
|
.pipe_rx6_elec_idle_o (PIPERX6ELECIDLE ),
|
1652 |
|
|
.pipe_rx6_polarity_o (PIPERX6POLARITYGT ),
|
1653 |
|
|
.pipe_tx6_compliance_o (PIPETX6COMPLIANCEGT ),
|
1654 |
|
|
.pipe_tx6_char_is_k_o (PIPETX6CHARISKGT ),
|
1655 |
|
|
.pipe_tx6_data_o (PIPETX6DATAGT ),
|
1656 |
|
|
.pipe_tx6_elec_idle_o (PIPETX6ELECIDLEGT ),
|
1657 |
|
|
.pipe_tx6_powerdown_o (PIPETX6POWERDOWNGT ),
|
1658 |
|
|
|
1659 |
|
|
// Pipe Per-Lane Signals - Lane 7
|
1660 |
|
|
.pipe_rx7_char_is_k_o (PIPERX7CHARISK ),
|
1661 |
|
|
.pipe_rx7_data_o (PIPERX7DATA ),
|
1662 |
|
|
.pipe_rx7_valid_o (PIPERX7VALID ),
|
1663 |
|
|
.pipe_rx7_chanisaligned_o (PIPERX7CHANISALIGNED ),
|
1664 |
|
|
.pipe_rx7_status_o (PIPERX7STATUS ),
|
1665 |
|
|
.pipe_rx7_phy_status_o (PIPERX7PHYSTATUS ),
|
1666 |
|
|
.pipe_rx7_elec_idle_i (PIPERX7ELECIDLEGT ),
|
1667 |
|
|
.pipe_rx7_polarity_i (PIPERX7POLARITY ),
|
1668 |
|
|
.pipe_tx7_compliance_i (PIPETX7COMPLIANCE ),
|
1669 |
|
|
.pipe_tx7_char_is_k_i (PIPETX7CHARISK ),
|
1670 |
|
|
.pipe_tx7_data_i (PIPETX7DATA ),
|
1671 |
|
|
.pipe_tx7_elec_idle_i (PIPETX7ELECIDLE ),
|
1672 |
|
|
.pipe_tx7_powerdown_i (PIPETX7POWERDOWN ),
|
1673 |
|
|
|
1674 |
|
|
.pipe_rx7_char_is_k_i (PIPERX7CHARISKGT ),
|
1675 |
|
|
.pipe_rx7_data_i (PIPERX7DATAGT ),
|
1676 |
|
|
.pipe_rx7_valid_i (PIPERX7VALIDGT ),
|
1677 |
|
|
.pipe_rx7_chanisaligned_i (PIPERX7CHANISALIGNEDGT ),
|
1678 |
|
|
.pipe_rx7_status_i (PIPERX7STATUSGT ),
|
1679 |
|
|
.pipe_rx7_phy_status_i (PIPERX7PHYSTATUSGT ),
|
1680 |
|
|
.pipe_rx7_elec_idle_o (PIPERX7ELECIDLE ),
|
1681 |
|
|
.pipe_rx7_polarity_o (PIPERX7POLARITYGT ),
|
1682 |
|
|
.pipe_tx7_compliance_o (PIPETX7COMPLIANCEGT ),
|
1683 |
|
|
.pipe_tx7_char_is_k_o (PIPETX7CHARISKGT ),
|
1684 |
|
|
.pipe_tx7_data_o (PIPETX7DATAGT ),
|
1685 |
|
|
.pipe_tx7_elec_idle_o (PIPETX7ELECIDLEGT ),
|
1686 |
|
|
.pipe_tx7_powerdown_o (PIPETX7POWERDOWNGT ),
|
1687 |
|
|
|
1688 |
|
|
// Non PIPE signals
|
1689 |
|
|
.pl_ltssm_state (PLLTSSMSTATE ),
|
1690 |
|
|
.pipe_clk (PIPECLK ),
|
1691 |
|
|
.rst_n (PHYRDYN )
|
1692 |
|
|
);
|
1693 |
|
|
|
1694 |
|
|
//-------------------------------------------------------
|
1695 |
|
|
// Virtex6 GTX Module
|
1696 |
|
|
//-------------------------------------------------------
|
1697 |
|
|
|
1698 |
|
|
pcie_gtx_v6 #(
|
1699 |
|
|
|
1700 |
|
|
.NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
|
1701 |
|
|
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
|
1702 |
|
|
.REF_CLK_FREQ(REF_CLK_FREQ),
|
1703 |
|
|
.PL_FAST_TRAIN(PL_FAST_TRAIN)
|
1704 |
|
|
|
1705 |
|
|
)
|
1706 |
|
|
pcie_gt_i (
|
1707 |
|
|
|
1708 |
|
|
// Pipe Common Signals
|
1709 |
|
|
.pipe_tx_rcvr_det (PIPETXRCVRDETGT ),
|
1710 |
|
|
.pipe_tx_reset (1'b0 ),
|
1711 |
|
|
.pipe_tx_rate (PIPETXRATEGT ),
|
1712 |
|
|
.pipe_tx_deemph (PIPETXDEEMPHGT ),
|
1713 |
|
|
.pipe_tx_margin (PIPETXMARGINGT ),
|
1714 |
|
|
.pipe_tx_swing (1'b0),
|
1715 |
|
|
|
1716 |
|
|
// Pipe Per-Lane Signals - Lane 0
|
1717 |
|
|
.pipe_rx0_char_is_k (PIPERX0CHARISKGT ),
|
1718 |
|
|
.pipe_rx0_data (PIPERX0DATAGT ),
|
1719 |
|
|
.pipe_rx0_valid (PIPERX0VALIDGT ),
|
1720 |
|
|
.pipe_rx0_chanisaligned (PIPERX0CHANISALIGNEDGT ),
|
1721 |
|
|
.pipe_rx0_status (PIPERX0STATUSGT ),
|
1722 |
|
|
.pipe_rx0_phy_status (PIPERX0PHYSTATUSGT ),
|
1723 |
|
|
.pipe_rx0_elec_idle (PIPERX0ELECIDLEGT ),
|
1724 |
|
|
.pipe_rx0_polarity (PIPERX0POLARITYGT ),
|
1725 |
|
|
.pipe_tx0_compliance (PIPETX0COMPLIANCEGT ),
|
1726 |
|
|
.pipe_tx0_char_is_k (PIPETX0CHARISKGT ),
|
1727 |
|
|
.pipe_tx0_data (PIPETX0DATAGT ),
|
1728 |
|
|
.pipe_tx0_elec_idle (PIPETX0ELECIDLEGT ),
|
1729 |
|
|
.pipe_tx0_powerdown (PIPETX0POWERDOWNGT ),
|
1730 |
|
|
|
1731 |
|
|
// Pipe Per-Lane Signals - Lane 1
|
1732 |
|
|
.pipe_rx1_char_is_k (PIPERX1CHARISKGT ),
|
1733 |
|
|
.pipe_rx1_data (PIPERX1DATAGT ),
|
1734 |
|
|
.pipe_rx1_valid (PIPERX1VALIDGT ),
|
1735 |
|
|
.pipe_rx1_chanisaligned (PIPERX1CHANISALIGNEDGT ),
|
1736 |
|
|
.pipe_rx1_status (PIPERX1STATUSGT ),
|
1737 |
|
|
.pipe_rx1_phy_status (PIPERX1PHYSTATUSGT ),
|
1738 |
|
|
.pipe_rx1_elec_idle (PIPERX1ELECIDLEGT ),
|
1739 |
|
|
.pipe_rx1_polarity (PIPERX1POLARITYGT ),
|
1740 |
|
|
.pipe_tx1_compliance (PIPETX1COMPLIANCEGT ),
|
1741 |
|
|
.pipe_tx1_char_is_k (PIPETX1CHARISKGT ),
|
1742 |
|
|
.pipe_tx1_data (PIPETX1DATAGT ),
|
1743 |
|
|
.pipe_tx1_elec_idle (PIPETX1ELECIDLEGT ),
|
1744 |
|
|
.pipe_tx1_powerdown (PIPETX1POWERDOWNGT ),
|
1745 |
|
|
|
1746 |
|
|
// Pipe Per-Lane Signals - Lane 2
|
1747 |
|
|
.pipe_rx2_char_is_k (PIPERX2CHARISKGT ),
|
1748 |
|
|
.pipe_rx2_data (PIPERX2DATAGT ),
|
1749 |
|
|
.pipe_rx2_valid (PIPERX2VALIDGT ),
|
1750 |
|
|
.pipe_rx2_chanisaligned (PIPERX2CHANISALIGNEDGT ),
|
1751 |
|
|
.pipe_rx2_status (PIPERX2STATUSGT ),
|
1752 |
|
|
.pipe_rx2_phy_status (PIPERX2PHYSTATUSGT ),
|
1753 |
|
|
.pipe_rx2_elec_idle (PIPERX2ELECIDLEGT ),
|
1754 |
|
|
.pipe_rx2_polarity (PIPERX2POLARITYGT ),
|
1755 |
|
|
.pipe_tx2_compliance (PIPETX2COMPLIANCEGT ),
|
1756 |
|
|
.pipe_tx2_char_is_k (PIPETX2CHARISKGT ),
|
1757 |
|
|
.pipe_tx2_data (PIPETX2DATAGT ),
|
1758 |
|
|
.pipe_tx2_elec_idle (PIPETX2ELECIDLEGT ),
|
1759 |
|
|
.pipe_tx2_powerdown (PIPETX2POWERDOWNGT ),
|
1760 |
|
|
|
1761 |
|
|
// Pipe Per-Lane Signals - Lane 3
|
1762 |
|
|
.pipe_rx3_char_is_k (PIPERX3CHARISKGT ),
|
1763 |
|
|
.pipe_rx3_data (PIPERX3DATAGT ),
|
1764 |
|
|
.pipe_rx3_valid (PIPERX3VALIDGT ),
|
1765 |
|
|
.pipe_rx3_chanisaligned (PIPERX3CHANISALIGNEDGT ),
|
1766 |
|
|
.pipe_rx3_status (PIPERX3STATUSGT ),
|
1767 |
|
|
.pipe_rx3_phy_status (PIPERX3PHYSTATUSGT ),
|
1768 |
|
|
.pipe_rx3_elec_idle (PIPERX3ELECIDLEGT ),
|
1769 |
|
|
.pipe_rx3_polarity (PIPERX3POLARITYGT ),
|
1770 |
|
|
.pipe_tx3_compliance (PIPETX3COMPLIANCEGT ),
|
1771 |
|
|
.pipe_tx3_char_is_k (PIPETX3CHARISKGT ),
|
1772 |
|
|
.pipe_tx3_data (PIPETX3DATAGT ),
|
1773 |
|
|
.pipe_tx3_elec_idle (PIPETX3ELECIDLEGT ),
|
1774 |
|
|
.pipe_tx3_powerdown (PIPETX3POWERDOWNGT ),
|
1775 |
|
|
|
1776 |
|
|
// Pipe Per-Lane Signals - Lane 4
|
1777 |
|
|
.pipe_rx4_char_is_k (PIPERX4CHARISKGT ),
|
1778 |
|
|
.pipe_rx4_data (PIPERX4DATAGT ),
|
1779 |
|
|
.pipe_rx4_valid (PIPERX4VALIDGT ),
|
1780 |
|
|
.pipe_rx4_chanisaligned (PIPERX4CHANISALIGNEDGT ),
|
1781 |
|
|
.pipe_rx4_status (PIPERX4STATUSGT ),
|
1782 |
|
|
.pipe_rx4_phy_status (PIPERX4PHYSTATUSGT ),
|
1783 |
|
|
.pipe_rx4_elec_idle (PIPERX4ELECIDLEGT ),
|
1784 |
|
|
.pipe_rx4_polarity (PIPERX4POLARITYGT ),
|
1785 |
|
|
.pipe_tx4_compliance (PIPETX4COMPLIANCEGT ),
|
1786 |
|
|
.pipe_tx4_char_is_k (PIPETX4CHARISKGT ),
|
1787 |
|
|
.pipe_tx4_data (PIPETX4DATAGT ),
|
1788 |
|
|
.pipe_tx4_elec_idle (PIPETX4ELECIDLEGT ),
|
1789 |
|
|
.pipe_tx4_powerdown (PIPETX4POWERDOWNGT ),
|
1790 |
|
|
|
1791 |
|
|
// Pipe Per-Lane Signals - Lane 5
|
1792 |
|
|
.pipe_rx5_char_is_k (PIPERX5CHARISKGT ),
|
1793 |
|
|
.pipe_rx5_data (PIPERX5DATAGT ),
|
1794 |
|
|
.pipe_rx5_valid (PIPERX5VALIDGT ),
|
1795 |
|
|
.pipe_rx5_chanisaligned (PIPERX5CHANISALIGNEDGT ),
|
1796 |
|
|
.pipe_rx5_status (PIPERX5STATUSGT ),
|
1797 |
|
|
.pipe_rx5_phy_status (PIPERX5PHYSTATUSGT ),
|
1798 |
|
|
.pipe_rx5_elec_idle (PIPERX5ELECIDLEGT ),
|
1799 |
|
|
.pipe_rx5_polarity (PIPERX5POLARITYGT ),
|
1800 |
|
|
.pipe_tx5_compliance (PIPETX5COMPLIANCEGT ),
|
1801 |
|
|
.pipe_tx5_char_is_k (PIPETX5CHARISKGT ),
|
1802 |
|
|
.pipe_tx5_data (PIPETX5DATAGT ),
|
1803 |
|
|
.pipe_tx5_elec_idle (PIPETX5ELECIDLEGT ),
|
1804 |
|
|
.pipe_tx5_powerdown (PIPETX5POWERDOWNGT ),
|
1805 |
|
|
|
1806 |
|
|
// Pipe Per-Lane Signals - Lane 6
|
1807 |
|
|
.pipe_rx6_char_is_k (PIPERX6CHARISKGT ),
|
1808 |
|
|
.pipe_rx6_data (PIPERX6DATAGT ),
|
1809 |
|
|
.pipe_rx6_valid (PIPERX6VALIDGT ),
|
1810 |
|
|
.pipe_rx6_chanisaligned (PIPERX6CHANISALIGNEDGT ),
|
1811 |
|
|
.pipe_rx6_status (PIPERX6STATUSGT ),
|
1812 |
|
|
.pipe_rx6_phy_status (PIPERX6PHYSTATUSGT ),
|
1813 |
|
|
.pipe_rx6_elec_idle (PIPERX6ELECIDLEGT ),
|
1814 |
|
|
.pipe_rx6_polarity (PIPERX6POLARITYGT ),
|
1815 |
|
|
.pipe_tx6_compliance (PIPETX6COMPLIANCEGT ),
|
1816 |
|
|
.pipe_tx6_char_is_k (PIPETX6CHARISKGT ),
|
1817 |
|
|
.pipe_tx6_data (PIPETX6DATAGT ),
|
1818 |
|
|
.pipe_tx6_elec_idle (PIPETX6ELECIDLEGT ),
|
1819 |
|
|
.pipe_tx6_powerdown (PIPETX6POWERDOWNGT ),
|
1820 |
|
|
|
1821 |
|
|
// Pipe Per-Lane Signals - Lane 7
|
1822 |
|
|
.pipe_rx7_char_is_k (PIPERX7CHARISKGT ),
|
1823 |
|
|
.pipe_rx7_data (PIPERX7DATAGT ),
|
1824 |
|
|
.pipe_rx7_valid (PIPERX7VALIDGT ),
|
1825 |
|
|
.pipe_rx7_chanisaligned (PIPERX7CHANISALIGNEDGT ),
|
1826 |
|
|
.pipe_rx7_status (PIPERX7STATUSGT ),
|
1827 |
|
|
.pipe_rx7_phy_status (PIPERX7PHYSTATUSGT ),
|
1828 |
|
|
.pipe_rx7_elec_idle (PIPERX7ELECIDLEGT ),
|
1829 |
|
|
.pipe_rx7_polarity (PIPERX7POLARITYGT ),
|
1830 |
|
|
.pipe_tx7_compliance (PIPETX7COMPLIANCEGT ),
|
1831 |
|
|
.pipe_tx7_char_is_k (PIPETX7CHARISKGT ),
|
1832 |
|
|
.pipe_tx7_data (PIPETX7DATAGT ),
|
1833 |
|
|
.pipe_tx7_elec_idle (PIPETX7ELECIDLEGT ),
|
1834 |
|
|
.pipe_tx7_powerdown (PIPETX7POWERDOWNGT ),
|
1835 |
|
|
|
1836 |
|
|
// PCI Express Signals
|
1837 |
|
|
.pci_exp_txn (PCIEXPTXN ),
|
1838 |
|
|
.pci_exp_txp (PCIEXPTXP ),
|
1839 |
|
|
.pci_exp_rxn (PCIEXPRXN ),
|
1840 |
|
|
.pci_exp_rxp (PCIEXPRXP ),
|
1841 |
|
|
|
1842 |
|
|
// Non PIPE Signals
|
1843 |
|
|
.sys_clk (SYSCLK ),
|
1844 |
|
|
.sys_rst_n (FUNDRSTN ),
|
1845 |
|
|
.pipe_clk (PIPECLK ),
|
1846 |
|
|
.drp_clk (DRPCLK ),
|
1847 |
|
|
.clock_locked (CLOCKLOCKED ),
|
1848 |
|
|
.pl_ltssm_state (PLLTSSMSTATE ),
|
1849 |
|
|
|
1850 |
|
|
.gt_pll_lock (GTPLLLOCK ),
|
1851 |
|
|
.phy_rdy_n (PHYRDYN ),
|
1852 |
|
|
.TxOutClk (TxOutClk )
|
1853 |
|
|
|
1854 |
|
|
);
|
1855 |
|
|
|
1856 |
|
|
//-------------------------------------------------------
|
1857 |
|
|
// PCI Express BRAM Module
|
1858 |
|
|
//-------------------------------------------------------
|
1859 |
|
|
|
1860 |
|
|
pcie_bram_top_v6 #(
|
1861 |
|
|
|
1862 |
|
|
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),
|
1863 |
|
|
|
1864 |
|
|
.VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),
|
1865 |
|
|
.TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
|
1866 |
|
|
.TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
|
1867 |
|
|
.TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),
|
1868 |
|
|
|
1869 |
|
|
.VC0_RX_LIMIT(VC0_RX_RAM_LIMIT),
|
1870 |
|
|
.TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
|
1871 |
|
|
.TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
|
1872 |
|
|
.TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY)
|
1873 |
|
|
|
1874 |
|
|
)
|
1875 |
|
|
pcie_bram_i (
|
1876 |
|
|
|
1877 |
|
|
.user_clk_i( USERCLK ),
|
1878 |
|
|
.reset_i( PHYRDYN ),
|
1879 |
|
|
|
1880 |
|
|
.mim_tx_waddr( MIMTXWADDR ),
|
1881 |
|
|
.mim_tx_wen( MIMTXWEN ),
|
1882 |
|
|
.mim_tx_ren( MIMTXREN ),
|
1883 |
|
|
.mim_tx_rce( MIMTXRCE ),
|
1884 |
|
|
.mim_tx_wdata( {3'b000, MIMTXWDATA} ),
|
1885 |
|
|
.mim_tx_raddr( MIMTXRADDR ),
|
1886 |
|
|
.mim_tx_rdata( MIMTXRDATA ),
|
1887 |
|
|
|
1888 |
|
|
.mim_rx_waddr( MIMRXWADDR ),
|
1889 |
|
|
.mim_rx_wen( MIMRXWEN ),
|
1890 |
|
|
.mim_rx_ren( MIMRXREN ),
|
1891 |
|
|
.mim_rx_rce( MIMRXRCE ),
|
1892 |
|
|
.mim_rx_wdata( {4'b0000, MIMRXWDATA} ),
|
1893 |
|
|
.mim_rx_raddr( MIMRXRADDR ),
|
1894 |
|
|
.mim_rx_rdata( MIMRXRDATA )
|
1895 |
|
|
|
1896 |
|
|
);
|
1897 |
|
|
|
1898 |
|
|
|
1899 |
|
|
//-------------------------------------------------------
|
1900 |
|
|
// PCI Express Port Workarounds
|
1901 |
|
|
//-------------------------------------------------------
|
1902 |
|
|
|
1903 |
|
|
pcie_upconfig_fix_3451_v6 # (
|
1904 |
|
|
|
1905 |
|
|
.UPSTREAM_FACING ( UPSTREAM_FACING ),
|
1906 |
|
|
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
|
1907 |
|
|
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH )
|
1908 |
|
|
|
1909 |
|
|
)
|
1910 |
|
|
pcie_upconfig_fix_3451_v6_i (
|
1911 |
|
|
|
1912 |
|
|
.pipe_clk(PIPECLK),
|
1913 |
|
|
.pl_phy_lnkup_n(PLPHYLNKUPN),
|
1914 |
|
|
|
1915 |
|
|
.pl_ltssm_state(PLLTSSMSTATE),
|
1916 |
|
|
.pl_sel_lnk_rate(PLSELLNKRATE),
|
1917 |
|
|
.pl_directed_link_change(PLDIRECTEDLINKCHANGE),
|
1918 |
|
|
|
1919 |
|
|
.cfg_link_status_negotiated_width(CFGLINKSTATUSNEGOTIATEDWIDTH),
|
1920 |
|
|
.pipe_rx0_data(PIPERX0DATAGT[15:0]),
|
1921 |
|
|
.pipe_rx0_char_isk(PIPERX0CHARISKGT[1:0]),
|
1922 |
|
|
|
1923 |
|
|
.filter_pipe(filter_pipe_upconfig_fix_3451)
|
1924 |
|
|
|
1925 |
|
|
);
|
1926 |
|
|
|
1927 |
|
|
endmodule
|