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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_clocking_v6.vhd
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-- Version : 1.7
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---- Description: Clocking module for Virtex6 PCIe Block
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----
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----
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_clocking_v6 is
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generic (
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IS_ENDPOINT : boolean := TRUE;
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CAP_LINK_WIDTH : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
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CAP_LINK_SPEED : integer := 1; -- 1 - Gen1 , 2 - Gen2
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
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USER_CLK_FREQ : integer := 3 -- 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
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);
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port (
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sys_clk : in std_logic;
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gt_pll_lock : in std_logic;
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sel_lnk_rate : in std_logic;
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sel_lnk_width : in std_logic_vector(1 downto 0);
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sys_clk_bufg : out std_logic;
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pipe_clk : out std_logic;
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user_clk : out std_logic;
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block_clk : out std_logic;
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drp_clk : out std_logic;
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clock_locked : out std_logic
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);
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end pcie_clocking_v6;
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architecture v6_pcie of pcie_clocking_v6 is
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-- MMCM Configuration
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function clkin_prd(
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constant REF_CLK_FREQ : integer)
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return real is
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variable CLKIN_PERD : real := 0.0;
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begin -- clkin_prd
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if (REF_CLK_FREQ = 0) then
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CLKIN_PERD := 10.0;
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elsif (REF_CLK_FREQ = 1) then
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CLKIN_PERD := 8.0;
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elsif (REF_CLK_FREQ = 2) then
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CLKIN_PERD := 4.0;
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else
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CLKIN_PERD := 0.0;
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end if;
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return CLKIN_PERD;
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end clkin_prd;
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constant mmcm_clockin_period : real := clkin_prd(REF_CLK_FREQ);
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function clkfb_mul(
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constant REF_CLK_FREQ : integer)
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return real is
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variable CLKFB_MULT : real := 0.0;
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begin -- clkfb_mul
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if (REF_CLK_FREQ = 0) then
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CLKFB_MULT := 10.0;
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elsif (REF_CLK_FREQ = 1) then
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CLKFB_MULT := 8.0;
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elsif (REF_CLK_FREQ = 2) then
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CLKFB_MULT := 8.0;
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else
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CLKFB_MULT := 0.0;
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end if;
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return CLKFB_MULT;
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end clkfb_mul;
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constant mmcm_clockfb_mult : real := clkfb_mul(REF_CLK_FREQ);
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function divclk_div(
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constant REF_CLK_FREQ : integer)
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return integer is
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variable DIVCLK_DIVIDE : integer := 0;
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begin -- divclk_div
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if (REF_CLK_FREQ = 0) then
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DIVCLK_DIVIDE := 1;
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elsif (REF_CLK_FREQ = 1) then
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DIVCLK_DIVIDE := 1;
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elsif (REF_CLK_FREQ = 2) then
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DIVCLK_DIVIDE := 2;
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else
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DIVCLK_DIVIDE := 0;
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end if;
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return DIVCLK_DIVIDE;
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end divclk_div;
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constant mmcm_divclk_divide : integer := divclk_div(REF_CLK_FREQ);
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constant mmcm_clock0_div : real := 4.0;
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constant mmcm_clock1_div : integer := 8;
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constant TCQ : integer := 1;
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function clk2_div(
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constant LNK_WDT : integer;
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constant LNK_SPD : integer;
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constant USR_CLK_FREQ : integer)
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return integer is
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variable CLK_DIV : integer := 1;
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begin -- clk2_div
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if ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 0)) then
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CLK_DIV := 32;
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elsif ((LNK_WDT = 1) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
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CLK_DIV := 16;
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elsif ((LNK_WDT = 1) and (LNK_SPD = 2) and (USR_CLK_FREQ = 1)) then
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CLK_DIV := 16;
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elsif ((LNK_WDT = 2) and (LNK_SPD = 1) and (USR_CLK_FREQ = 1)) then
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CLK_DIV := 16;
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else
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CLK_DIV := 2;
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end if;
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return CLK_DIV;
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end clk2_div;
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constant mmcm_clock2_div : integer := clk2_div(CAP_LINK_WIDTH, CAP_LINK_SPEED, USER_CLK_FREQ);
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constant mmcm_clock3_div : integer := 2;
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signal mmcm_locked : std_logic;
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signal mmcm_clkfbin : std_logic;
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signal mmcm_clkfbout : std_logic;
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signal mmcm_reset : std_logic;
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signal clk_500 : std_logic;
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signal clk_250 : std_logic;
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signal clk_125 : std_logic;
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signal user_clk_prebuf : std_logic;
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signal sel_lnk_rate_d : std_logic;
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signal reg_clock_locked : std_logic_vector(1 downto 0) := "11";
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-- Declare intermediate signals for referenced outputs
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signal sys_clk_bufg_v6pcie3 : std_logic;
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signal pipe_clk_v6pcie : std_logic;
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signal user_clk_v6pcie4 : std_logic;
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signal block_clk_v6pcie0 : std_logic;
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signal clock_locked_v6pcie : std_logic;
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signal drp_clk_v6pcie1 : std_logic;
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signal clock_locked_int : std_logic;
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begin
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-- Drive referenced outputs
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sys_clk_bufg <= sys_clk_bufg_v6pcie3;
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pipe_clk <= pipe_clk_v6pcie;
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user_clk <= user_clk_v6pcie4;
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block_clk <= block_clk_v6pcie0;
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drp_clk <= drp_clk_v6pcie1;
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clock_locked <= clock_locked_v6pcie;
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clock_locked_v6pcie <= clock_locked_int and mmcm_locked;
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clock_locked_int <= not(reg_clock_locked(1));
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-- MMCM Reset
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mmcm_reset <= '0';
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-- PIPE Clock BUFG.
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GEN1_LINK : if (CAP_LINK_SPEED = 1) generate
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pipe_clk_bufg : BUFG port map (O => pipe_clk_v6pcie, I => clk_125 );
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end generate;
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GEN2_LINK : if (CAP_LINK_SPEED = 2) generate
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sel_lnk_rate_delay : SRL16E generic map ( INIT => X"0000" )
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port map (
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Q => sel_lnk_rate_d,
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D => sel_lnk_rate,
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CLK => pipe_clk_v6pcie,
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CE => clock_locked_v6pcie,
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A3 => '1',
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A2 => '1',
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A1 => '1',
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A0 => '1'
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);
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pipe_clk_bufgmux : BUFGMUX port map (
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O => pipe_clk_v6pcie,
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I0 => clk_125,
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I1 => clk_250,
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S => sel_lnk_rate_d
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);
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end generate;
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ILLEGAL_LINK_SPEED : if ((CAP_LINK_SPEED /= 1) and (CAP_LINK_SPEED /= 2)) generate
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--$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
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--$finish;
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end generate;
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-- User Clock BUFG.
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x1_GEN1_31_25 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 0)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
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end generate;
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x1_GEN1_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
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end generate;
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x1_GEN1_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
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end generate;
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x1_GEN1_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
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end generate;
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x1_GEN2_62_50 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 1)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
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end generate;
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x1_GEN2_125_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
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end generate;
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x1_GEN2_250_00 : if ((CAP_LINK_WIDTH = 1) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
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end generate;
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x2_GEN1_62_50 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 1)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => user_clk_prebuf );
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end generate;
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x2_GEN1_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
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end generate;
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x2_GEN1_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
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end generate;
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x2_GEN2_125_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 2)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
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end generate;
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x2_GEN2_250_00 : if ((CAP_LINK_WIDTH = 2) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
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end generate;
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x4_GEN1_125_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 2)) generate
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user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_125 );
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end generate;
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333 |
|
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x4_GEN1_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
|
334 |
|
|
|
335 |
|
|
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
|
336 |
|
|
|
337 |
|
|
end generate;
|
338 |
|
|
|
339 |
|
|
x4_GEN2_250_00 : if ((CAP_LINK_WIDTH = 4) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 3)) generate
|
340 |
|
|
|
341 |
|
|
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
|
342 |
|
|
|
343 |
|
|
end generate;
|
344 |
|
|
|
345 |
|
|
x8_GEN1_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 1) and (USER_CLK_FREQ = 3)) generate
|
346 |
|
|
|
347 |
|
|
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
|
348 |
|
|
|
349 |
|
|
end generate;
|
350 |
|
|
|
351 |
|
|
x8_GEN2_250_00 : if ((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4)) generate
|
352 |
|
|
|
353 |
|
|
user_clk_bufg : BUFG port map ( O => user_clk_v6pcie4, I => clk_250 );
|
354 |
|
|
|
355 |
|
|
block_clk_bufg : BUFG port map ( O => block_clk_v6pcie0, I => clk_500 );
|
356 |
|
|
|
357 |
|
|
end generate;
|
358 |
|
|
|
359 |
|
|
-- v6pcie42 : if (not((CAP_LINK_WIDTH = 8) and (CAP_LINK_SPEED = 2) and (USER_CLK_FREQ = 4))) generate
|
360 |
|
|
|
361 |
|
|
--$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
|
362 |
|
|
--$finish;
|
363 |
|
|
|
364 |
|
|
-- end generate;
|
365 |
|
|
|
366 |
|
|
-- DRP clk
|
367 |
|
|
drp_clk_bufg_i : BUFG port map ( O => drp_clk_v6pcie1, I => clk_125 );
|
368 |
|
|
|
369 |
|
|
-- Feedback BUFG. Required for Temp Compensation
|
370 |
|
|
clkfbin_bufg_i : BUFG port map ( O => mmcm_clkfbin, I => mmcm_clkfbout );
|
371 |
|
|
|
372 |
|
|
-- sys_clk BUFG.
|
373 |
|
|
sys_clk_bufg_i : BUFG port map ( O => sys_clk_bufg_v6pcie3, I => sys_clk );
|
374 |
|
|
|
375 |
|
|
mmcm_adv_i : MMCM_ADV
|
376 |
|
|
generic map (
|
377 |
|
|
-- 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
|
378 |
|
|
CLKFBOUT_MULT_F => mmcm_clockfb_mult,
|
379 |
|
|
DIVCLK_DIVIDE => mmcm_divclk_divide,
|
380 |
|
|
CLKFBOUT_PHASE => 0.0,
|
381 |
|
|
-- 10 for 100 MHz, 4 for 250 MHz
|
382 |
|
|
CLKIN1_PERIOD => mmcm_clockin_period,
|
383 |
|
|
CLKIN2_PERIOD => mmcm_clockin_period,
|
384 |
|
|
-- 500 MHz / mmcm_clockx_div
|
385 |
|
|
CLKOUT0_DIVIDE_F => mmcm_clock0_div,
|
386 |
|
|
CLKOUT0_PHASE => 0.0,
|
387 |
|
|
CLKOUT1_DIVIDE => mmcm_clock1_div,
|
388 |
|
|
CLKOUT1_PHASE => 0.0,
|
389 |
|
|
CLKOUT2_DIVIDE => mmcm_clock2_div,
|
390 |
|
|
CLKOUT2_PHASE => 0.0,
|
391 |
|
|
CLKOUT3_DIVIDE => mmcm_clock3_div,
|
392 |
|
|
CLKOUT3_PHASE => 0.0
|
393 |
|
|
)
|
394 |
|
|
port map (
|
395 |
|
|
clkfbout => mmcm_clkfbout,
|
396 |
|
|
clkout0 => clk_250, -- 250 MHz for pipe_clk
|
397 |
|
|
clkout1 => clk_125, -- 125 MHz for pipe_clk
|
398 |
|
|
clkout2 => user_clk_prebuf, -- user clk
|
399 |
|
|
clkout3 => clk_500,
|
400 |
|
|
clkout4 => open,
|
401 |
|
|
clkout5 => open,
|
402 |
|
|
clkout6 => open,
|
403 |
|
|
do => open,
|
404 |
|
|
drdy => open,
|
405 |
|
|
clkfboutb => open,
|
406 |
|
|
clkfbstopped => open,
|
407 |
|
|
clkinstopped => open,
|
408 |
|
|
clkout0b => open,
|
409 |
|
|
clkout1b => open,
|
410 |
|
|
clkout2b => open,
|
411 |
|
|
clkout3b => open,
|
412 |
|
|
psdone => open,
|
413 |
|
|
locked => mmcm_locked,
|
414 |
|
|
clkfbin => mmcm_clkfbin,
|
415 |
|
|
clkin1 => sys_clk,
|
416 |
|
|
clkin2 => '0',
|
417 |
|
|
clkinsel => '1',
|
418 |
|
|
daddr => "0000000",
|
419 |
|
|
dclk => '0',
|
420 |
|
|
den => '0',
|
421 |
|
|
di => "0000000000000000",
|
422 |
|
|
dwe => '0',
|
423 |
|
|
psen => '0',
|
424 |
|
|
psincdec => '0',
|
425 |
|
|
pwrdwn => '0',
|
426 |
|
|
psclk => '0',
|
427 |
|
|
rst => mmcm_reset
|
428 |
|
|
);
|
429 |
|
|
|
430 |
|
|
-- Synchronize MMCM locked output
|
431 |
|
|
process (pipe_clk_v6pcie, gt_pll_lock)
|
432 |
|
|
begin
|
433 |
|
|
|
434 |
|
|
if ((not(gt_pll_lock)) = '1') then
|
435 |
|
|
|
436 |
|
|
reg_clock_locked <= "11" after (TCQ)*1 ps;
|
437 |
|
|
|
438 |
|
|
elsif (pipe_clk_v6pcie'event and pipe_clk_v6pcie = '1') then
|
439 |
|
|
|
440 |
|
|
reg_clock_locked <= (reg_clock_locked(0) & '0') after (TCQ)*1 ps;
|
441 |
|
|
|
442 |
|
|
end if;
|
443 |
|
|
end process;
|
444 |
|
|
|
445 |
|
|
end v6_pcie;
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
|