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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_pipe_v6.v
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// Version : 1.7
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//-- Description: PIPE module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_pipe_v6 #
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(
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parameter NO_OF_LANES = 8,
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
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parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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)
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(
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// Pipe Per-Link Signals
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input wire pipe_tx_rcvr_det_i ,
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input wire pipe_tx_reset_i ,
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input wire pipe_tx_rate_i ,
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input wire pipe_tx_deemph_i ,
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input wire [2:0] pipe_tx_margin_i ,
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input wire pipe_tx_swing_i ,
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output wire pipe_tx_rcvr_det_o ,
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output wire pipe_tx_reset_o ,
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output wire pipe_tx_rate_o ,
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output wire pipe_tx_deemph_o ,
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output wire [2:0] pipe_tx_margin_o ,
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output wire pipe_tx_swing_o ,
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// Pipe Per-Lane Signals - Lane 0
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output wire [ 1:0] pipe_rx0_char_is_k_o ,
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output wire [15:0] pipe_rx0_data_o ,
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output wire pipe_rx0_valid_o ,
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output wire pipe_rx0_chanisaligned_o ,
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output wire [ 2:0] pipe_rx0_status_o ,
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| 89 |
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output wire pipe_rx0_phy_status_o ,
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| 90 |
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output wire pipe_rx0_elec_idle_o ,
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| 91 |
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input wire pipe_rx0_polarity_i ,
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| 92 |
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input wire pipe_tx0_compliance_i ,
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| 93 |
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input wire [ 1:0] pipe_tx0_char_is_k_i ,
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| 94 |
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input wire [15:0] pipe_tx0_data_i ,
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| 95 |
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input wire pipe_tx0_elec_idle_i ,
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input wire [ 1:0] pipe_tx0_powerdown_i ,
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| 97 |
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input wire [ 1:0] pipe_rx0_char_is_k_i ,
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input wire [15:0] pipe_rx0_data_i ,
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| 100 |
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input wire pipe_rx0_valid_i ,
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| 101 |
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input wire pipe_rx0_chanisaligned_i ,
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| 102 |
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input wire [ 2:0] pipe_rx0_status_i ,
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| 103 |
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input wire pipe_rx0_phy_status_i ,
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| 104 |
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input wire pipe_rx0_elec_idle_i ,
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| 105 |
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output wire pipe_rx0_polarity_o ,
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| 106 |
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output wire pipe_tx0_compliance_o ,
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| 107 |
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output wire [ 1:0] pipe_tx0_char_is_k_o ,
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| 108 |
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output wire [15:0] pipe_tx0_data_o ,
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| 109 |
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output wire pipe_tx0_elec_idle_o ,
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| 110 |
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output wire [ 1:0] pipe_tx0_powerdown_o ,
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| 111 |
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// Pipe Per-Lane Signals - Lane 1
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output wire [ 1:0] pipe_rx1_char_is_k_o ,
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output wire [15:0] pipe_rx1_data_o ,
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| 115 |
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output wire pipe_rx1_valid_o ,
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output wire pipe_rx1_chanisaligned_o ,
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| 117 |
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output wire [ 2:0] pipe_rx1_status_o ,
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| 118 |
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output wire pipe_rx1_phy_status_o ,
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| 119 |
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output wire pipe_rx1_elec_idle_o ,
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| 120 |
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input wire pipe_rx1_polarity_i ,
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| 121 |
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input wire pipe_tx1_compliance_i ,
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| 122 |
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input wire [ 1:0] pipe_tx1_char_is_k_i ,
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| 123 |
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input wire [15:0] pipe_tx1_data_i ,
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| 124 |
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input wire pipe_tx1_elec_idle_i ,
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input wire [ 1:0] pipe_tx1_powerdown_i ,
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| 126 |
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| 127 |
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input wire [ 1:0] pipe_rx1_char_is_k_i ,
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| 128 |
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input wire [15:0] pipe_rx1_data_i ,
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| 129 |
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input wire pipe_rx1_valid_i ,
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| 130 |
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input wire pipe_rx1_chanisaligned_i ,
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| 131 |
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input wire [ 2:0] pipe_rx1_status_i ,
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input wire pipe_rx1_phy_status_i ,
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input wire pipe_rx1_elec_idle_i ,
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output wire pipe_rx1_polarity_o ,
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output wire pipe_tx1_compliance_o ,
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output wire [ 1:0] pipe_tx1_char_is_k_o ,
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| 137 |
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output wire [15:0] pipe_tx1_data_o ,
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output wire pipe_tx1_elec_idle_o ,
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| 139 |
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output wire [ 1:0] pipe_tx1_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 2
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output wire [ 1:0] pipe_rx2_char_is_k_o ,
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| 143 |
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output wire [15:0] pipe_rx2_data_o ,
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| 144 |
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output wire pipe_rx2_valid_o ,
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| 145 |
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output wire pipe_rx2_chanisaligned_o ,
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output wire [ 2:0] pipe_rx2_status_o ,
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| 147 |
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output wire pipe_rx2_phy_status_o ,
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| 148 |
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output wire pipe_rx2_elec_idle_o ,
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| 149 |
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input wire pipe_rx2_polarity_i ,
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| 150 |
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input wire pipe_tx2_compliance_i ,
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| 151 |
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input wire [ 1:0] pipe_tx2_char_is_k_i ,
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| 152 |
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input wire [15:0] pipe_tx2_data_i ,
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| 153 |
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input wire pipe_tx2_elec_idle_i ,
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| 154 |
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input wire [ 1:0] pipe_tx2_powerdown_i ,
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| 155 |
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| 156 |
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input wire [ 1:0] pipe_rx2_char_is_k_i ,
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| 157 |
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input wire [15:0] pipe_rx2_data_i ,
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| 158 |
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input wire pipe_rx2_valid_i ,
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| 159 |
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input wire pipe_rx2_chanisaligned_i ,
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| 160 |
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input wire [ 2:0] pipe_rx2_status_i ,
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| 161 |
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input wire pipe_rx2_phy_status_i ,
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| 162 |
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input wire pipe_rx2_elec_idle_i ,
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| 163 |
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output wire pipe_rx2_polarity_o ,
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| 164 |
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output wire pipe_tx2_compliance_o ,
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| 165 |
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output wire [ 1:0] pipe_tx2_char_is_k_o ,
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| 166 |
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output wire [15:0] pipe_tx2_data_o ,
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| 167 |
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output wire pipe_tx2_elec_idle_o ,
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| 168 |
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output wire [ 1:0] pipe_tx2_powerdown_o ,
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| 169 |
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| 170 |
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// Pipe Per-Lane Signals - Lane 3
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output wire [ 1:0] pipe_rx3_char_is_k_o ,
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| 172 |
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output wire [15:0] pipe_rx3_data_o ,
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| 173 |
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output wire pipe_rx3_valid_o ,
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| 174 |
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output wire pipe_rx3_chanisaligned_o ,
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| 175 |
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output wire [ 2:0] pipe_rx3_status_o ,
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| 176 |
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output wire pipe_rx3_phy_status_o ,
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| 177 |
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output wire pipe_rx3_elec_idle_o ,
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| 178 |
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input wire pipe_rx3_polarity_i ,
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| 179 |
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input wire pipe_tx3_compliance_i ,
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| 180 |
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input wire [ 1:0] pipe_tx3_char_is_k_i ,
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| 181 |
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input wire [15:0] pipe_tx3_data_i ,
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| 182 |
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input wire pipe_tx3_elec_idle_i ,
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| 183 |
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input wire [ 1:0] pipe_tx3_powerdown_i ,
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| 184 |
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| 185 |
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input wire [ 1:0] pipe_rx3_char_is_k_i ,
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| 186 |
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input wire [15:0] pipe_rx3_data_i ,
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| 187 |
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input wire pipe_rx3_valid_i ,
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| 188 |
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input wire pipe_rx3_chanisaligned_i ,
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| 189 |
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input wire [ 2:0] pipe_rx3_status_i ,
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| 190 |
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input wire pipe_rx3_phy_status_i ,
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| 191 |
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input wire pipe_rx3_elec_idle_i ,
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| 192 |
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output wire pipe_rx3_polarity_o ,
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| 193 |
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output wire pipe_tx3_compliance_o ,
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| 194 |
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output wire [ 1:0] pipe_tx3_char_is_k_o ,
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| 195 |
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output wire [15:0] pipe_tx3_data_o ,
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| 196 |
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output wire pipe_tx3_elec_idle_o ,
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| 197 |
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output wire [ 1:0] pipe_tx3_powerdown_o ,
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| 198 |
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| 199 |
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// Pipe Per-Lane Signals - Lane 4
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| 200 |
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output wire [ 1:0] pipe_rx4_char_is_k_o ,
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| 201 |
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output wire [15:0] pipe_rx4_data_o ,
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| 202 |
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output wire pipe_rx4_valid_o ,
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| 203 |
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output wire pipe_rx4_chanisaligned_o ,
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| 204 |
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output wire [ 2:0] pipe_rx4_status_o ,
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| 205 |
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output wire pipe_rx4_phy_status_o ,
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| 206 |
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output wire pipe_rx4_elec_idle_o ,
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| 207 |
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input wire pipe_rx4_polarity_i ,
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| 208 |
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input wire pipe_tx4_compliance_i ,
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| 209 |
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input wire [ 1:0] pipe_tx4_char_is_k_i ,
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| 210 |
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input wire [15:0] pipe_tx4_data_i ,
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| 211 |
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input wire pipe_tx4_elec_idle_i ,
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| 212 |
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input wire [ 1:0] pipe_tx4_powerdown_i ,
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| 213 |
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| 214 |
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input wire [ 1:0] pipe_rx4_char_is_k_i ,
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| 215 |
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input wire [15:0] pipe_rx4_data_i ,
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| 216 |
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input wire pipe_rx4_valid_i ,
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| 217 |
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input wire pipe_rx4_chanisaligned_i ,
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| 218 |
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input wire [ 2:0] pipe_rx4_status_i ,
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| 219 |
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input wire pipe_rx4_phy_status_i ,
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| 220 |
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input wire pipe_rx4_elec_idle_i ,
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| 221 |
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output wire pipe_rx4_polarity_o ,
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| 222 |
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output wire pipe_tx4_compliance_o ,
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| 223 |
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output wire [ 1:0] pipe_tx4_char_is_k_o ,
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| 224 |
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output wire [15:0] pipe_tx4_data_o ,
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| 225 |
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output wire pipe_tx4_elec_idle_o ,
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| 226 |
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output wire [ 1:0] pipe_tx4_powerdown_o ,
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| 227 |
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| 228 |
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// Pipe Per-Lane Signals - Lane 5
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| 229 |
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output wire [ 1:0] pipe_rx5_char_is_k_o ,
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| 230 |
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output wire [15:0] pipe_rx5_data_o ,
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| 231 |
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output wire pipe_rx5_valid_o ,
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| 232 |
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output wire pipe_rx5_chanisaligned_o ,
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| 233 |
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output wire [ 2:0] pipe_rx5_status_o ,
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| 234 |
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output wire pipe_rx5_phy_status_o ,
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| 235 |
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output wire pipe_rx5_elec_idle_o ,
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| 236 |
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input wire pipe_rx5_polarity_i ,
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| 237 |
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input wire pipe_tx5_compliance_i ,
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| 238 |
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input wire [ 1:0] pipe_tx5_char_is_k_i ,
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| 239 |
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input wire [15:0] pipe_tx5_data_i ,
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| 240 |
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input wire pipe_tx5_elec_idle_i ,
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| 241 |
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input wire [ 1:0] pipe_tx5_powerdown_i ,
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| 242 |
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| 243 |
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input wire [ 1:0] pipe_rx5_char_is_k_i ,
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| 244 |
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input wire [15:0] pipe_rx5_data_i ,
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| 245 |
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input wire pipe_rx5_valid_i ,
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| 246 |
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input wire pipe_rx5_chanisaligned_i ,
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| 247 |
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input wire [ 2:0] pipe_rx5_status_i ,
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| 248 |
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input wire pipe_rx5_phy_status_i ,
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| 249 |
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input wire pipe_rx5_elec_idle_i ,
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| 250 |
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output wire pipe_rx5_polarity_o ,
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| 251 |
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output wire pipe_tx5_compliance_o ,
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| 252 |
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output wire [ 1:0] pipe_tx5_char_is_k_o ,
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| 253 |
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output wire [15:0] pipe_tx5_data_o ,
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| 254 |
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output wire pipe_tx5_elec_idle_o ,
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| 255 |
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output wire [ 1:0] pipe_tx5_powerdown_o ,
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| 256 |
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| 257 |
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// Pipe Per-Lane Signals - Lane 6
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| 258 |
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output wire [ 1:0] pipe_rx6_char_is_k_o ,
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| 259 |
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output wire [15:0] pipe_rx6_data_o ,
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| 260 |
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output wire pipe_rx6_valid_o ,
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| 261 |
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output wire pipe_rx6_chanisaligned_o ,
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| 262 |
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output wire [ 2:0] pipe_rx6_status_o ,
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| 263 |
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output wire pipe_rx6_phy_status_o ,
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| 264 |
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output wire pipe_rx6_elec_idle_o ,
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| 265 |
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input wire pipe_rx6_polarity_i ,
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| 266 |
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input wire pipe_tx6_compliance_i ,
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| 267 |
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input wire [ 1:0] pipe_tx6_char_is_k_i ,
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| 268 |
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input wire [15:0] pipe_tx6_data_i ,
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| 269 |
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input wire pipe_tx6_elec_idle_i ,
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| 270 |
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input wire [ 1:0] pipe_tx6_powerdown_i ,
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| 271 |
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| 272 |
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input wire [ 1:0] pipe_rx6_char_is_k_i ,
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| 273 |
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input wire [15:0] pipe_rx6_data_i ,
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| 274 |
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input wire pipe_rx6_valid_i ,
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| 275 |
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input wire pipe_rx6_chanisaligned_i ,
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| 276 |
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input wire [ 2:0] pipe_rx6_status_i ,
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| 277 |
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input wire pipe_rx6_phy_status_i ,
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| 278 |
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input wire pipe_rx6_elec_idle_i ,
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| 279 |
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output wire pipe_rx6_polarity_o ,
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| 280 |
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output wire pipe_tx6_compliance_o ,
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| 281 |
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output wire [ 1:0] pipe_tx6_char_is_k_o ,
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| 282 |
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output wire [15:0] pipe_tx6_data_o ,
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| 283 |
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output wire pipe_tx6_elec_idle_o ,
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| 284 |
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output wire [ 1:0] pipe_tx6_powerdown_o ,
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| 285 |
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| 286 |
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// Pipe Per-Lane Signals - Lane 7
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| 287 |
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output wire [ 1:0] pipe_rx7_char_is_k_o ,
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| 288 |
|
|
output wire [15:0] pipe_rx7_data_o ,
|
| 289 |
|
|
output wire pipe_rx7_valid_o ,
|
| 290 |
|
|
output wire pipe_rx7_chanisaligned_o ,
|
| 291 |
|
|
output wire [ 2:0] pipe_rx7_status_o ,
|
| 292 |
|
|
output wire pipe_rx7_phy_status_o ,
|
| 293 |
|
|
output wire pipe_rx7_elec_idle_o ,
|
| 294 |
|
|
input wire pipe_rx7_polarity_i ,
|
| 295 |
|
|
input wire pipe_tx7_compliance_i ,
|
| 296 |
|
|
input wire [ 1:0] pipe_tx7_char_is_k_i ,
|
| 297 |
|
|
input wire [15:0] pipe_tx7_data_i ,
|
| 298 |
|
|
input wire pipe_tx7_elec_idle_i ,
|
| 299 |
|
|
input wire [ 1:0] pipe_tx7_powerdown_i ,
|
| 300 |
|
|
|
| 301 |
|
|
input wire [ 1:0] pipe_rx7_char_is_k_i ,
|
| 302 |
|
|
input wire [15:0] pipe_rx7_data_i ,
|
| 303 |
|
|
input wire pipe_rx7_valid_i ,
|
| 304 |
|
|
input wire pipe_rx7_chanisaligned_i ,
|
| 305 |
|
|
input wire [ 2:0] pipe_rx7_status_i ,
|
| 306 |
|
|
input wire pipe_rx7_phy_status_i ,
|
| 307 |
|
|
input wire pipe_rx7_elec_idle_i ,
|
| 308 |
|
|
output wire pipe_rx7_polarity_o ,
|
| 309 |
|
|
output wire pipe_tx7_compliance_o ,
|
| 310 |
|
|
output wire [ 1:0] pipe_tx7_char_is_k_o ,
|
| 311 |
|
|
output wire [15:0] pipe_tx7_data_o ,
|
| 312 |
|
|
output wire pipe_tx7_elec_idle_o ,
|
| 313 |
|
|
output wire [ 1:0] pipe_tx7_powerdown_o ,
|
| 314 |
|
|
|
| 315 |
|
|
// Non PIPE signals
|
| 316 |
|
|
input wire [ 5:0] pl_ltssm_state ,
|
| 317 |
|
|
input wire pipe_clk ,
|
| 318 |
|
|
input wire rst_n
|
| 319 |
|
|
);
|
| 320 |
|
|
|
| 321 |
|
|
//******************************************************************//
|
| 322 |
|
|
// Reality check. //
|
| 323 |
|
|
//******************************************************************//
|
| 324 |
|
|
|
| 325 |
|
|
parameter Tc2o = 1; // clock to out delay model
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
wire [ 1:0] pipe_rx0_char_is_k_q ;
|
| 329 |
|
|
wire [15:0] pipe_rx0_data_q ;
|
| 330 |
|
|
wire [ 1:0] pipe_rx1_char_is_k_q ;
|
| 331 |
|
|
wire [15:0] pipe_rx1_data_q ;
|
| 332 |
|
|
wire [ 1:0] pipe_rx2_char_is_k_q ;
|
| 333 |
|
|
wire [15:0] pipe_rx2_data_q ;
|
| 334 |
|
|
wire [ 1:0] pipe_rx3_char_is_k_q ;
|
| 335 |
|
|
wire [15:0] pipe_rx3_data_q ;
|
| 336 |
|
|
wire [ 1:0] pipe_rx4_char_is_k_q ;
|
| 337 |
|
|
wire [15:0] pipe_rx4_data_q ;
|
| 338 |
|
|
wire [ 1:0] pipe_rx5_char_is_k_q ;
|
| 339 |
|
|
wire [15:0] pipe_rx5_data_q ;
|
| 340 |
|
|
wire [ 1:0] pipe_rx6_char_is_k_q ;
|
| 341 |
|
|
wire [15:0] pipe_rx6_data_q ;
|
| 342 |
|
|
wire [ 1:0] pipe_rx7_char_is_k_q ;
|
| 343 |
|
|
wire [15:0] pipe_rx7_data_q ;
|
| 344 |
|
|
|
| 345 |
|
|
//synthesis translate_off
|
| 346 |
|
|
// initial begin
|
| 347 |
|
|
// $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
|
| 348 |
|
|
// end
|
| 349 |
|
|
//synthesis translate_on
|
| 350 |
|
|
|
| 351 |
|
|
generate
|
| 352 |
|
|
|
| 353 |
|
|
pcie_pipe_misc_v6 # (
|
| 354 |
|
|
|
| 355 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 356 |
|
|
|
| 357 |
|
|
)
|
| 358 |
|
|
pipe_misc_i (
|
| 359 |
|
|
|
| 360 |
|
|
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
|
| 361 |
|
|
.pipe_tx_reset_i(pipe_tx_reset_i),
|
| 362 |
|
|
.pipe_tx_rate_i(pipe_tx_rate_i),
|
| 363 |
|
|
.pipe_tx_deemph_i(pipe_tx_deemph_i),
|
| 364 |
|
|
.pipe_tx_margin_i(pipe_tx_margin_i),
|
| 365 |
|
|
.pipe_tx_swing_i(pipe_tx_swing_i),
|
| 366 |
|
|
|
| 367 |
|
|
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
|
| 368 |
|
|
.pipe_tx_reset_o(pipe_tx_reset_o),
|
| 369 |
|
|
.pipe_tx_rate_o(pipe_tx_rate_o),
|
| 370 |
|
|
.pipe_tx_deemph_o(pipe_tx_deemph_o),
|
| 371 |
|
|
.pipe_tx_margin_o(pipe_tx_margin_o),
|
| 372 |
|
|
.pipe_tx_swing_o(pipe_tx_swing_o) ,
|
| 373 |
|
|
|
| 374 |
|
|
.pipe_clk(pipe_clk),
|
| 375 |
|
|
.rst_n(rst_n)
|
| 376 |
|
|
);
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
pcie_pipe_lane_v6 # (
|
| 380 |
|
|
|
| 381 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 382 |
|
|
|
| 383 |
|
|
)
|
| 384 |
|
|
pipe_lane_0_i (
|
| 385 |
|
|
|
| 386 |
|
|
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),
|
| 387 |
|
|
.pipe_rx_data_o(pipe_rx0_data_q),
|
| 388 |
|
|
.pipe_rx_valid_o(pipe_rx0_valid_o),
|
| 389 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
|
| 390 |
|
|
.pipe_rx_status_o(pipe_rx0_status_o),
|
| 391 |
|
|
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
|
| 392 |
|
|
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
|
| 393 |
|
|
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
|
| 394 |
|
|
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
|
| 395 |
|
|
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
|
| 396 |
|
|
.pipe_tx_data_i(pipe_tx0_data_i),
|
| 397 |
|
|
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
|
| 398 |
|
|
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
|
| 399 |
|
|
|
| 400 |
|
|
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
|
| 401 |
|
|
.pipe_rx_data_i(pipe_rx0_data_i),
|
| 402 |
|
|
.pipe_rx_valid_i(pipe_rx0_valid_i),
|
| 403 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
|
| 404 |
|
|
.pipe_rx_status_i(pipe_rx0_status_i),
|
| 405 |
|
|
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
|
| 406 |
|
|
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
|
| 407 |
|
|
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
|
| 408 |
|
|
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
|
| 409 |
|
|
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
|
| 410 |
|
|
.pipe_tx_data_o(pipe_tx0_data_o),
|
| 411 |
|
|
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
|
| 412 |
|
|
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
|
| 413 |
|
|
|
| 414 |
|
|
.pipe_clk(pipe_clk),
|
| 415 |
|
|
.rst_n(rst_n)
|
| 416 |
|
|
|
| 417 |
|
|
);
|
| 418 |
|
|
|
| 419 |
|
|
if (NO_OF_LANES >= 2) begin
|
| 420 |
|
|
|
| 421 |
|
|
pcie_pipe_lane_v6 # (
|
| 422 |
|
|
|
| 423 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 424 |
|
|
|
| 425 |
|
|
)
|
| 426 |
|
|
pipe_lane_1_i (
|
| 427 |
|
|
|
| 428 |
|
|
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),
|
| 429 |
|
|
.pipe_rx_data_o(pipe_rx1_data_q),
|
| 430 |
|
|
.pipe_rx_valid_o(pipe_rx1_valid_o),
|
| 431 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
|
| 432 |
|
|
.pipe_rx_status_o(pipe_rx1_status_o),
|
| 433 |
|
|
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
|
| 434 |
|
|
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
|
| 435 |
|
|
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
|
| 436 |
|
|
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
|
| 437 |
|
|
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
|
| 438 |
|
|
.pipe_tx_data_i(pipe_tx1_data_i),
|
| 439 |
|
|
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
|
| 440 |
|
|
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
|
| 441 |
|
|
|
| 442 |
|
|
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
|
| 443 |
|
|
.pipe_rx_data_i(pipe_rx1_data_i),
|
| 444 |
|
|
.pipe_rx_valid_i(pipe_rx1_valid_i),
|
| 445 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
|
| 446 |
|
|
.pipe_rx_status_i(pipe_rx1_status_i),
|
| 447 |
|
|
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
|
| 448 |
|
|
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
|
| 449 |
|
|
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
|
| 450 |
|
|
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
|
| 451 |
|
|
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
|
| 452 |
|
|
.pipe_tx_data_o(pipe_tx1_data_o),
|
| 453 |
|
|
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
|
| 454 |
|
|
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
|
| 455 |
|
|
|
| 456 |
|
|
.pipe_clk(pipe_clk),
|
| 457 |
|
|
.rst_n(rst_n)
|
| 458 |
|
|
|
| 459 |
|
|
);
|
| 460 |
|
|
|
| 461 |
|
|
end
|
| 462 |
|
|
else begin
|
| 463 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 464 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 465 |
|
|
assign pipe_rx1_char_is_k_o = 2'b00;
|
| 466 |
|
|
assign pipe_rx1_data_o = 16'h0000;
|
| 467 |
|
|
assign pipe_rx1_valid_o = 1'b0;
|
| 468 |
|
|
assign pipe_rx1_chanisaligned_o = 1'b0;
|
| 469 |
|
|
assign pipe_rx1_status_o = 3'b000;
|
| 470 |
|
|
assign pipe_rx1_phy_status_o = 1'b0;
|
| 471 |
|
|
assign pipe_rx1_elec_idle_o = 1'b1;
|
| 472 |
|
|
assign pipe_rx1_polarity_o = 1'b0;
|
| 473 |
|
|
assign pipe_tx1_compliance_o = 1'b0;
|
| 474 |
|
|
assign pipe_tx1_char_is_k_o = 2'b00;
|
| 475 |
|
|
assign pipe_tx1_data_o = 16'h0000;
|
| 476 |
|
|
assign pipe_tx1_elec_idle_o = 1'b1;
|
| 477 |
|
|
assign pipe_tx1_powerdown_o = 2'b00;
|
| 478 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 479 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 480 |
|
|
end
|
| 481 |
|
|
|
| 482 |
|
|
if (NO_OF_LANES >= 4) begin
|
| 483 |
|
|
|
| 484 |
|
|
pcie_pipe_lane_v6 # (
|
| 485 |
|
|
|
| 486 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 487 |
|
|
)
|
| 488 |
|
|
pipe_lane_2_i (
|
| 489 |
|
|
|
| 490 |
|
|
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),
|
| 491 |
|
|
.pipe_rx_data_o(pipe_rx2_data_q),
|
| 492 |
|
|
.pipe_rx_valid_o(pipe_rx2_valid_o),
|
| 493 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
|
| 494 |
|
|
.pipe_rx_status_o(pipe_rx2_status_o),
|
| 495 |
|
|
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
|
| 496 |
|
|
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
|
| 497 |
|
|
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
|
| 498 |
|
|
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
|
| 499 |
|
|
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
|
| 500 |
|
|
.pipe_tx_data_i(pipe_tx2_data_i),
|
| 501 |
|
|
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
|
| 502 |
|
|
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
|
| 503 |
|
|
|
| 504 |
|
|
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
|
| 505 |
|
|
.pipe_rx_data_i(pipe_rx2_data_i),
|
| 506 |
|
|
.pipe_rx_valid_i(pipe_rx2_valid_i),
|
| 507 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
|
| 508 |
|
|
.pipe_rx_status_i(pipe_rx2_status_i),
|
| 509 |
|
|
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
|
| 510 |
|
|
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
|
| 511 |
|
|
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
|
| 512 |
|
|
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
|
| 513 |
|
|
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
|
| 514 |
|
|
.pipe_tx_data_o(pipe_tx2_data_o),
|
| 515 |
|
|
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
|
| 516 |
|
|
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
|
| 517 |
|
|
|
| 518 |
|
|
.pipe_clk(pipe_clk),
|
| 519 |
|
|
.rst_n(rst_n)
|
| 520 |
|
|
|
| 521 |
|
|
);
|
| 522 |
|
|
|
| 523 |
|
|
pcie_pipe_lane_v6 # (
|
| 524 |
|
|
|
| 525 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 526 |
|
|
|
| 527 |
|
|
)
|
| 528 |
|
|
pipe_lane_3_i (
|
| 529 |
|
|
|
| 530 |
|
|
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),
|
| 531 |
|
|
.pipe_rx_data_o(pipe_rx3_data_q),
|
| 532 |
|
|
.pipe_rx_valid_o(pipe_rx3_valid_o),
|
| 533 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
|
| 534 |
|
|
.pipe_rx_status_o(pipe_rx3_status_o),
|
| 535 |
|
|
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
|
| 536 |
|
|
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
|
| 537 |
|
|
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
|
| 538 |
|
|
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
|
| 539 |
|
|
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
|
| 540 |
|
|
.pipe_tx_data_i(pipe_tx3_data_i),
|
| 541 |
|
|
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
|
| 542 |
|
|
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
|
| 543 |
|
|
|
| 544 |
|
|
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
|
| 545 |
|
|
.pipe_rx_data_i(pipe_rx3_data_i),
|
| 546 |
|
|
.pipe_rx_valid_i(pipe_rx3_valid_i),
|
| 547 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
|
| 548 |
|
|
.pipe_rx_status_i(pipe_rx3_status_i),
|
| 549 |
|
|
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
|
| 550 |
|
|
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
|
| 551 |
|
|
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
|
| 552 |
|
|
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
|
| 553 |
|
|
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
|
| 554 |
|
|
.pipe_tx_data_o(pipe_tx3_data_o),
|
| 555 |
|
|
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
|
| 556 |
|
|
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
|
| 557 |
|
|
|
| 558 |
|
|
.pipe_clk(pipe_clk),
|
| 559 |
|
|
.rst_n(rst_n)
|
| 560 |
|
|
|
| 561 |
|
|
);
|
| 562 |
|
|
|
| 563 |
|
|
end
|
| 564 |
|
|
else begin
|
| 565 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 566 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 567 |
|
|
assign pipe_rx2_char_is_k_o = 2'b00;
|
| 568 |
|
|
assign pipe_rx2_data_o = 16'h0000;
|
| 569 |
|
|
assign pipe_rx2_valid_o = 1'b0;
|
| 570 |
|
|
assign pipe_rx2_chanisaligned_o = 1'b0;
|
| 571 |
|
|
assign pipe_rx2_status_o = 3'b000;
|
| 572 |
|
|
assign pipe_rx2_phy_status_o = 1'b0;
|
| 573 |
|
|
assign pipe_rx2_elec_idle_o = 1'b1;
|
| 574 |
|
|
assign pipe_rx2_polarity_o = 1'b0;
|
| 575 |
|
|
assign pipe_tx2_compliance_o = 1'b0;
|
| 576 |
|
|
assign pipe_tx2_char_is_k_o = 2'b00;
|
| 577 |
|
|
assign pipe_tx2_data_o = 16'h0000;
|
| 578 |
|
|
assign pipe_tx2_elec_idle_o = 1'b1;
|
| 579 |
|
|
assign pipe_tx2_powerdown_o = 2'b00;
|
| 580 |
|
|
|
| 581 |
|
|
assign pipe_rx3_char_is_k_o = 2'b00;
|
| 582 |
|
|
assign pipe_rx3_data_o = 16'h0000;
|
| 583 |
|
|
assign pipe_rx3_valid_o = 1'b0;
|
| 584 |
|
|
assign pipe_rx3_chanisaligned_o = 1'b0;
|
| 585 |
|
|
assign pipe_rx3_status_o = 3'b000;
|
| 586 |
|
|
assign pipe_rx3_phy_status_o = 1'b0;
|
| 587 |
|
|
assign pipe_rx3_elec_idle_o = 1'b1;
|
| 588 |
|
|
assign pipe_rx3_polarity_o = 1'b0;
|
| 589 |
|
|
assign pipe_tx3_compliance_o = 1'b0;
|
| 590 |
|
|
assign pipe_tx3_char_is_k_o = 2'b00;
|
| 591 |
|
|
assign pipe_tx3_data_o = 16'h0000;
|
| 592 |
|
|
assign pipe_tx3_elec_idle_o = 1'b1;
|
| 593 |
|
|
assign pipe_tx3_powerdown_o = 2'b00;
|
| 594 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 595 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 596 |
|
|
end
|
| 597 |
|
|
|
| 598 |
|
|
if (NO_OF_LANES >= 8) begin
|
| 599 |
|
|
|
| 600 |
|
|
pcie_pipe_lane_v6 # (
|
| 601 |
|
|
|
| 602 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 603 |
|
|
|
| 604 |
|
|
)
|
| 605 |
|
|
pipe_lane_4_i (
|
| 606 |
|
|
|
| 607 |
|
|
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),
|
| 608 |
|
|
.pipe_rx_data_o(pipe_rx4_data_q),
|
| 609 |
|
|
.pipe_rx_valid_o(pipe_rx4_valid_o),
|
| 610 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
|
| 611 |
|
|
.pipe_rx_status_o(pipe_rx4_status_o),
|
| 612 |
|
|
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
|
| 613 |
|
|
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
|
| 614 |
|
|
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
|
| 615 |
|
|
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
|
| 616 |
|
|
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
|
| 617 |
|
|
.pipe_tx_data_i(pipe_tx4_data_i),
|
| 618 |
|
|
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
|
| 619 |
|
|
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
|
| 620 |
|
|
|
| 621 |
|
|
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
|
| 622 |
|
|
.pipe_rx_data_i(pipe_rx4_data_i),
|
| 623 |
|
|
.pipe_rx_valid_i(pipe_rx4_valid_i),
|
| 624 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
|
| 625 |
|
|
.pipe_rx_status_i(pipe_rx4_status_i),
|
| 626 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
| 627 |
|
|
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
|
| 628 |
|
|
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
|
| 629 |
|
|
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
|
| 630 |
|
|
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
|
| 631 |
|
|
.pipe_tx_data_o(pipe_tx4_data_o),
|
| 632 |
|
|
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
|
| 633 |
|
|
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
|
| 634 |
|
|
|
| 635 |
|
|
.pipe_clk(pipe_clk),
|
| 636 |
|
|
.rst_n(rst_n)
|
| 637 |
|
|
|
| 638 |
|
|
);
|
| 639 |
|
|
|
| 640 |
|
|
pcie_pipe_lane_v6 # (
|
| 641 |
|
|
|
| 642 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 643 |
|
|
|
| 644 |
|
|
)
|
| 645 |
|
|
pipe_lane_5_i (
|
| 646 |
|
|
|
| 647 |
|
|
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),
|
| 648 |
|
|
.pipe_rx_data_o(pipe_rx5_data_q),
|
| 649 |
|
|
.pipe_rx_valid_o(pipe_rx5_valid_o),
|
| 650 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
|
| 651 |
|
|
.pipe_rx_status_o(pipe_rx5_status_o),
|
| 652 |
|
|
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
|
| 653 |
|
|
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
|
| 654 |
|
|
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
|
| 655 |
|
|
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
|
| 656 |
|
|
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
|
| 657 |
|
|
.pipe_tx_data_i(pipe_tx5_data_i),
|
| 658 |
|
|
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
|
| 659 |
|
|
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
|
| 660 |
|
|
|
| 661 |
|
|
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
|
| 662 |
|
|
.pipe_rx_data_i(pipe_rx5_data_i),
|
| 663 |
|
|
.pipe_rx_valid_i(pipe_rx5_valid_i),
|
| 664 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
|
| 665 |
|
|
.pipe_rx_status_i(pipe_rx5_status_i),
|
| 666 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
| 667 |
|
|
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
|
| 668 |
|
|
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
|
| 669 |
|
|
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
|
| 670 |
|
|
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
|
| 671 |
|
|
.pipe_tx_data_o(pipe_tx5_data_o),
|
| 672 |
|
|
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
|
| 673 |
|
|
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
|
| 674 |
|
|
|
| 675 |
|
|
.pipe_clk(pipe_clk),
|
| 676 |
|
|
.rst_n(rst_n)
|
| 677 |
|
|
|
| 678 |
|
|
);
|
| 679 |
|
|
|
| 680 |
|
|
pcie_pipe_lane_v6 # (
|
| 681 |
|
|
|
| 682 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 683 |
|
|
|
| 684 |
|
|
)
|
| 685 |
|
|
pipe_lane_6_i (
|
| 686 |
|
|
|
| 687 |
|
|
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),
|
| 688 |
|
|
.pipe_rx_data_o(pipe_rx6_data_q),
|
| 689 |
|
|
.pipe_rx_valid_o(pipe_rx6_valid_o),
|
| 690 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
|
| 691 |
|
|
.pipe_rx_status_o(pipe_rx6_status_o),
|
| 692 |
|
|
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
|
| 693 |
|
|
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
|
| 694 |
|
|
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
|
| 695 |
|
|
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
|
| 696 |
|
|
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
|
| 697 |
|
|
.pipe_tx_data_i(pipe_tx6_data_i),
|
| 698 |
|
|
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
|
| 699 |
|
|
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
|
| 700 |
|
|
|
| 701 |
|
|
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
|
| 702 |
|
|
.pipe_rx_data_i(pipe_rx6_data_i),
|
| 703 |
|
|
.pipe_rx_valid_i(pipe_rx6_valid_i),
|
| 704 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
|
| 705 |
|
|
.pipe_rx_status_i(pipe_rx6_status_i),
|
| 706 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
| 707 |
|
|
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
|
| 708 |
|
|
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
|
| 709 |
|
|
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
|
| 710 |
|
|
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
|
| 711 |
|
|
.pipe_tx_data_o(pipe_tx6_data_o),
|
| 712 |
|
|
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
|
| 713 |
|
|
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
|
| 714 |
|
|
|
| 715 |
|
|
.pipe_clk(pipe_clk),
|
| 716 |
|
|
.rst_n(rst_n)
|
| 717 |
|
|
|
| 718 |
|
|
);
|
| 719 |
|
|
|
| 720 |
|
|
pcie_pipe_lane_v6 # (
|
| 721 |
|
|
|
| 722 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
| 723 |
|
|
|
| 724 |
|
|
)
|
| 725 |
|
|
pipe_lane_7_i (
|
| 726 |
|
|
|
| 727 |
|
|
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),
|
| 728 |
|
|
.pipe_rx_data_o(pipe_rx7_data_q),
|
| 729 |
|
|
.pipe_rx_valid_o(pipe_rx7_valid_o),
|
| 730 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
|
| 731 |
|
|
.pipe_rx_status_o(pipe_rx7_status_o),
|
| 732 |
|
|
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
|
| 733 |
|
|
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
|
| 734 |
|
|
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
|
| 735 |
|
|
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
|
| 736 |
|
|
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
|
| 737 |
|
|
.pipe_tx_data_i(pipe_tx7_data_i),
|
| 738 |
|
|
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
|
| 739 |
|
|
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
|
| 740 |
|
|
|
| 741 |
|
|
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
|
| 742 |
|
|
.pipe_rx_data_i(pipe_rx7_data_i),
|
| 743 |
|
|
.pipe_rx_valid_i(pipe_rx7_valid_i),
|
| 744 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
|
| 745 |
|
|
.pipe_rx_status_i(pipe_rx7_status_i),
|
| 746 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
| 747 |
|
|
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
|
| 748 |
|
|
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
|
| 749 |
|
|
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
|
| 750 |
|
|
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
|
| 751 |
|
|
.pipe_tx_data_o(pipe_tx7_data_o),
|
| 752 |
|
|
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
|
| 753 |
|
|
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
|
| 754 |
|
|
|
| 755 |
|
|
.pipe_clk(pipe_clk),
|
| 756 |
|
|
.rst_n(rst_n)
|
| 757 |
|
|
|
| 758 |
|
|
);
|
| 759 |
|
|
|
| 760 |
|
|
end
|
| 761 |
|
|
else begin
|
| 762 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 763 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 764 |
|
|
assign pipe_rx4_char_is_k_o = 2'b00;
|
| 765 |
|
|
assign pipe_rx4_data_o = 16'h0000;
|
| 766 |
|
|
assign pipe_rx4_valid_o = 1'b0;
|
| 767 |
|
|
assign pipe_rx4_chanisaligned_o = 1'b0;
|
| 768 |
|
|
assign pipe_rx4_status_o = 3'b000;
|
| 769 |
|
|
assign pipe_rx4_phy_status_o = 1'b0;
|
| 770 |
|
|
assign pipe_rx4_elec_idle_o = 1'b1;
|
| 771 |
|
|
assign pipe_rx4_polarity_o = 1'b0;
|
| 772 |
|
|
assign pipe_tx4_compliance_o = 1'b0;
|
| 773 |
|
|
assign pipe_tx4_char_is_k_o = 2'b00;
|
| 774 |
|
|
assign pipe_tx4_data_o = 16'h0000;
|
| 775 |
|
|
assign pipe_tx4_elec_idle_o = 1'b1;
|
| 776 |
|
|
assign pipe_tx4_powerdown_o = 2'b00;
|
| 777 |
|
|
|
| 778 |
|
|
assign pipe_rx5_char_is_k_o = 2'b00;
|
| 779 |
|
|
assign pipe_rx5_data_o = 16'h0000;
|
| 780 |
|
|
assign pipe_rx5_valid_o = 1'b0;
|
| 781 |
|
|
assign pipe_rx5_chanisaligned_o = 1'b0;
|
| 782 |
|
|
assign pipe_rx5_status_o = 3'b000;
|
| 783 |
|
|
assign pipe_rx5_phy_status_o = 1'b0;
|
| 784 |
|
|
assign pipe_rx5_elec_idle_o = 1'b1;
|
| 785 |
|
|
assign pipe_rx5_polarity_o = 1'b0;
|
| 786 |
|
|
assign pipe_tx5_compliance_o = 1'b0;
|
| 787 |
|
|
assign pipe_tx5_char_is_k_o = 2'b00;
|
| 788 |
|
|
assign pipe_tx5_data_o = 16'h0000;
|
| 789 |
|
|
assign pipe_tx5_elec_idle_o = 1'b1;
|
| 790 |
|
|
assign pipe_tx5_powerdown_o = 2'b00;
|
| 791 |
|
|
|
| 792 |
|
|
assign pipe_rx6_char_is_k_o = 2'b00;
|
| 793 |
|
|
assign pipe_rx6_data_o = 16'h0000;
|
| 794 |
|
|
assign pipe_rx6_valid_o = 1'b0;
|
| 795 |
|
|
assign pipe_rx6_chanisaligned_o = 1'b0;
|
| 796 |
|
|
assign pipe_rx6_status_o = 3'b000;
|
| 797 |
|
|
assign pipe_rx6_phy_status_o = 1'b0;
|
| 798 |
|
|
assign pipe_rx6_elec_idle_o = 1'b1;
|
| 799 |
|
|
assign pipe_rx6_polarity_o = 1'b0;
|
| 800 |
|
|
assign pipe_tx6_compliance_o = 1'b0;
|
| 801 |
|
|
assign pipe_tx6_char_is_k_o = 2'b00;
|
| 802 |
|
|
assign pipe_tx6_data_o = 16'h0000;
|
| 803 |
|
|
assign pipe_tx6_elec_idle_o = 1'b1;
|
| 804 |
|
|
assign pipe_tx6_powerdown_o = 2'b00;
|
| 805 |
|
|
|
| 806 |
|
|
assign pipe_rx7_char_is_k_o = 2'b00;
|
| 807 |
|
|
assign pipe_rx7_data_o = 16'h0000;
|
| 808 |
|
|
assign pipe_rx7_valid_o = 1'b0;
|
| 809 |
|
|
assign pipe_rx7_chanisaligned_o = 1'b0;
|
| 810 |
|
|
assign pipe_rx7_status_o = 3'b000;
|
| 811 |
|
|
assign pipe_rx7_phy_status_o = 1'b0;
|
| 812 |
|
|
assign pipe_rx7_elec_idle_o = 1'b1;
|
| 813 |
|
|
assign pipe_rx7_polarity_o = 1'b0;
|
| 814 |
|
|
assign pipe_tx7_compliance_o = 1'b0;
|
| 815 |
|
|
assign pipe_tx7_char_is_k_o = 2'b00;
|
| 816 |
|
|
assign pipe_tx7_data_o = 16'h0000;
|
| 817 |
|
|
assign pipe_tx7_elec_idle_o = 1'b1;
|
| 818 |
|
|
assign pipe_tx7_powerdown_o = 2'b00;
|
| 819 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 820 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 821 |
|
|
end
|
| 822 |
|
|
|
| 823 |
|
|
endgenerate
|
| 824 |
|
|
|
| 825 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 826 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 827 |
|
|
|
| 828 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 829 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 830 |
|
|
|
| 831 |
|
|
assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
|
| 832 |
|
|
assign pipe_rx0_data_o = pipe_rx0_data_q;
|
| 833 |
|
|
assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
|
| 834 |
|
|
assign pipe_rx1_data_o = pipe_rx1_data_q;
|
| 835 |
|
|
assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
|
| 836 |
|
|
assign pipe_rx2_data_o = pipe_rx2_data_q;
|
| 837 |
|
|
assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
|
| 838 |
|
|
assign pipe_rx3_data_o = pipe_rx3_data_q;
|
| 839 |
|
|
assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
|
| 840 |
|
|
assign pipe_rx4_data_o = pipe_rx4_data_q;
|
| 841 |
|
|
assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
|
| 842 |
|
|
assign pipe_rx5_data_o = pipe_rx5_data_q;
|
| 843 |
|
|
assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
|
| 844 |
|
|
assign pipe_rx6_data_o = pipe_rx6_data_q;
|
| 845 |
|
|
assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
|
| 846 |
|
|
assign pipe_rx7_data_o = pipe_rx7_data_q;
|
| 847 |
|
|
|
| 848 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 849 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
| 850 |
|
|
|
| 851 |
|
|
endmodule
|
