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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_upconfig_fix_3451_v6.v
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// Version : 1.7
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//--
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//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_upconfig_fix_3451_v6 # (
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parameter UPSTREAM_FACING = "TRUE",
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parameter PL_FAST_TRAIN = "FALSE",
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parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08
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)
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(
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input pipe_clk,
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input pl_phy_lnkup_n,
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input [5:0] pl_ltssm_state,
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input pl_sel_lnk_rate,
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input [1:0] pl_directed_link_change,
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input [3:0] cfg_link_status_negotiated_width,
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input [15:0] pipe_rx0_data,
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input [1:0] pipe_rx0_char_isk,
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output filter_pipe
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);
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parameter TCQ = 1;
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reg reg_filter_pipe;
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reg [15:0] reg_tsx_counter;
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wire [15:0] tsx_counter;
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wire [5:0] cap_link_width;
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// Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
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// the core to see the TS1s on all the lanes being configured at the same time
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// R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
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// 225 pipe_clk cycles-sim_fast_train
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// 60000 pipe_clk cycles-without sim_fast_train
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// Not taking any action when PLDIRECTEDLINKCHANGE is set
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// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
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// data0 will be the first symbol on lane 0, data1 will be the next symbol.
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// Don't look for PAD on data1 since it's unnecessary.
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// COM=0xbc and PAD=0xf7 (and isk).
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// detect if (data & 0xb4) == 0xb4 and isk, and then
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// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
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// no more than a 6-input LUT, so should be "free".
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reg reg_filter_used, reg_com_then_pad;
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reg reg_data0_b4, reg_data0_08, reg_data0_43;
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reg reg_data1_b4, reg_data1_08, reg_data1_43;
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reg reg_data0_com, reg_data1_com, reg_data1_pad;
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wire data0_b4 = pipe_rx0_char_isk[0] &&
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((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);
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wire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);
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wire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);
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wire data1_b4 = pipe_rx0_char_isk[1] &&
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((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);
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wire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);
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wire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);
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wire data0_com = reg_data0_b4 && reg_data0_08;
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wire data1_com = reg_data1_b4 && reg_data1_08;
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wire data0_pad = reg_data0_b4 && reg_data0_43;
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wire data1_pad = reg_data1_b4 && reg_data1_43;
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wire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;
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wire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;
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wire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;
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wire filter_used = (pl_ltssm_state == 6'h20) &&
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(reg_filter_pipe || reg_filter_used);
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always @(posedge pipe_clk) begin
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reg_data0_b4 <= #TCQ data0_b4;
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reg_data0_08 <= #TCQ data0_08;
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reg_data0_43 <= #TCQ data0_43;
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reg_data1_b4 <= #TCQ data1_b4;
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reg_data1_08 <= #TCQ data1_08;
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reg_data1_43 <= #TCQ data1_43;
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reg_data0_com <= #TCQ data0_com;
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reg_data1_com <= #TCQ data1_com;
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reg_data1_pad <= #TCQ data1_pad;
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reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;
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reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;
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end
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always @ (posedge pipe_clk) begin
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if (pl_phy_lnkup_n) begin
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reg_tsx_counter <= #TCQ 16'h0;
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reg_filter_pipe <= #TCQ 1'b0;
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end else if ((pl_ltssm_state == 6'h20) &&
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reg_com_then_pad &&
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(cfg_link_status_negotiated_width != cap_link_width) &&
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(pl_directed_link_change[1:0] == 2'b00)) begin
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reg_tsx_counter <= #TCQ 16'h0;
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reg_filter_pipe <= #TCQ 1'b1;
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end else if (filter_pipe == 1'b1) begin
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if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin
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reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
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reg_filter_pipe <= #TCQ 1'b1;
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end else begin
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reg_tsx_counter <= #TCQ 16'h0;
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reg_filter_pipe <= #TCQ 1'b0;
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end
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end
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end
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assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
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assign tsx_counter = reg_tsx_counter;
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assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
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endmodule
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