Subversion Repositories pcie_sg_dma

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-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : pci_exp_usrapp_pl.vhd

-- Version    : 1.7

--

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library ieee;

   use ieee.std_logic_1164.all;

entity pci_exp_usrapp_pl is

   generic (

     LINK_CAP_MAX_LINK_SPEED : integer := 1);

   port (

      pl_initial_link_width           : in std_logic_vector(2 downto 0);

      pl_lane_reversal_mode           : in std_logic_vector(1 downto 0);

      pl_link_gen2_capable            : in std_logic;

      pl_link_partner_gen2_supported  : in std_logic;

      pl_link_upcfg_capable           : in std_logic;

      pl_ltssm_state                  : in std_logic_vector(5 downto 0);

      pl_received_hot_rst             : in std_logic;

      pl_sel_link_rate                : in std_logic;

      pl_sel_link_width               : in std_logic_vector(1 downto 0);

      pl_directed_link_auton          : out std_logic;

      pl_directed_link_change         : out std_logic_vector(1 downto 0);

      pl_directed_link_speed          : out std_logic;

      pl_directed_link_width          : out std_logic_vector(1 downto 0);

      pl_upstream_prefer_deemph       : out std_logic;

      speed_change_done_n             : out std_logic;

      trn_lnk_up_n                    : in std_logic;

      trn_clk                         : in std_logic;

      trn_reset_n                     : in std_logic

   );

end pci_exp_usrapp_pl;

architecture rtl of pci_exp_usrapp_pl is

   constant Tcq                     : integer := 1;

begin

   process

   begin

      pl_directed_link_auton <= '0';

      pl_directed_link_change <= "00";

      pl_directed_link_speed <= '0';

      pl_directed_link_width <= "00";

      pl_upstream_prefer_deemph <= '0';

      speed_change_done_n <= '1';

      if (LINK_CAP_MAX_LINK_SPEED = 2) then

         wait until trn_lnk_up_n = '0';

         pl_directed_link_speed <= '1';

         pl_directed_link_change <= "10";

         wait until pl_ltssm_state = "100000";

         pl_directed_link_speed <= '0';

         pl_directed_link_change <= "00";

         wait until pl_sel_link_rate = '1';

         speed_change_done_n <= '0';

      end if;

      wait;

   end process;

end rtl;

-- pci_exp_usrapp_pl