Subversion Repositories pcie_sg_dma

//-----------------------------------------------------------------------------

//

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//-----------------------------------------------------------------------------

// Project    : Virtex-6 Integrated Block for PCI Express

// File       : board.v

// Version    : 1.7

// Description:  Top level testbench

//

//------------------------------------------------------------------------------

`timescale 1ns/1ns

`include "board_common.v"

module board;

parameter          REF_CLK_FREQ                 = 0;      // 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz

localparam         REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :

                                        (REF_CLK_FREQ == 1) ? 4000 :

                                        (REF_CLK_FREQ == 2) ? 2000 : 0;

integer            i;

//

// System reset

//

reg                sys_reset_n;

//

// System clocks

//

wire                                   rp_sys_clk;

wire                                   ep_sys_clk_p;

wire                                   ep_sys_clk_n;

//

// PCI-Express Serial Interconnect

//

wire  [0:0]  ep_pci_exp_txn;

wire  [0:0]  ep_pci_exp_txp;

wire  [0:0]  rp_pci_exp_txn;

wire  [0:0]  rp_pci_exp_txp;

//

// PCI-Express Endpoint Instance

//

xilinx_pcie_2_0_ep_v6 # (

      .PL_FAST_TRAIN("TRUE")

)

EP (

      // SYS Inteface

      .sys_clk_p(ep_sys_clk_p),

      .sys_clk_n(ep_sys_clk_n),

      .sys_reset_n(sys_reset_n),

`ifdef ENABLE_LEDS

      // Misc signals 

      .led_0(led_0),

      .led_1(led_1),

      .led_2(led_2),

`endif

      // PCI-Express Interface

      .pci_exp_txn(ep_pci_exp_txn),

      .pci_exp_txp(ep_pci_exp_txp),

      .pci_exp_rxn(rp_pci_exp_txn),

      .pci_exp_rxp(rp_pci_exp_txp)

);

//

// PCI-Express Model Root Port Instance

//

xilinx_pcie_2_0_rport_v6 # (

      .REF_CLK_FREQ(0),

      .PL_FAST_TRAIN("TRUE"),

      .LINK_CAP_MAX_LINK_WIDTH(6'h01),

      .DEVICE_ID(16'h6021),

      .ALLOW_X8_GEN2("FALSE"),

      .LINK_CAP_MAX_LINK_SPEED(4'h2),

      .LINK_CTRL2_TARGET_LINK_SPEED(4'h2),

      .DEV_CAP_MAX_PAYLOAD_SUPPORTED(3'h2),

      .VC0_TX_LASTPACKET(29),

      .VC0_RX_RAM_LIMIT(13'h7FF),

      .VC0_CPL_INFINITE("TRUE"),

      .VC0_TOTAL_CREDITS_PD(308),

      .VC0_TOTAL_CREDITS_CD(308),

      .USER_CLK_FREQ(2)

)

RP (

      // SYS Inteface

      .sys_clk(rp_sys_clk),

      .sys_reset_n(sys_reset_n),

      // PCI-Express Interface

      .pci_exp_txn(rp_pci_exp_txn),

      .pci_exp_txp(rp_pci_exp_txp),

      .pci_exp_rxn(ep_pci_exp_txn),

      .pci_exp_rxp(ep_pci_exp_txp)

);

sys_clk_gen  # (

      .halfcycle(REF_CLK_HALF_CYCLE),

      .offset(0)

)

CLK_GEN_RP (

      .sys_clk(rp_sys_clk)

);

sys_clk_gen_ds # (

      .halfcycle(REF_CLK_HALF_CYCLE),

      .offset(0)

)

CLK_GEN_EP (

      .sys_clk_p(ep_sys_clk_p),

      .sys_clk_n(ep_sys_clk_n)

);

initial begin

  $display("[%t] : System Reset Asserted...", $realtime);

  sys_reset_n = 1'b0;

  for (i = 0; i < 500; i = i + 1) begin

    @(posedge ep_sys_clk_p);

  end

  $display("[%t] : System Reset De-asserted...", $realtime);

  sys_reset_n = 1'b1;

end

initial begin

  if ($test$plusargs ("dump_all")) begin

`ifdef NCV // Cadence TRN dump

    $recordsetup("design=board",

                 "compress",

                 "wrapsize=100M",

                 "version=1",

                 "run=1");

    $recordvars();

`elsif VCS //Synopsys VPD dump

    $vcdplusfile("board.vpd");

    $vcdpluson;

    $vcdplusglitchon;

    $vcdplusflush;

`else

    // Verilog VC dump

    $dumpfile("board.vcd");

    $dumpvars(0, board);

`endif

  end

end

endmodule // BOARD