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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : gtx_wrapper_v6.vhd
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-- Version : 1.7
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-- Description: GTX module for Virtex6 PCIe Block
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity gtx_wrapper_v6 is
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generic (
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NO_OF_LANES : integer := 1;
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REF_CLK_FREQ : integer := 0;
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PL_FAST_TRAIN : boolean := FALSE
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);
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port (
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-- TX
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TX : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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-- RX
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RX : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
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-- other
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GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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plm_in_l0 : in std_logic;
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plm_in_rl : in std_logic;
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plm_in_dt : in std_logic;
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plm_in_rs : in std_logic;
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RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxDetectRx : in std_logic;
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PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TXPdownAsynch : in std_logic;
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PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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Rate : in std_logic;
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Reset_n : in std_logic;
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GTReset_n : in std_logic;
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PCLK : in std_logic;
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REFCLK : in std_logic;
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TxDeemph : in std_logic;
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TxMargin : in std_logic;
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TxSwing : in std_logic;
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ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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local_pcs_reset : in std_logic;
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RxResetDone : out std_logic;
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SyncDone : out std_logic;
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DRPCLK : in std_logic;
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TxOutClk : out std_logic
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);
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end gtx_wrapper_v6;
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architecture v6_pcie of gtx_wrapper_v6 is
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component GTX_RX_VALID_FILTER_V6 is
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generic (
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CLK_COR_MIN_LAT : integer
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);
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port (
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USER_RXCHARISK : out std_logic_vector(1 downto 0);
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USER_RXDATA : out std_logic_vector(15 downto 0);
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USER_RXVALID : out std_logic;
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USER_RXELECIDLE : out std_logic;
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USER_RX_STATUS : out std_logic_vector(2 downto 0);
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USER_RX_PHY_STATUS : out std_logic;
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GT_RXCHARISK : in std_logic_vector(1 downto 0);
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GT_RXDATA : in std_logic_vector(15 downto 0);
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GT_RXVALID : in std_logic;
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GT_RXELECIDLE : in std_logic;
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GT_RX_STATUS : in std_logic_vector(2 downto 0);
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GT_RX_PHY_STATUS : in std_logic;
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PLM_IN_L0 : in std_logic;
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PLM_IN_RS : in std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic
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);
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end component;
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component GTX_DRP_CHANALIGN_FIX_3752_V6 is
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generic (
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C_SIMULATION : integer
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);
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port (
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dwe : out std_logic;
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din : out std_logic_vector(15 downto 0);
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den : out std_logic;
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daddr : out std_logic_vector(7 downto 0);
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drpstate : out std_logic_vector(3 downto 0);
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write_ts1 : in std_logic;
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write_fts : in std_logic;
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dout : in std_logic_vector(15 downto 0);
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drdy : in std_logic;
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Reset_n : in std_logic;
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drp_clk : in std_logic
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);
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end component;
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component GTX_TX_SYNC_RATE_V6 is
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generic (
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C_SIMULATION : integer
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);
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port (
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ENPMAPHASEALIGN : out std_logic;
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PMASETPHASE : out std_logic;
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SYNC_DONE : out std_logic;
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OUT_DIV_RESET : out std_logic;
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PCS_RESET : out std_logic;
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USER_PHYSTATUS : out std_logic;
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TXALIGNDISABLE : out std_logic;
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DELAYALIGNRESET : out std_logic;
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USER_CLK : in std_logic;
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RESET : in std_logic;
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RATE : in std_logic;
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RATEDONE : in std_logic;
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GT_PHYSTATUS : in std_logic;
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RESETDONE : in std_logic
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);
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end component;
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FUNCTION to_stdlogicvector (
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val_in : IN integer;
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length : IN integer) RETURN std_logic_vector IS
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VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0');
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VARIABLE num : integer := val_in;
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VARIABLE x : integer;
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BEGIN
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FOR index IN 0 TO length-1 LOOP
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x := num rem 2;
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num := num/2;
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IF (x = 1) THEN
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ret(index) := '1';
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ELSE
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ret(index) := '0';
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END IF;
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END LOOP;
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RETURN(ret);
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END to_stdlogicvector;
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FUNCTION and_bw (
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val_in : std_logic_vector) RETURN std_logic IS
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VARIABLE ret : std_logic := '1';
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BEGIN
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FOR index IN val_in'RANGE LOOP
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ret := ret AND val_in(index);
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END LOOP;
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RETURN(ret);
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END and_bw;
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FUNCTION to_integer (
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in_val : IN boolean) RETURN integer IS
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BEGIN
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IF (in_val) THEN
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RETURN(1);
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ELSE
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RETURN(0);
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END IF;
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END to_integer;
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FUNCTION to_stdlogic (
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in_val : IN boolean) RETURN std_logic IS
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BEGIN
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IF (in_val) THEN
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RETURN('1');
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ELSE
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RETURN('0');
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END IF;
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END to_stdlogic;
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-- purpose: PLL_CP_CFG selector function
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function pll_cp_cfg_sel (
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ref_freq : integer)
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return bit_vector is
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begin -- pll_cp_cfg_sel
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if (ref_freq = 2) then
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return (X"05");
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else
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return (X"05");
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end if;
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end pll_cp_cfg_sel;
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FUNCTION clk_div (
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in_val : IN integer) RETURN integer IS
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BEGIN
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if (in_val = 0) THEN
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return (4);
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elsif (in_val = 1) then
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return (5);
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else
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return (10);
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end if;
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END clk_div;
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FUNCTION pll_div (
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in_val : IN integer) RETURN integer IS
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BEGIN
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if (in_val = 0) THEN
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return (5);
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elsif (in_val = 1) then
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return (4);
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elsif (in_val = 2) then
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return (2);
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else
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return (0);
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end if;
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END pll_div;
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-- ground and tied_to_vcc_i signals
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signal tied_to_ground_i : std_logic;
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signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
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signal tied_to_vcc_i : std_logic;
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type type_v6pcie10 is array (NO_OF_LANES + 1 downto 0) of std_logic_vector(3 downto 0);
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type type_v6pcie11 is array (NO_OF_LANES - 1 downto 0) of std_logic;
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type type_v6pcie16 is array (NO_OF_LANES - 1 downto 0) of std_logic_vector(12 downto 0);
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-- dummy signals to avoid port mismatch with DUAL_GTX
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signal RxData_dummy : std_logic_vector(15 downto 0);
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signal RxDataK_dummy : std_logic_vector(1 downto 0);
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signal TxData_dummy : std_logic_vector(15 downto 0);
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signal TxDataK_dummy : std_logic_vector(1 downto 0);
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-- inputs
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signal GTX_TxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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signal GTX_TxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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signal GTX_TxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_TxCompliance : std_logic_vector((NO_OF_LANES - 1) downto 0);
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signal GTX_RXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_RXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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-- outputs
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signal GTX_TXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_TXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_RxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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signal GTX_RxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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signal GTX_RxPolarity : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_RxValid : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_RxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
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signal GTX_RxResetDone : std_logic_vector((NO_OF_LANES - 1) downto 0);
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signal GTX_RxChbondLevel : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
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signal GTX_RxStatus : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
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signal RXCHBOND : type_v6pcie10;
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signal TXBYPASS8B10B : std_logic_vector(3 downto 0);
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signal RXDEC8B10BUSE : std_logic;
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signal GTX_PhyStatus : std_logic_vector(NO_OF_LANES - 1 downto 0);
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signal RESETDONE : type_v6pcie11;
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signal GTXRESET : std_logic;
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signal RXRECCLK : std_logic;
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signal SYNC_DONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
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signal OUT_DIV_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
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signal PCS_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
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signal TXENPMAPHASEALIGN : std_logic_vector(NO_OF_LANES - 1 downto 0);
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signal TXPMASETPHASE : std_logic_vector(NO_OF_LANES - 1 downto 0);
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|
|
signal TXRESETDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
327 |
|
|
signal TXRATEDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
328 |
|
|
signal PHYSTATUS_int : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
329 |
|
|
signal RATE_CLK_SEL : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
330 |
|
|
signal TXOCLK : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
331 |
|
|
signal TXDLYALIGNDISABLE : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
332 |
|
|
signal TXDLYALIGNRESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
333 |
|
|
|
334 |
|
|
signal GTX_RxResetDone_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
|
335 |
|
|
signal TXRESETDONE_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
|
336 |
|
|
|
337 |
|
|
signal daddr : std_logic_vector((NO_OF_LANES * 8 - 1) downto 0);
|
338 |
|
|
signal den : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
339 |
|
|
signal din : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
|
340 |
|
|
signal dwe : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
341 |
|
|
|
342 |
|
|
signal drpstate : std_logic_vector((NO_OF_LANES * 4 - 1) downto 0);
|
343 |
|
|
signal drdy : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
344 |
|
|
signal dout : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
|
345 |
|
|
|
346 |
|
|
signal write_drp_cb_fts : std_logic;
|
347 |
|
|
signal write_drp_cb_ts1 : std_logic;
|
348 |
|
|
|
349 |
|
|
-- X-HDL generated signals
|
350 |
|
|
|
351 |
|
|
signal v6pcie12 : std_logic;
|
352 |
|
|
signal v6pcie13 : std_logic;
|
353 |
|
|
signal v6pcie14 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
354 |
|
|
signal v6pcie15 : std_logic;
|
355 |
|
|
signal v6pcie16 : type_v6pcie16;
|
356 |
|
|
signal v6pcie18 : std_logic_vector(1 downto 0);
|
357 |
|
|
signal v6pcie21 : std_logic_vector((NO_OF_LANES*4) - 1 downto 0);
|
358 |
|
|
signal v6pcie23 : std_logic_vector((NO_OF_LANES*32) - 1 downto 0);
|
359 |
|
|
signal v6pcie24 : std_logic_vector(1 downto 0);
|
360 |
|
|
signal v6pcie25 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
361 |
|
|
signal v6pcie26 : std_logic_vector(19 downto 0);
|
362 |
|
|
signal v6pcie27 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
|
363 |
|
|
signal v6pcie28 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
|
364 |
|
|
signal v6pcie29 : std_logic_vector((NO_OF_LANES * 32) - 1 downto 0) := (others => '0');
|
365 |
|
|
signal v6pcie30 : std_logic_vector(2 downto 0);
|
366 |
|
|
|
367 |
|
|
-- Declare intermediate signals for referenced outputs
|
368 |
|
|
signal RxData_v6pcie3 : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
|
369 |
|
|
signal RxDataK_v6pcie4 : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
|
370 |
|
|
signal RxValid_v6pcie8 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
371 |
|
|
signal RxElecIdle_v6pcie5 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
372 |
|
|
signal RxStatus_v6pcie7 : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
|
373 |
|
|
signal RxPLLLkDet_v6pcie6 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
374 |
|
|
signal PhyStatus_v6pcie1 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
375 |
|
|
signal ChanIsAligned_v6pcie0 : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
376 |
|
|
begin
|
377 |
|
|
|
378 |
|
|
--------------------------- Static signal Assignments ---------------------
|
379 |
|
|
|
380 |
|
|
tied_to_ground_i <= '0';
|
381 |
|
|
tied_to_ground_vec_i(31 downto 0) <= (others => '0');
|
382 |
|
|
tied_to_vcc_i <= '1';
|
383 |
|
|
|
384 |
|
|
-- Drive referenced outputs
|
385 |
|
|
RxData <= RxData_v6pcie3;
|
386 |
|
|
RxDataK <= RxDataK_v6pcie4;
|
387 |
|
|
RxValid <= RxValid_v6pcie8;
|
388 |
|
|
RxElecIdle <= RxElecIdle_v6pcie5;
|
389 |
|
|
RxStatus <= RxStatus_v6pcie7;
|
390 |
|
|
RxPLLLkDet <= RxPLLLkDet_v6pcie6;
|
391 |
|
|
PhyStatus <= PhyStatus_v6pcie1;
|
392 |
|
|
ChanIsAligned <= ChanIsAligned_v6pcie0;
|
393 |
|
|
GTX_TxData <= TxData;
|
394 |
|
|
GTX_TxDataK <= TxDataK;
|
395 |
|
|
GTX_TxElecIdle <= TxElecIdle;
|
396 |
|
|
GTX_TxCompliance <= TxCompliance;
|
397 |
|
|
GTX_RXP <= RX((NO_OF_LANES) - 1 downto 0);
|
398 |
|
|
GTX_RXN <= RXN((NO_OF_LANES) - 1 downto 0);
|
399 |
|
|
GTX_RxPolarity <= RxPolarity;
|
400 |
|
|
TXBYPASS8B10B <= "0000";
|
401 |
|
|
RXDEC8B10BUSE <= '1';
|
402 |
|
|
GTXRESET <= '0';
|
403 |
|
|
|
404 |
|
|
RxResetDone <= and_bw((GTX_RxResetDone_q((NO_OF_LANES) - 1 downto 0)));
|
405 |
|
|
TX((NO_OF_LANES - 1) downto 0) <= GTX_TXP((NO_OF_LANES - 1) downto 0);
|
406 |
|
|
TXN((NO_OF_LANES - 1) downto 0) <= GTX_TXN((NO_OF_LANES - 1) downto 0);
|
407 |
|
|
RXCHBOND(0) <= "0000";
|
408 |
|
|
TxData_dummy <= "0000000000000000";
|
409 |
|
|
TxDataK_dummy <= "00";
|
410 |
|
|
SyncDone <= and_bw((SYNC_DONE((NO_OF_LANES - 1) downto 0)));
|
411 |
|
|
TxOutClk <= TXOCLK(0);
|
412 |
|
|
|
413 |
|
|
write_drp_cb_fts <= plm_in_l0;
|
414 |
|
|
write_drp_cb_ts1 <= plm_in_rl or plm_in_dt;
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
-- pipeline to improve timing
|
418 |
|
|
process (PCLK)
|
419 |
|
|
begin
|
420 |
|
|
if (PCLK'event and PCLK = '1') then
|
421 |
|
|
|
422 |
|
|
GTX_RxResetDone_q((NO_OF_LANES - 1) downto 0) <= GTX_RxResetDone((NO_OF_LANES - 1) downto 0);
|
423 |
|
|
|
424 |
|
|
TXRESETDONE_q((NO_OF_LANES - 1) downto 0) <= TXRESETDONE((NO_OF_LANES - 1) downto 0);
|
425 |
|
|
end if;
|
426 |
|
|
end process;
|
427 |
|
|
|
428 |
|
|
GTXD : for i in 0 to (NO_OF_LANES - 1) generate
|
429 |
|
|
GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)) <= (to_stdlogicvector((NO_OF_LANES - (i + 1)), 3));
|
430 |
|
|
|
431 |
|
|
GTX_DRP_CHANALIGN_FIX_3752 : GTX_DRP_CHANALIGN_FIX_3752_V6
|
432 |
|
|
generic map (
|
433 |
|
|
C_SIMULATION => to_integer(PL_FAST_TRAIN)
|
434 |
|
|
)
|
435 |
|
|
port map (
|
436 |
|
|
|
437 |
|
|
dwe => dwe(i),
|
438 |
|
|
din => din((16 * i) + 15 downto (16 * i)),
|
439 |
|
|
den => den(i),
|
440 |
|
|
daddr => daddr((8 * i) + 7 downto (8 * i)),
|
441 |
|
|
drpstate => drpstate((4 * i) + 3 downto (4 * i)),
|
442 |
|
|
write_ts1 => write_drp_cb_ts1,
|
443 |
|
|
write_fts => write_drp_cb_fts,
|
444 |
|
|
dout => dout((16 * i) + 15 downto (16 * i)),
|
445 |
|
|
drdy => drdy(i),
|
446 |
|
|
Reset_n => Reset_n,
|
447 |
|
|
drp_clk => DRPCLK
|
448 |
|
|
);
|
449 |
|
|
|
450 |
|
|
v6pcie12 <= not(Reset_n); --I
|
451 |
|
|
|
452 |
|
|
GTX_RX_VALID_FILTER : GTX_RX_VALID_FILTER_V6
|
453 |
|
|
generic map (
|
454 |
|
|
CLK_COR_MIN_LAT => 28
|
455 |
|
|
)
|
456 |
|
|
port map (
|
457 |
|
|
USER_RXCHARISK => RxDataK_v6pcie4((2 * i) + 1 downto 2 * i), --O
|
458 |
|
|
USER_RXDATA => RxData_v6pcie3((16 * i) + 15 downto (16 * i) + 0), --O
|
459 |
|
|
USER_RXVALID => RxValid_v6pcie8(i), --O
|
460 |
|
|
USER_RXELECIDLE => RxElecIdle_v6pcie5(i), --O
|
461 |
|
|
USER_RX_STATUS => RxStatus_v6pcie7((3 * i) + 2 downto (3 * i)), --O
|
462 |
|
|
USER_RX_PHY_STATUS => PhyStatus_v6pcie1(i), --O
|
463 |
|
|
GT_RXCHARISK => GTX_RxDataK((2 * i) + 1 downto 2 * i), --I
|
464 |
|
|
GT_RXDATA => GTX_RxData((16 * i) + 15 downto (16 * i) + 0), --I
|
465 |
|
|
GT_RXVALID => GTX_RxValid(i), --I
|
466 |
|
|
GT_RXELECIDLE => GTX_RxElecIdle(i), --I
|
467 |
|
|
GT_RX_STATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)), --I
|
468 |
|
|
GT_RX_PHY_STATUS => PHYSTATUS_int(i), --I
|
469 |
|
|
PLM_IN_L0 => plm_in_l0, --I
|
470 |
|
|
PLM_IN_RS => plm_in_rs, --I
|
471 |
|
|
USER_CLK => PCLK, --I
|
472 |
|
|
RESET => v6pcie12 --I
|
473 |
|
|
);
|
474 |
|
|
|
475 |
|
|
v6pcie14(i) <= (TXRESETDONE_q(i) and GTX_RxResetDone_q(i)); --I
|
476 |
|
|
|
477 |
|
|
GTX_TX_SYNC : GTX_TX_SYNC_RATE_V6
|
478 |
|
|
generic map (
|
479 |
|
|
C_SIMULATION => to_integer(PL_FAST_TRAIN)
|
480 |
|
|
)
|
481 |
|
|
port map (
|
482 |
|
|
ENPMAPHASEALIGN => TXENPMAPHASEALIGN(i), --O
|
483 |
|
|
PMASETPHASE => TXPMASETPHASE(i), --O
|
484 |
|
|
SYNC_DONE => SYNC_DONE(i), --O
|
485 |
|
|
OUT_DIV_RESET => OUT_DIV_RESET(i), --O
|
486 |
|
|
PCS_RESET => PCS_RESET(i), --O
|
487 |
|
|
USER_PHYSTATUS => PHYSTATUS_int(i), --O
|
488 |
|
|
TXALIGNDISABLE => TXDLYALIGNDISABLE(i), --O
|
489 |
|
|
DELAYALIGNRESET => TXDLYALIGNRESET(i), --O
|
490 |
|
|
USER_CLK => PCLK, --I
|
491 |
|
|
RESET => v6pcie12, --I
|
492 |
|
|
RATE => Rate, --I
|
493 |
|
|
RATEDONE => TXRATEDONE(i), --I
|
494 |
|
|
GT_PHYSTATUS => GTX_PhyStatus(i), --I
|
495 |
|
|
RESETDONE => v6pcie14(i) --I
|
496 |
|
|
);
|
497 |
|
|
|
498 |
|
|
v6pcie15 <= not(GTReset_n);
|
499 |
|
|
v6pcie16(i) <= ("10000000000" & OUT_DIV_RESET(i) & '0');
|
500 |
|
|
v6pcie18 <= ('0' & REFCLK);
|
501 |
|
|
GTX_RxDataK((2 * i) + 1 downto 2 * i) <= v6pcie21((4*i)+1 downto (4*i));
|
502 |
|
|
GTX_RxData((16 * i) + 15 downto (16 * i) + 0) <= v6pcie23((32*i)+15 downto (32*i));
|
503 |
|
|
v6pcie24 <= ('1' & Rate);
|
504 |
|
|
v6pcie25(i) <= not(GTReset_n) or local_pcs_reset or PCS_RESET(i);
|
505 |
|
|
v6pcie26 <= (others => '1');
|
506 |
|
|
v6pcie27((4 * i) + 3 downto (4 * i) + 0) <= ("000" & GTX_TxCompliance(i));
|
507 |
|
|
v6pcie28((4 * i) + 3 downto (4 * i) + 0) <= (TxDataK_dummy(1 downto 0) & GTX_TxDataK((2 * i) + 1 downto 2 * i));
|
508 |
|
|
v6pcie29((32 * i) + 31 downto (32 * i) + 0) <= (TxData_dummy(15 downto 0) & GTX_TxData((16 * i) + 15 downto (16 * i) + 0));
|
509 |
|
|
|
510 |
|
|
v6pcie30 <= (TxMargin & "00");
|
511 |
|
|
|
512 |
|
|
GTX : GTXE1
|
513 |
|
|
generic map (
|
514 |
|
|
TX_DRIVE_MODE => "PIPE",
|
515 |
|
|
TX_DEEMPH_1 => "10010",
|
516 |
|
|
TX_MARGIN_FULL_0 => "1001101",
|
517 |
|
|
TX_CLK_SOURCE => "RXPLL",
|
518 |
|
|
POWER_SAVE => "0000110100",
|
519 |
|
|
CM_TRIM => "01",
|
520 |
|
|
PMA_CDR_SCAN => x"640404C",
|
521 |
|
|
PMA_CFG => x"0040000040000000003",
|
522 |
|
|
RCV_TERM_GND => TRUE,
|
523 |
|
|
RCV_TERM_VTTRX => FALSE,
|
524 |
|
|
RX_DLYALIGN_EDGESET => "00010",
|
525 |
|
|
RX_DLYALIGN_LPFINC => "0110",
|
526 |
|
|
RX_DLYALIGN_OVRDSETTING => "10000000",
|
527 |
|
|
TERMINATION_CTRL => "00000",
|
528 |
|
|
TERMINATION_OVRD => FALSE,
|
529 |
|
|
TX_DLYALIGN_LPFINC => "0110",
|
530 |
|
|
TX_DLYALIGN_OVRDSETTING => "10000000",
|
531 |
|
|
TXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
|
532 |
|
|
OOBDETECT_THRESHOLD => "011",
|
533 |
|
|
RXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
|
534 |
|
|
-------------------------------------------------------------------------
|
535 |
|
|
-- TX_DETECT_RX_CFG => x"1832",
|
536 |
|
|
-------------------------------------------------------------------------
|
537 |
|
|
TX_TDCC_CFG => "11",
|
538 |
|
|
BIAS_CFG => x"00000",
|
539 |
|
|
AC_CAP_DIS => FALSE,
|
540 |
|
|
DFE_CFG => "00011011",
|
541 |
|
|
SIM_TX_ELEC_IDLE_LEVEL => "1",
|
542 |
|
|
SIM_RECEIVER_DETECT_PASS => TRUE,
|
543 |
|
|
RX_EN_REALIGN_RESET_BUF => FALSE,
|
544 |
|
|
TX_IDLE_ASSERT_DELAY => "100", -- TX-idle-set-to-idle (13 UI)
|
545 |
|
|
TX_IDLE_DEASSERT_DELAY => "010", -- TX-idle-to-diff (7 UI)
|
546 |
|
|
CHAN_BOND_SEQ_2_CFG => "11111", -- 5'b11111 for PCIE mode, 5'b00000 for other modes
|
547 |
|
|
CHAN_BOND_KEEP_ALIGN => TRUE,
|
548 |
|
|
RX_IDLE_HI_CNT => "1000",
|
549 |
|
|
RX_IDLE_LO_CNT => "0000",
|
550 |
|
|
RX_EN_IDLE_RESET_BUF => TRUE,
|
551 |
|
|
TX_DATA_WIDTH => 20,
|
552 |
|
|
RX_DATA_WIDTH => 20,
|
553 |
|
|
ALIGN_COMMA_WORD => 1,
|
554 |
|
|
CHAN_BOND_1_MAX_SKEW => 7,
|
555 |
|
|
CHAN_BOND_2_MAX_SKEW => 1,
|
556 |
|
|
CHAN_BOND_SEQ_1_1 => "0001000101", -- D5.2 (end TS2)
|
557 |
|
|
CHAN_BOND_SEQ_1_2 => "0001000101", -- D5.2 (end TS2)
|
558 |
|
|
CHAN_BOND_SEQ_1_3 => "0001000101", -- D5.2 (end TS2)
|
559 |
|
|
CHAN_BOND_SEQ_1_4 => "0110111100", -- K28.5 (COM)
|
560 |
|
|
CHAN_BOND_SEQ_1_ENABLE => "1111", -- order is 4321
|
561 |
|
|
CHAN_BOND_SEQ_2_1 => "0100111100", -- K28.1 (FTS)
|
562 |
|
|
CHAN_BOND_SEQ_2_2 => "0100111100", -- K28.1 (FTS)
|
563 |
|
|
CHAN_BOND_SEQ_2_3 => "0110111100", -- K28.5 (COM)
|
564 |
|
|
CHAN_BOND_SEQ_2_4 => "0100111100", -- K28.1 (FTS)
|
565 |
|
|
CHAN_BOND_SEQ_2_ENABLE => "1111", -- order is 4321
|
566 |
|
|
CHAN_BOND_SEQ_2_USE => TRUE,
|
567 |
|
|
CHAN_BOND_SEQ_LEN => 4, -- 1..4
|
568 |
|
|
RX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
|
569 |
|
|
TX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
|
570 |
|
|
CLK_COR_ADJ_LEN => 1, -- 1..4
|
571 |
|
|
CLK_COR_DET_LEN => 1, -- 1..4
|
572 |
|
|
CLK_COR_INSERT_IDLE_FLAG => FALSE,
|
573 |
|
|
CLK_COR_KEEP_IDLE => FALSE,
|
574 |
|
|
CLK_COR_MAX_LAT => 30,
|
575 |
|
|
CLK_COR_MIN_LAT => 28,
|
576 |
|
|
CLK_COR_PRECEDENCE => TRUE,
|
577 |
|
|
CLK_CORRECT_USE => TRUE,
|
578 |
|
|
CLK_COR_REPEAT_WAIT => 0,
|
579 |
|
|
CLK_COR_SEQ_1_1 => "0100011100", -- K28.0 (SKP)
|
580 |
|
|
CLK_COR_SEQ_1_2 => "0000000000",
|
581 |
|
|
CLK_COR_SEQ_1_3 => "0000000000",
|
582 |
|
|
CLK_COR_SEQ_1_4 => "0000000000",
|
583 |
|
|
CLK_COR_SEQ_1_ENABLE => "1111",
|
584 |
|
|
CLK_COR_SEQ_2_1 => "0000000000",
|
585 |
|
|
CLK_COR_SEQ_2_2 => "0000000000",
|
586 |
|
|
CLK_COR_SEQ_2_3 => "0000000000",
|
587 |
|
|
CLK_COR_SEQ_2_4 => "0000000000",
|
588 |
|
|
CLK_COR_SEQ_2_ENABLE => "1111",
|
589 |
|
|
CLK_COR_SEQ_2_USE => FALSE,
|
590 |
|
|
COMMA_10B_ENABLE => "1111111111",
|
591 |
|
|
COMMA_DOUBLE => FALSE,
|
592 |
|
|
DEC_MCOMMA_DETECT => TRUE,
|
593 |
|
|
DEC_PCOMMA_DETECT => TRUE,
|
594 |
|
|
DEC_VALID_COMMA_ONLY => TRUE,
|
595 |
|
|
MCOMMA_10B_VALUE => "1010000011",
|
596 |
|
|
MCOMMA_DETECT => TRUE,
|
597 |
|
|
PCI_EXPRESS_MODE => TRUE,
|
598 |
|
|
PCOMMA_10B_VALUE => "0101111100",
|
599 |
|
|
PCOMMA_DETECT => TRUE,
|
600 |
|
|
RXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
|
601 |
|
|
TXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
|
602 |
|
|
RXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
|
603 |
|
|
TXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
|
604 |
|
|
RXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
|
605 |
|
|
TXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
|
606 |
|
|
RXPLL_DIVSEL45_FB => 5,
|
607 |
|
|
TXPLL_DIVSEL45_FB => 5,
|
608 |
|
|
RX_BUFFER_USE => TRUE,
|
609 |
|
|
RX_DECODE_SEQ_MATCH => TRUE,
|
610 |
|
|
RX_LOS_INVALID_INCR => 8, -- power of 2: 1..128
|
611 |
|
|
RX_LOSS_OF_SYNC_FSM => FALSE,
|
612 |
|
|
RX_LOS_THRESHOLD => 128, -- power of 2: 4..512
|
613 |
|
|
RX_SLIDE_MODE => "OFF", -- 00=OFF 01=AUTO 10=PCS 11=PMA
|
614 |
|
|
RX_XCLK_SEL => "RXREC",
|
615 |
|
|
TX_BUFFER_USE => FALSE, -- Must be set to FALSE for use by PCIE
|
616 |
|
|
TX_XCLK_SEL => "TXUSR", -- Must be set to TXUSR for use by PCIE
|
617 |
|
|
TXPLL_LKDET_CFG => "101",
|
618 |
|
|
RX_EYE_SCANMODE => "00",
|
619 |
|
|
RX_EYE_OFFSET => x"4C",
|
620 |
|
|
PMA_RX_CFG => x"05ce008",
|
621 |
|
|
TRANS_TIME_NON_P2 => x"02", -- Reduced simulation time
|
622 |
|
|
TRANS_TIME_FROM_P2 => x"03c", -- Reduced simulation time
|
623 |
|
|
TRANS_TIME_TO_P2 => x"064", -- Reduced simulation time
|
624 |
|
|
TRANS_TIME_RATE => x"D7", -- Reduced simulation time
|
625 |
|
|
SHOW_REALIGN_COMMA => FALSE,
|
626 |
|
|
TX_PMADATA_OPT => '1', -- Lockup latch between PCS and PMA
|
627 |
|
|
PMA_TX_CFG => x"80082", -- Aligns posedge of USRCLK
|
628 |
|
|
TXOUTCLK_CTRL => "TXPLLREFCLK_DIV1"
|
629 |
|
|
)
|
630 |
|
|
port map (
|
631 |
|
|
COMFINISH => open,
|
632 |
|
|
COMINITDET => open,
|
633 |
|
|
COMSASDET => open,
|
634 |
|
|
COMWAKEDET => open,
|
635 |
|
|
DADDR => daddr((8 * i) + 7 downto (8 * i)),
|
636 |
|
|
DCLK => DRPCLK,
|
637 |
|
|
DEN => den(i),
|
638 |
|
|
DFECLKDLYADJ => "000000", -- Hex 13
|
639 |
|
|
DFECLKDLYADJMON => open,
|
640 |
|
|
DFEDLYOVRD => '1',
|
641 |
|
|
DFEEYEDACMON => open,
|
642 |
|
|
DFESENSCAL => open,
|
643 |
|
|
DFETAP1 => "00000",
|
644 |
|
|
DFETAP1MONITOR => open,
|
645 |
|
|
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
|
646 |
|
|
DFETAP2MONITOR => open,
|
647 |
|
|
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
|
648 |
|
|
DFETAP3MONITOR => open,
|
649 |
|
|
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
|
650 |
|
|
DFETAP4MONITOR => open,
|
651 |
|
|
DFETAPOVRD => '1',
|
652 |
|
|
DI => din((16 * i) + 15 downto (16 * i)),
|
653 |
|
|
DRDY => drdy(i),
|
654 |
|
|
DRPDO => dout((16 * i) + 15 downto (16 * i)),
|
655 |
|
|
DWE => dwe(i),
|
656 |
|
|
GATERXELECIDLE => '0',
|
657 |
|
|
GREFCLKRX => tied_to_ground_i,
|
658 |
|
|
GREFCLKTX => tied_to_ground_i,
|
659 |
|
|
GTXRXRESET => v6pcie15,
|
660 |
|
|
GTXTEST => v6pcie16(i),
|
661 |
|
|
GTXTXRESET => v6pcie15,
|
662 |
|
|
LOOPBACK => "000",
|
663 |
|
|
MGTREFCLKFAB => open,
|
664 |
|
|
MGTREFCLKRX => v6pcie18,
|
665 |
|
|
MGTREFCLKTX => v6pcie18,
|
666 |
|
|
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
|
667 |
|
|
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
|
668 |
|
|
PHYSTATUS => GTX_PhyStatus(i),
|
669 |
|
|
PLLRXRESET => '0',
|
670 |
|
|
PLLTXRESET => '0',
|
671 |
|
|
PRBSCNTRESET => '0',
|
672 |
|
|
RXBUFRESET => '0',
|
673 |
|
|
RXBUFSTATUS => open,
|
674 |
|
|
RXBYTEISALIGNED => open,
|
675 |
|
|
RXBYTEREALIGN => open,
|
676 |
|
|
RXCDRRESET => '0',
|
677 |
|
|
RXCHANBONDSEQ => open,
|
678 |
|
|
RXCHANISALIGNED => ChanIsAligned_v6pcie0(i),
|
679 |
|
|
RXCHANREALIGN => open,
|
680 |
|
|
RXCHARISCOMMA => open,
|
681 |
|
|
RXCHARISK => v6pcie21((4 * i) + 3 downto (4 * i)),
|
682 |
|
|
RXCHBONDI => RXCHBOND(i),
|
683 |
|
|
RXCHBONDLEVEL => GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)),
|
684 |
|
|
RXCHBONDMASTER => to_stdlogic(i = 0),
|
685 |
|
|
RXCHBONDO => RXCHBOND(i + 1),
|
686 |
|
|
RXCHBONDSLAVE => to_stdlogic(i > 0),
|
687 |
|
|
RXCLKCORCNT => open,
|
688 |
|
|
RXCOMMADET => open,
|
689 |
|
|
RXCOMMADETUSE => '1',
|
690 |
|
|
RXDATA => v6pcie23(((32 * i) + 31) downto (32 * i)),
|
691 |
|
|
RXDATAVALID => open,
|
692 |
|
|
RXDEC8B10BUSE => RXDEC8B10BUSE,
|
693 |
|
|
RXDISPERR => open,
|
694 |
|
|
RXDLYALIGNDISABLE => '1',
|
695 |
|
|
RXELECIDLE => GTX_RxElecIdle(i),
|
696 |
|
|
RXENCHANSYNC => '1',
|
697 |
|
|
RXENMCOMMAALIGN => '1',
|
698 |
|
|
RXENPCOMMAALIGN => '1',
|
699 |
|
|
RXENPMAPHASEALIGN => '0',
|
700 |
|
|
RXENPRBSTST => "000",
|
701 |
|
|
RXENSAMPLEALIGN => '0',
|
702 |
|
|
RXDLYALIGNMONENB => '1',
|
703 |
|
|
RXEQMIX => "0110000011",
|
704 |
|
|
RXGEARBOXSLIP => '0',
|
705 |
|
|
RXHEADER => open,
|
706 |
|
|
RXHEADERVALID => open,
|
707 |
|
|
RXLOSSOFSYNC => open,
|
708 |
|
|
RXN => GTX_RXN(i),
|
709 |
|
|
RXNOTINTABLE => open,
|
710 |
|
|
RXOVERSAMPLEERR => open,
|
711 |
|
|
RXP => GTX_RXP(i),
|
712 |
|
|
RXPLLLKDET => RxPLLLkDet_v6pcie6(i),
|
713 |
|
|
RXPLLLKDETEN => '1',
|
714 |
|
|
RXPLLPOWERDOWN => '0',
|
715 |
|
|
RXPLLREFSELDY => "000",
|
716 |
|
|
RXPMASETPHASE => '0',
|
717 |
|
|
RXPOLARITY => GTX_RxPolarity(i),
|
718 |
|
|
RXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
|
719 |
|
|
RXPRBSERR => open,
|
720 |
|
|
RXRATE => v6pcie24,
|
721 |
|
|
RXRATEDONE => open,
|
722 |
|
|
RXRECCLK => RXRECCLK,
|
723 |
|
|
RXRECCLKPCS => open,
|
724 |
|
|
RXRESET => v6pcie25(i),
|
725 |
|
|
RXRESETDONE => GTX_RxResetDone(i),
|
726 |
|
|
RXRUNDISP => open,
|
727 |
|
|
RXSLIDE => '0',
|
728 |
|
|
RXSTARTOFSEQ => open,
|
729 |
|
|
RXSTATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)),
|
730 |
|
|
RXUSRCLK => PCLK,
|
731 |
|
|
RXUSRCLK2 => PCLK,
|
732 |
|
|
RXVALID => GTX_RxValid(i),
|
733 |
|
|
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
|
734 |
|
|
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
|
735 |
|
|
TSTCLK0 => '0',
|
736 |
|
|
TSTCLK1 => '0',
|
737 |
|
|
TSTIN => v6pcie26,
|
738 |
|
|
TSTOUT => open,
|
739 |
|
|
TXBUFDIFFCTRL => "111",
|
740 |
|
|
TXBUFSTATUS => open,
|
741 |
|
|
TXBYPASS8B10B => TXBYPASS8B10B(3 downto 0),
|
742 |
|
|
TXCHARDISPMODE => v6pcie27((4 * i) + 3 downto (4 * i) + 0),
|
743 |
|
|
TXCHARDISPVAL => "0000",
|
744 |
|
|
TXCHARISK => v6pcie28((4 * i) + 3 downto (4 * i) + 0),
|
745 |
|
|
TXCOMINIT => '0',
|
746 |
|
|
TXCOMSAS => '0',
|
747 |
|
|
TXCOMWAKE => '0',
|
748 |
|
|
TXDATA => v6pcie29((32 * i) + 31 downto (32 * i) + 0),
|
749 |
|
|
TXDEEMPH => TxDeemph,
|
750 |
|
|
TXDETECTRX => TxDetectRx,
|
751 |
|
|
TXDIFFCTRL => "1111",
|
752 |
|
|
TXDLYALIGNDISABLE => TXDLYALIGNDISABLE(i),
|
753 |
|
|
TXDLYALIGNRESET => TXDLYALIGNRESET(i),
|
754 |
|
|
TXELECIDLE => GTX_TxElecIdle(i),
|
755 |
|
|
TXENC8B10BUSE => '1',
|
756 |
|
|
TXENPMAPHASEALIGN => TXENPMAPHASEALIGN(i),
|
757 |
|
|
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
|
758 |
|
|
TXGEARBOXREADY => open,
|
759 |
|
|
TXHEADER => tied_to_ground_vec_i(2 downto 0),
|
760 |
|
|
TXINHIBIT => '0',
|
761 |
|
|
TXKERR => open,
|
762 |
|
|
TXMARGIN => v6pcie30,
|
763 |
|
|
TXN => GTX_TXN(i),
|
764 |
|
|
TXOUTCLK => TXOCLK(i),
|
765 |
|
|
TXOUTCLKPCS => open,
|
766 |
|
|
TXP => GTX_TXP(i),
|
767 |
|
|
TXPDOWNASYNCH => TXPdownAsynch,
|
768 |
|
|
TXPLLLKDET => open,
|
769 |
|
|
TXPLLLKDETEN => '0',
|
770 |
|
|
TXPLLPOWERDOWN => '0',
|
771 |
|
|
TXPLLREFSELDY => "000",
|
772 |
|
|
TXPMASETPHASE => TXPMASETPHASE(i),
|
773 |
|
|
TXPOLARITY => '0',
|
774 |
|
|
TXPOSTEMPHASIS => tied_to_ground_vec_i(4 downto 0),
|
775 |
|
|
TXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
|
776 |
|
|
TXPRBSFORCEERR => tied_to_ground_i,
|
777 |
|
|
TXPREEMPHASIS => tied_to_ground_vec_i(3 downto 0),
|
778 |
|
|
TXRATE => v6pcie24,
|
779 |
|
|
TXRESET => v6pcie25(i),
|
780 |
|
|
TXRESETDONE => TXRESETDONE(i),
|
781 |
|
|
TXRUNDISP => open,
|
782 |
|
|
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
|
783 |
|
|
TXSTARTSEQ => tied_to_ground_i,
|
784 |
|
|
TXSWING => TxSwing,
|
785 |
|
|
TXUSRCLK => PCLK,
|
786 |
|
|
TXUSRCLK2 => PCLK,
|
787 |
|
|
USRCODEERR => tied_to_ground_i,
|
788 |
|
|
IGNORESIGDET => tied_to_ground_i,
|
789 |
|
|
PERFCLKRX => tied_to_ground_i,
|
790 |
|
|
PERFCLKTX => tied_to_ground_i,
|
791 |
|
|
RXDLYALIGNMONITOR => open,
|
792 |
|
|
RXDLYALIGNOVERRIDE => '0',
|
793 |
|
|
RXDLYALIGNRESET => tied_to_ground_i,
|
794 |
|
|
RXDLYALIGNSWPPRECURB => '1',
|
795 |
|
|
RXDLYALIGNUPDSW => '0',
|
796 |
|
|
TXDLYALIGNMONITOR => open,
|
797 |
|
|
TXDLYALIGNOVERRIDE => '0',
|
798 |
|
|
TXDLYALIGNUPDSW => '0',
|
799 |
|
|
TXDLYALIGNMONENB => '1',
|
800 |
|
|
TXRATEDONE => TXRATEDONE(i)
|
801 |
|
|
);
|
802 |
|
|
|
803 |
|
|
end generate;
|
804 |
|
|
|
805 |
|
|
|
806 |
|
|
end v6_pcie;
|
807 |
|
|
|