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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_gtx_v6.v
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// Version : 1.7
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//-- Description: GTX module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_gtx_v6 #
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(
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parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2
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parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
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parameter PL_FAST_TRAIN = "FALSE"
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)
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(
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// Pipe Per-Link Signals
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input wire pipe_tx_rcvr_det ,
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input wire pipe_tx_reset ,
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input wire pipe_tx_rate ,
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input wire pipe_tx_deemph ,
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input wire [2:0] pipe_tx_margin ,
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input wire pipe_tx_swing ,
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// Pipe Per-Lane Signals - Lane 0
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output wire [ 1:0] pipe_rx0_char_is_k ,
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output wire [15:0] pipe_rx0_data ,
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output wire pipe_rx0_valid ,
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output wire pipe_rx0_chanisaligned ,
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output wire [ 2:0] pipe_rx0_status ,
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output wire pipe_rx0_phy_status ,
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output wire pipe_rx0_elec_idle ,
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input wire pipe_rx0_polarity ,
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input wire pipe_tx0_compliance ,
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input wire [ 1:0] pipe_tx0_char_is_k ,
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input wire [15:0] pipe_tx0_data ,
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input wire pipe_tx0_elec_idle ,
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input wire [ 1:0] pipe_tx0_powerdown ,
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// Pipe Per-Lane Signals - Lane 1
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output wire [ 1:0] pipe_rx1_char_is_k ,
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output wire [15:0] pipe_rx1_data ,
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output wire pipe_rx1_valid ,
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output wire pipe_rx1_chanisaligned ,
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output wire [ 2:0] pipe_rx1_status ,
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output wire pipe_rx1_phy_status ,
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output wire pipe_rx1_elec_idle ,
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input wire pipe_rx1_polarity ,
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input wire pipe_tx1_compliance ,
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input wire [ 1:0] pipe_tx1_char_is_k ,
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input wire [15:0] pipe_tx1_data ,
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input wire pipe_tx1_elec_idle ,
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input wire [ 1:0] pipe_tx1_powerdown ,
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// Pipe Per-Lane Signals - Lane 2
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output wire [ 1:0] pipe_rx2_char_is_k ,
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output wire [15:0] pipe_rx2_data ,
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output wire pipe_rx2_valid ,
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output wire pipe_rx2_chanisaligned ,
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output wire [ 2:0] pipe_rx2_status ,
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output wire pipe_rx2_phy_status ,
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output wire pipe_rx2_elec_idle ,
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input wire pipe_rx2_polarity ,
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input wire pipe_tx2_compliance ,
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input wire [ 1:0] pipe_tx2_char_is_k ,
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input wire [15:0] pipe_tx2_data ,
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input wire pipe_tx2_elec_idle ,
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input wire [ 1:0] pipe_tx2_powerdown ,
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// Pipe Per-Lane Signals - Lane 3
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output wire [ 1:0] pipe_rx3_char_is_k ,
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output wire [15:0] pipe_rx3_data ,
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output wire pipe_rx3_valid ,
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output wire pipe_rx3_chanisaligned ,
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output wire [ 2:0] pipe_rx3_status ,
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output wire pipe_rx3_phy_status ,
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output wire pipe_rx3_elec_idle ,
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input wire pipe_rx3_polarity ,
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input wire pipe_tx3_compliance ,
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input wire [ 1:0] pipe_tx3_char_is_k ,
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input wire [15:0] pipe_tx3_data ,
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input wire pipe_tx3_elec_idle ,
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input wire [ 1:0] pipe_tx3_powerdown ,
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// Pipe Per-Lane Signals - Lane 4
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output wire [ 1:0] pipe_rx4_char_is_k ,
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output wire [15:0] pipe_rx4_data ,
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output wire pipe_rx4_valid ,
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output wire pipe_rx4_chanisaligned ,
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output wire [ 2:0] pipe_rx4_status ,
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output wire pipe_rx4_phy_status ,
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output wire pipe_rx4_elec_idle ,
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input wire pipe_rx4_polarity ,
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input wire pipe_tx4_compliance ,
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input wire [ 1:0] pipe_tx4_char_is_k ,
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input wire [15:0] pipe_tx4_data ,
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input wire pipe_tx4_elec_idle ,
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input wire [ 1:0] pipe_tx4_powerdown ,
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// Pipe Per-Lane Signals - Lane 5
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output wire [ 1:0] pipe_rx5_char_is_k ,
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output wire [15:0] pipe_rx5_data ,
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output wire pipe_rx5_valid ,
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output wire pipe_rx5_chanisaligned ,
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output wire [ 2:0] pipe_rx5_status ,
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output wire pipe_rx5_phy_status ,
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output wire pipe_rx5_elec_idle ,
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input wire pipe_rx5_polarity ,
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input wire pipe_tx5_compliance ,
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input wire [ 1:0] pipe_tx5_char_is_k ,
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input wire [15:0] pipe_tx5_data ,
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input wire pipe_tx5_elec_idle ,
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input wire [ 1:0] pipe_tx5_powerdown ,
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// Pipe Per-Lane Signals - Lane 6
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output wire [ 1:0] pipe_rx6_char_is_k ,
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output wire [15:0] pipe_rx6_data ,
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output wire pipe_rx6_valid ,
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output wire pipe_rx6_chanisaligned ,
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output wire [ 2:0] pipe_rx6_status ,
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output wire pipe_rx6_phy_status ,
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output wire pipe_rx6_elec_idle ,
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input wire pipe_rx6_polarity ,
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input wire pipe_tx6_compliance ,
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input wire [ 1:0] pipe_tx6_char_is_k ,
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input wire [15:0] pipe_tx6_data ,
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input wire pipe_tx6_elec_idle ,
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input wire [ 1:0] pipe_tx6_powerdown ,
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// Pipe Per-Lane Signals - Lane 7
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output wire [ 1:0] pipe_rx7_char_is_k ,
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output wire [15:0] pipe_rx7_data ,
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output wire pipe_rx7_valid ,
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output wire pipe_rx7_chanisaligned ,
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output wire [ 2:0] pipe_rx7_status ,
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output wire pipe_rx7_phy_status ,
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output wire pipe_rx7_elec_idle ,
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input wire pipe_rx7_polarity ,
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input wire pipe_tx7_compliance ,
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input wire [ 1:0] pipe_tx7_char_is_k ,
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input wire [15:0] pipe_tx7_data ,
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input wire pipe_tx7_elec_idle ,
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input wire [ 1:0] pipe_tx7_powerdown ,
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// PCI Express signals
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output wire [ (NO_OF_LANES-1):0] pci_exp_txn ,
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output wire [ (NO_OF_LANES-1):0] pci_exp_txp ,
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input wire [ (NO_OF_LANES-1):0] pci_exp_rxn ,
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input wire [ (NO_OF_LANES-1):0] pci_exp_rxp ,
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// Non PIPE signals
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire pipe_clk ,
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input wire drp_clk ,
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input wire clock_locked ,
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output wire gt_pll_lock ,
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input wire [ 5:0] pl_ltssm_state ,
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output reg phy_rdy_n ,
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output wire TxOutClk
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);
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parameter TCQ = 1; // clock to out delay model
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wire [ 7:0] gt_rx_phy_status_wire ;
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wire [ 7:0] gt_rxchanisaligned_wire ;
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wire [127:0] gt_rx_data_k_wire ;
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wire [127:0] gt_rx_data_wire ;
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wire [ 7:0] gt_rx_elec_idle_wire ;
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wire [ 23:0] gt_rx_status_wire ;
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wire [ 7:0] gt_rx_valid_wire ;
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wire [ 7:0] gt_rx_polarity ;
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wire [ 15:0] gt_power_down ;
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wire [ 7:0] gt_tx_char_disp_mode ;
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wire [ 15:0] gt_tx_data_k ;
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wire [127:0] gt_tx_data ;
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wire gt_tx_detect_rx_loopback ;
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wire [ 7:0] gt_tx_elec_idle ;
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wire [ 7:0] gt_rx_elec_idle_reset ;
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wire [NO_OF_LANES-1:0] plllkdet;
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wire RxResetDone;
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reg local_pcs_reset;
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reg local_pcs_reset_done;
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reg [3:0] cnt_local_pcs_reset;
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reg [4:0] phy_rdy_pre_cnt;
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reg [5:0] pl_ltssm_state_q;
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wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
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wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
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wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
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wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
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gtx_wrapper_v6 #(
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.NO_OF_LANES(NO_OF_LANES),
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.REF_CLK_FREQ(REF_CLK_FREQ),
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.PL_FAST_TRAIN(PL_FAST_TRAIN)
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)
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gtx_v6_i (
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// TX
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.TX(pci_exp_txp[((NO_OF_LANES)-1):0]),
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.TX_(pci_exp_txn[((NO_OF_LANES)-1):0]),
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.TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]),
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.TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]),
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.TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]),
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.TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]),
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// RX
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.RX(pci_exp_rxp[((NO_OF_LANES)-1):0]),
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.RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]),
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.RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]),
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.RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]),
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.RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]),
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.RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]),
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.RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]),
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.RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]),
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// other
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.GTRefClkout(),
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.plm_in_l0(plm_in_l0),
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.plm_in_rl(plm_in_rl),
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.plm_in_dt(plm_in_dt),
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.plm_in_rs(plm_in_rs),
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.RxPLLLkDet(plllkdet),
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.ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]),
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.TxDetectRx(gt_tx_detect_rx_loopback),
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.PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]),
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.TXPdownAsynch(~clock_locked),
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.PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]),
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.Rate(pipe_tx_rate),
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.Reset_n(clock_locked),
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.GTReset_n(sys_rst_n),
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.PCLK(pipe_clk),
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.REFCLK(sys_clk),
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.DRPCLK(drp_clk),
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.TxDeemph(pipe_tx_deemph),
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.TxMargin(pipe_tx_margin[2]),
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.TxSwing(pipe_tx_swing),
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.local_pcs_reset(local_pcs_reset),
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.RxResetDone(RxResetDone),
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.SyncDone(SyncDone),
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.TxOutClk(TxOutClk)
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);
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assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
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assign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
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assign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
|
306 |
|
|
assign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
|
307 |
|
|
assign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
|
308 |
|
|
assign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
|
309 |
|
|
assign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
|
310 |
|
|
assign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
|
311 |
|
|
|
312 |
|
|
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
|
313 |
|
|
assign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
|
314 |
|
|
assign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
|
315 |
|
|
assign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
|
316 |
|
|
assign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
|
317 |
|
|
assign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
|
318 |
|
|
assign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
|
319 |
|
|
assign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
|
320 |
|
|
|
321 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
322 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
323 |
|
|
|
324 |
|
|
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
|
325 |
|
|
assign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ;
|
326 |
|
|
assign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
|
327 |
|
|
assign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ;
|
328 |
|
|
assign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
|
329 |
|
|
assign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ;
|
330 |
|
|
assign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
|
331 |
|
|
assign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ;
|
332 |
|
|
|
333 |
|
|
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
|
334 |
|
|
assign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ;
|
335 |
|
|
assign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
|
336 |
|
|
assign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ;
|
337 |
|
|
assign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
|
338 |
|
|
assign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ;
|
339 |
|
|
assign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
|
340 |
|
|
assign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ;
|
341 |
|
|
|
342 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
343 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
344 |
|
|
|
345 |
|
|
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
|
346 |
|
|
assign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
|
347 |
|
|
assign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
|
348 |
|
|
assign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
|
349 |
|
|
assign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
|
350 |
|
|
assign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
|
351 |
|
|
assign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
|
352 |
|
|
assign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
|
353 |
|
|
|
354 |
|
|
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
|
355 |
|
|
assign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
|
356 |
|
|
assign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
|
357 |
|
|
assign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
|
358 |
|
|
assign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
|
359 |
|
|
assign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
|
360 |
|
|
assign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
|
361 |
|
|
assign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
|
362 |
|
|
|
363 |
|
|
assign pipe_rx0_valid = gt_rx_valid_wire[0];
|
364 |
|
|
assign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
|
365 |
|
|
assign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
|
366 |
|
|
assign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
|
367 |
|
|
assign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
|
368 |
|
|
assign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
|
369 |
|
|
assign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
|
370 |
|
|
assign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
|
371 |
|
|
|
372 |
|
|
assign gt_rx_polarity[0] = pipe_rx0_polarity;
|
373 |
|
|
assign gt_rx_polarity[1] = pipe_rx1_polarity;
|
374 |
|
|
assign gt_rx_polarity[2] = pipe_rx2_polarity;
|
375 |
|
|
assign gt_rx_polarity[3] = pipe_rx3_polarity;
|
376 |
|
|
assign gt_rx_polarity[4] = pipe_rx4_polarity;
|
377 |
|
|
assign gt_rx_polarity[5] = pipe_rx5_polarity;
|
378 |
|
|
assign gt_rx_polarity[6] = pipe_rx6_polarity;
|
379 |
|
|
assign gt_rx_polarity[7] = pipe_rx7_polarity;
|
380 |
|
|
|
381 |
|
|
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
|
382 |
|
|
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
|
383 |
|
|
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
|
384 |
|
|
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
|
385 |
|
|
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
|
386 |
|
|
assign gt_power_down[11:10] = pipe_tx5_powerdown;
|
387 |
|
|
assign gt_power_down[13:12] = pipe_tx6_powerdown;
|
388 |
|
|
assign gt_power_down[15:14] = pipe_tx7_powerdown;
|
389 |
|
|
|
390 |
|
|
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
|
391 |
|
|
pipe_tx6_compliance,
|
392 |
|
|
pipe_tx5_compliance,
|
393 |
|
|
pipe_tx4_compliance,
|
394 |
|
|
pipe_tx3_compliance,
|
395 |
|
|
pipe_tx2_compliance,
|
396 |
|
|
pipe_tx1_compliance,
|
397 |
|
|
pipe_tx0_compliance};
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
assign gt_tx_data_k = {pipe_tx7_char_is_k,
|
401 |
|
|
pipe_tx6_char_is_k,
|
402 |
|
|
pipe_tx5_char_is_k,
|
403 |
|
|
pipe_tx4_char_is_k,
|
404 |
|
|
pipe_tx3_char_is_k,
|
405 |
|
|
pipe_tx2_char_is_k,
|
406 |
|
|
pipe_tx1_char_is_k,
|
407 |
|
|
pipe_tx0_char_is_k};
|
408 |
|
|
|
409 |
|
|
assign gt_tx_data = {pipe_tx7_data,
|
410 |
|
|
pipe_tx6_data,
|
411 |
|
|
pipe_tx5_data,
|
412 |
|
|
pipe_tx4_data,
|
413 |
|
|
pipe_tx3_data,
|
414 |
|
|
pipe_tx2_data,
|
415 |
|
|
pipe_tx1_data,
|
416 |
|
|
pipe_tx0_data};
|
417 |
|
|
|
418 |
|
|
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
|
419 |
|
|
|
420 |
|
|
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
|
421 |
|
|
pipe_tx6_elec_idle,
|
422 |
|
|
pipe_tx5_elec_idle,
|
423 |
|
|
pipe_tx4_elec_idle,
|
424 |
|
|
pipe_tx3_elec_idle,
|
425 |
|
|
pipe_tx2_elec_idle,
|
426 |
|
|
pipe_tx1_elec_idle,
|
427 |
|
|
pipe_tx0_elec_idle};
|
428 |
|
|
|
429 |
|
|
assign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4];
|
430 |
|
|
|
431 |
|
|
// Asserted after all workarounds have completed.
|
432 |
|
|
|
433 |
|
|
always @(posedge pipe_clk or negedge clock_locked) begin
|
434 |
|
|
|
435 |
|
|
if (!clock_locked) begin
|
436 |
|
|
|
437 |
|
|
phy_rdy_n <= #TCQ 1'b1;
|
438 |
|
|
|
439 |
|
|
end else begin
|
440 |
|
|
|
441 |
|
|
if (~&plllkdet[NO_OF_LANES-1:0])
|
442 |
|
|
phy_rdy_n <= #TCQ 1'b1;
|
443 |
|
|
else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone)
|
444 |
|
|
phy_rdy_n <= #TCQ 1'b0;
|
445 |
|
|
|
446 |
|
|
end
|
447 |
|
|
|
448 |
|
|
end
|
449 |
|
|
|
450 |
|
|
// Handle the warm reset case, where sys_rst_n is asseted when
|
451 |
|
|
// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
|
452 |
|
|
// before gt_pll_lock is de-asserted so that synnchronous
|
453 |
|
|
// logic see reset de-asset before clock is lost.
|
454 |
|
|
|
455 |
|
|
always @(posedge pipe_clk or negedge clock_locked) begin
|
456 |
|
|
|
457 |
|
|
if (!clock_locked) begin
|
458 |
|
|
|
459 |
|
|
phy_rdy_pre_cnt <= #TCQ 5'b11111;
|
460 |
|
|
|
461 |
|
|
end else begin
|
462 |
|
|
|
463 |
|
|
if (gt_pll_lock && phy_rdy_n)
|
464 |
|
|
phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1;
|
465 |
|
|
|
466 |
|
|
end
|
467 |
|
|
|
468 |
|
|
end
|
469 |
|
|
|
470 |
|
|
always @(posedge pipe_clk or negedge clock_locked) begin
|
471 |
|
|
|
472 |
|
|
if (!clock_locked) begin
|
473 |
|
|
|
474 |
|
|
cnt_local_pcs_reset <= #TCQ 4'hF;
|
475 |
|
|
local_pcs_reset <= #TCQ 1'b0;
|
476 |
|
|
local_pcs_reset_done <= #TCQ 1'b0;
|
477 |
|
|
|
478 |
|
|
end else begin
|
479 |
|
|
|
480 |
|
|
if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF))
|
481 |
|
|
local_pcs_reset <= #TCQ 1'b1;
|
482 |
|
|
else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin
|
483 |
|
|
local_pcs_reset <= #TCQ 1'b1;
|
484 |
|
|
cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1;
|
485 |
|
|
end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin
|
486 |
|
|
local_pcs_reset <= #TCQ 1'b0;
|
487 |
|
|
local_pcs_reset_done <= #TCQ 1'b1;
|
488 |
|
|
end
|
489 |
|
|
|
490 |
|
|
end
|
491 |
|
|
|
492 |
|
|
end
|
493 |
|
|
|
494 |
|
|
always @(posedge pipe_clk or negedge clock_locked) begin
|
495 |
|
|
|
496 |
|
|
if (!clock_locked)
|
497 |
|
|
pl_ltssm_state_q <= #TCQ 6'b0;
|
498 |
|
|
else
|
499 |
|
|
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
|
500 |
|
|
|
501 |
|
|
end
|
502 |
|
|
|
503 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
504 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
505 |
|
|
|
506 |
|
|
endmodule
|