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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : v6_pcie_v1_7_x1.v
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// Version : 1.7
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//--
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//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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(* CORE_GENERATION_INFO = "v6_pcie_v1_7_x1,v6_pcie_v1_7,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=01,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,USER_CLK_FREQ=2,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=29,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=308,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=308,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,PIPE_PIPELINE_STAGES=0,REVISION_ID=06,VC_CAP_ON=FALSE}" *)
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module v6_pcie_v1_7_x1 # (
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parameter ALLOW_X8_GEN2 = "FALSE",
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parameter BAR0 = 32'hFFFF0000,
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parameter BAR1 = 32'hFFF00000,
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parameter BAR2 = 32'hFFFFF000,
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parameter BAR3 = 32'h00000000,
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parameter BAR4 = 32'h00000000,
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parameter BAR5 = 32'h00000000,
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parameter CARDBUS_CIS_POINTER = 32'h00000000,
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parameter CLASS_CODE = 24'h050000,
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parameter CMD_INTX_IMPLEMENTED = "TRUE",
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parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
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parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
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parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 7,
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parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,
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parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
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parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
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parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
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parameter DEVICE_ID = 16'h6021,
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parameter DISABLE_LANE_REVERSAL = "TRUE",
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parameter DISABLE_SCRAMBLING = "FALSE",
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parameter DSN_BASE_PTR = 12'h100,
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parameter DSN_CAP_NEXTPTR = 12'h000,
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parameter DSN_CAP_ON = "TRUE",
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parameter ENABLE_MSG_ROUTE = 11'h00000000000,
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parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
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parameter EXPANSION_ROM = 32'h00000000,
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parameter EXT_CFG_CAP_PTR = 6'h3F,
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parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,
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parameter HEADER_TYPE = 8'h00,
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parameter INTERRUPT_PIN = 8'h1,
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parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
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parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h2,
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parameter LINK_CAP_MAX_LINK_WIDTH = 6'h01,
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parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
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parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
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parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
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parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
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parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",
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parameter LL_ACK_TIMEOUT = 15'h0000,
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parameter LL_ACK_TIMEOUT_EN = "FALSE",
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parameter LL_ACK_TIMEOUT_FUNC = 0,
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parameter LL_REPLAY_TIMEOUT = 15'h0026,
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parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
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parameter LL_REPLAY_TIMEOUT_FUNC = 1,
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parameter LTSSM_MAX_LINK_WIDTH = 6'h01,
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parameter MSI_CAP_MULTIMSGCAP = 0,
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parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
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parameter MSI_CAP_ON = "TRUE",
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parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
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parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
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parameter MSIX_CAP_ON = "FALSE",
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parameter MSIX_CAP_PBA_BIR = 0,
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parameter MSIX_CAP_PBA_OFFSET = 29'h0,
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parameter MSIX_CAP_TABLE_BIR = 0,
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parameter MSIX_CAP_TABLE_OFFSET = 29'h0,
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parameter MSIX_CAP_TABLE_SIZE = 11'h000,
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parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,
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parameter PCIE_CAP_INT_MSG_NUM = 5'h1,
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parameter PCIE_CAP_NEXTPTR = 8'h00,
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parameter PCIE_DRP_ENABLE = "FALSE",
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parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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parameter PM_CAP_DSI = "FALSE",
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parameter PM_CAP_D1SUPPORT = "FALSE",
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parameter PM_CAP_D2SUPPORT = "FALSE",
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parameter PM_CAP_NEXTPTR = 8'h48,
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parameter PM_CAP_PMESUPPORT = 5'h0F,
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parameter PM_CSR_NOSOFTRST = "TRUE",
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parameter PM_DATA_SCALE0 = 2'h0,
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parameter PM_DATA_SCALE1 = 2'h0,
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parameter PM_DATA_SCALE2 = 2'h0,
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parameter PM_DATA_SCALE3 = 2'h0,
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parameter PM_DATA_SCALE4 = 2'h0,
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parameter PM_DATA_SCALE5 = 2'h0,
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parameter PM_DATA_SCALE6 = 2'h0,
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parameter PM_DATA_SCALE7 = 2'h0,
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parameter PM_DATA0 = 8'h00,
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parameter PM_DATA1 = 8'h00,
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parameter PM_DATA2 = 8'h00,
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parameter PM_DATA3 = 8'h00,
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parameter PM_DATA4 = 8'h00,
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parameter PM_DATA5 = 8'h00,
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parameter PM_DATA6 = 8'h00,
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parameter PM_DATA7 = 8'h00,
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parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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parameter REVISION_ID = 8'h06,
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parameter SPARE_BIT0 = 0,
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parameter SUBSYSTEM_ID = 16'hABB3,
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parameter SUBSYSTEM_VENDOR_ID = 16'h0084,
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parameter TL_RX_RAM_RADDR_LATENCY = 0,
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parameter TL_RX_RAM_RDATA_LATENCY = 2,
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parameter TL_RX_RAM_WRITE_LATENCY = 0,
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parameter TL_TX_RAM_RADDR_LATENCY = 0,
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parameter TL_TX_RAM_RDATA_LATENCY = 2,
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parameter TL_TX_RAM_WRITE_LATENCY = 0,
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parameter UPCONFIG_CAPABLE = "TRUE",
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parameter USER_CLK_FREQ = 2,
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parameter VC_BASE_PTR = 12'h0,
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parameter VC_CAP_NEXTPTR = 12'h000,
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parameter VC_CAP_ON = "FALSE",
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parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
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parameter VC0_CPL_INFINITE = "TRUE",
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parameter VC0_RX_RAM_LIMIT = 13'h7FF,
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parameter VC0_TOTAL_CREDITS_CD = 308,
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parameter VC0_TOTAL_CREDITS_CH = 36,
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parameter VC0_TOTAL_CREDITS_NPH = 12,
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parameter VC0_TOTAL_CREDITS_PD = 308,
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parameter VC0_TOTAL_CREDITS_PH = 32,
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parameter VC0_TX_LASTPACKET = 29,
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parameter VENDOR_ID = 16'h10EE,
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parameter VSEC_BASE_PTR = 12'h0,
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parameter VSEC_CAP_NEXTPTR = 12'h000,
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parameter VSEC_CAP_ON = "FALSE",
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parameter AER_BASE_PTR = 12'h128,
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parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
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parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
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parameter AER_CAP_ID = 16'h0001,
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parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
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parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
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parameter AER_CAP_NEXTPTR = 12'h160,
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parameter AER_CAP_ON = "FALSE",
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parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
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parameter AER_CAP_VERSION = 4'h1,
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parameter CAPABILITIES_PTR = 8'h40,
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parameter CRM_MODULE_RSTS = 7'h00,
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parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
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parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
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parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
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parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
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parameter DEV_CAP_RSVD_14_12 = 0,
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parameter DEV_CAP_RSVD_17_16 = 0,
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parameter DEV_CAP_RSVD_31_29 = 0,
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parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
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parameter DISABLE_ASPM_L1_TIMER = "FALSE",
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parameter DISABLE_BAR_FILTERING = "FALSE",
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parameter DISABLE_ID_CHECK = "FALSE",
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parameter DISABLE_RX_TC_FILTER = "FALSE",
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parameter DNSTREAM_LINK_NUM = 8'h00,
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parameter DSN_CAP_ID = 16'h0003,
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parameter DSN_CAP_VERSION = 4'h1,
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parameter ENTER_RVRY_EI_L0 = "TRUE",
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parameter INFER_EI = 5'h0c,
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parameter IS_SWITCH = "FALSE",
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parameter LAST_CONFIG_DWORD = 10'h3FF,
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parameter LINK_CAP_ASPM_SUPPORT = 1,
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parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
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parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
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parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
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parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
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parameter LINK_CAP_RSVD_23_22 = 0,
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parameter LINK_CONTROL_RCB = 0,
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parameter MSI_BASE_PTR = 8'h48,
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parameter MSI_CAP_ID = 8'h05,
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parameter MSI_CAP_NEXTPTR = 8'h60,
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parameter MSIX_BASE_PTR = 8'h9c,
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parameter MSIX_CAP_ID = 8'h11,
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parameter MSIX_CAP_NEXTPTR = 8'h00,
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parameter N_FTS_COMCLK_GEN1 = 255,
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parameter N_FTS_COMCLK_GEN2 = 254,
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parameter N_FTS_GEN1 = 255,
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parameter N_FTS_GEN2 = 255,
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parameter PCIE_BASE_PTR = 8'h60,
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parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
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parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
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parameter PCIE_CAP_ON = "TRUE",
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parameter PCIE_CAP_RSVD_15_14 = 0,
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parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
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parameter PCIE_REVISION = 2,
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parameter PGL0_LANE = 0,
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parameter PGL1_LANE = 1,
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parameter PGL2_LANE = 2,
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parameter PGL3_LANE = 3,
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parameter PGL4_LANE = 4,
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parameter PGL5_LANE = 5,
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parameter PGL6_LANE = 6,
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parameter PGL7_LANE = 7,
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parameter PL_AUTO_CONFIG = 0,
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parameter PL_FAST_TRAIN = "FALSE",
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parameter PM_BASE_PTR = 8'h40,
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parameter PM_CAP_AUXCURRENT = 0,
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parameter PM_CAP_ID = 8'h01,
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parameter PM_CAP_ON = "TRUE",
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parameter PM_CAP_PME_CLOCK = "FALSE",
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parameter PM_CAP_RSVD_04 = 0,
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parameter PM_CAP_VERSION = 3,
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parameter PM_CSR_BPCCEN = "FALSE",
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parameter PM_CSR_B2B3 = "FALSE",
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parameter RECRC_CHK = 0,
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parameter RECRC_CHK_TRIM = "FALSE",
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parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
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parameter SELECT_DLL_IF = "FALSE",
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parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
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parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
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|
|
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
|
290 |
|
|
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
|
291 |
|
|
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
|
292 |
|
|
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
|
293 |
|
|
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
|
294 |
|
|
parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
|
295 |
|
|
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
|
296 |
|
|
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
|
297 |
|
|
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
|
298 |
|
|
parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
|
299 |
|
|
parameter SPARE_BIT1 = 0,
|
300 |
|
|
parameter SPARE_BIT2 = 0,
|
301 |
|
|
parameter SPARE_BIT3 = 0,
|
302 |
|
|
parameter SPARE_BIT4 = 0,
|
303 |
|
|
parameter SPARE_BIT5 = 0,
|
304 |
|
|
parameter SPARE_BIT6 = 0,
|
305 |
|
|
parameter SPARE_BIT7 = 0,
|
306 |
|
|
parameter SPARE_BIT8 = 0,
|
307 |
|
|
parameter SPARE_BYTE0 = 8'h00,
|
308 |
|
|
parameter SPARE_BYTE1 = 8'h00,
|
309 |
|
|
parameter SPARE_BYTE2 = 8'h00,
|
310 |
|
|
parameter SPARE_BYTE3 = 8'h00,
|
311 |
|
|
parameter SPARE_WORD0 = 32'h00000000,
|
312 |
|
|
parameter SPARE_WORD1 = 32'h00000000,
|
313 |
|
|
parameter SPARE_WORD2 = 32'h00000000,
|
314 |
|
|
parameter SPARE_WORD3 = 32'h00000000,
|
315 |
|
|
|
316 |
|
|
parameter TL_RBYPASS = "FALSE",
|
317 |
|
|
parameter TL_TFC_DISABLE = "FALSE",
|
318 |
|
|
parameter TL_TX_CHECKS_DISABLE = "FALSE",
|
319 |
|
|
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
|
320 |
|
|
parameter UPSTREAM_FACING = "TRUE",
|
321 |
|
|
parameter UR_INV_REQ = "TRUE",
|
322 |
|
|
|
323 |
|
|
parameter VC_CAP_ID = 16'h0002,
|
324 |
|
|
parameter VC_CAP_VERSION = 4'h1,
|
325 |
|
|
parameter VSEC_CAP_HDR_ID = 16'h1234,
|
326 |
|
|
parameter VSEC_CAP_HDR_LENGTH = 12'h018,
|
327 |
|
|
parameter VSEC_CAP_HDR_REVISION = 4'h1,
|
328 |
|
|
parameter VSEC_CAP_ID = 16'h000b,
|
329 |
|
|
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
|
330 |
|
|
parameter VSEC_CAP_VERSION = 4'h1
|
331 |
|
|
)
|
332 |
|
|
(
|
333 |
|
|
//-------------------------------------------------------
|
334 |
|
|
// 1. PCI Express (pci_exp) Interface
|
335 |
|
|
//-------------------------------------------------------
|
336 |
|
|
|
337 |
|
|
// Tx
|
338 |
|
|
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,
|
339 |
|
|
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,
|
340 |
|
|
|
341 |
|
|
// Rx
|
342 |
|
|
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,
|
343 |
|
|
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,
|
344 |
|
|
|
345 |
|
|
//-------------------------------------------------------
|
346 |
|
|
// 2. Transaction (TRN) Interface
|
347 |
|
|
//-------------------------------------------------------
|
348 |
|
|
|
349 |
|
|
// Common
|
350 |
|
|
output trn_clk,
|
351 |
|
|
output trn_reset_n,
|
352 |
|
|
output trn_lnk_up_n,
|
353 |
|
|
|
354 |
|
|
// Tx
|
355 |
|
|
output [5:0] trn_tbuf_av,
|
356 |
|
|
output trn_tcfg_req_n,
|
357 |
|
|
output trn_terr_drop_n,
|
358 |
|
|
output trn_tdst_rdy_n,
|
359 |
|
|
input [63:0] trn_td,
|
360 |
|
|
input trn_trem_n,
|
361 |
|
|
input trn_tsof_n,
|
362 |
|
|
input trn_teof_n,
|
363 |
|
|
input trn_tsrc_rdy_n,
|
364 |
|
|
input trn_tsrc_dsc_n,
|
365 |
|
|
input trn_terrfwd_n,
|
366 |
|
|
input trn_tcfg_gnt_n,
|
367 |
|
|
input trn_tstr_n,
|
368 |
|
|
|
369 |
|
|
// Rx
|
370 |
|
|
output [63:0] trn_rd,
|
371 |
|
|
output trn_rrem_n,
|
372 |
|
|
output trn_rsof_n,
|
373 |
|
|
output trn_reof_n,
|
374 |
|
|
output trn_rsrc_rdy_n,
|
375 |
|
|
output trn_rsrc_dsc_n,
|
376 |
|
|
output trn_rerrfwd_n,
|
377 |
|
|
output [6:0] trn_rbar_hit_n,
|
378 |
|
|
input trn_rdst_rdy_n,
|
379 |
|
|
input trn_rnp_ok_n,
|
380 |
|
|
|
381 |
|
|
// Flow Control
|
382 |
|
|
output [11:0] trn_fc_cpld,
|
383 |
|
|
output [7:0] trn_fc_cplh,
|
384 |
|
|
output [11:0] trn_fc_npd,
|
385 |
|
|
output [7:0] trn_fc_nph,
|
386 |
|
|
output [11:0] trn_fc_pd,
|
387 |
|
|
output [7:0] trn_fc_ph,
|
388 |
|
|
input [2:0] trn_fc_sel,
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
//-------------------------------------------------------
|
392 |
|
|
// 3. Configuration (CFG) Interface
|
393 |
|
|
//-------------------------------------------------------
|
394 |
|
|
|
395 |
|
|
output [31:0] cfg_do,
|
396 |
|
|
output cfg_rd_wr_done_n,
|
397 |
|
|
input [31:0] cfg_di,
|
398 |
|
|
input [3:0] cfg_byte_en_n,
|
399 |
|
|
input [9:0] cfg_dwaddr,
|
400 |
|
|
input cfg_wr_en_n,
|
401 |
|
|
input cfg_rd_en_n,
|
402 |
|
|
|
403 |
|
|
input cfg_err_cor_n,
|
404 |
|
|
input cfg_err_ur_n,
|
405 |
|
|
input cfg_err_ecrc_n,
|
406 |
|
|
input cfg_err_cpl_timeout_n,
|
407 |
|
|
input cfg_err_cpl_abort_n,
|
408 |
|
|
input cfg_err_cpl_unexpect_n,
|
409 |
|
|
input cfg_err_posted_n,
|
410 |
|
|
input cfg_err_locked_n,
|
411 |
|
|
input [47:0] cfg_err_tlp_cpl_header,
|
412 |
|
|
output cfg_err_cpl_rdy_n,
|
413 |
|
|
input cfg_interrupt_n,
|
414 |
|
|
output cfg_interrupt_rdy_n,
|
415 |
|
|
input cfg_interrupt_assert_n,
|
416 |
|
|
input [7:0] cfg_interrupt_di,
|
417 |
|
|
output [7:0] cfg_interrupt_do,
|
418 |
|
|
output [2:0] cfg_interrupt_mmenable,
|
419 |
|
|
output cfg_interrupt_msienable,
|
420 |
|
|
output cfg_interrupt_msixenable,
|
421 |
|
|
output cfg_interrupt_msixfm,
|
422 |
|
|
input cfg_turnoff_ok_n,
|
423 |
|
|
output cfg_to_turnoff_n,
|
424 |
|
|
input cfg_trn_pending_n,
|
425 |
|
|
input cfg_pm_wake_n,
|
426 |
|
|
output [7:0] cfg_bus_number,
|
427 |
|
|
output [4:0] cfg_device_number,
|
428 |
|
|
output [2:0] cfg_function_number,
|
429 |
|
|
output [15:0] cfg_status,
|
430 |
|
|
output [15:0] cfg_command,
|
431 |
|
|
output [15:0] cfg_dstatus,
|
432 |
|
|
output [15:0] cfg_dcommand,
|
433 |
|
|
output [15:0] cfg_lstatus,
|
434 |
|
|
output [15:0] cfg_lcommand,
|
435 |
|
|
output [15:0] cfg_dcommand2,
|
436 |
|
|
output [2:0] cfg_pcie_link_state_n,
|
437 |
|
|
input [63:0] cfg_dsn,
|
438 |
|
|
output cfg_pmcsr_pme_en,
|
439 |
|
|
output cfg_pmcsr_pme_status,
|
440 |
|
|
output [1:0] cfg_pmcsr_powerstate,
|
441 |
|
|
|
442 |
|
|
//-------------------------------------------------------
|
443 |
|
|
// 4. Physical Layer Control and Status (PL) Interface
|
444 |
|
|
//-------------------------------------------------------
|
445 |
|
|
|
446 |
|
|
output [2:0] pl_initial_link_width,
|
447 |
|
|
output [1:0] pl_lane_reversal_mode,
|
448 |
|
|
output pl_link_gen2_capable,
|
449 |
|
|
output pl_link_partner_gen2_supported,
|
450 |
|
|
output pl_link_upcfg_capable,
|
451 |
|
|
output [5:0] pl_ltssm_state,
|
452 |
|
|
output pl_received_hot_rst,
|
453 |
|
|
output pl_sel_link_rate,
|
454 |
|
|
output [1:0] pl_sel_link_width,
|
455 |
|
|
input pl_directed_link_auton,
|
456 |
|
|
input [1:0] pl_directed_link_change,
|
457 |
|
|
input pl_directed_link_speed,
|
458 |
|
|
input [1:0] pl_directed_link_width,
|
459 |
|
|
input pl_upstream_prefer_deemph,
|
460 |
|
|
|
461 |
|
|
//-------------------------------------------------------
|
462 |
|
|
// 5. System (SYS) Interface
|
463 |
|
|
//-------------------------------------------------------
|
464 |
|
|
|
465 |
|
|
input sys_clk,
|
466 |
|
|
input sys_reset_n
|
467 |
|
|
|
468 |
|
|
|
469 |
|
|
);
|
470 |
|
|
|
471 |
|
|
|
472 |
|
|
wire rx_func_level_reset_n;
|
473 |
|
|
wire cfg_msg_received;
|
474 |
|
|
wire cfg_msg_received_pme_to;
|
475 |
|
|
|
476 |
|
|
wire cfg_cmd_bme;
|
477 |
|
|
wire cfg_cmd_intdis;
|
478 |
|
|
wire cfg_cmd_io_en;
|
479 |
|
|
wire cfg_cmd_mem_en;
|
480 |
|
|
wire cfg_cmd_serr_en;
|
481 |
|
|
wire cfg_dev_control_aux_power_en ;
|
482 |
|
|
wire cfg_dev_control_corr_err_reporting_en ;
|
483 |
|
|
wire cfg_dev_control_enable_relaxed_order ;
|
484 |
|
|
wire cfg_dev_control_ext_tag_en ;
|
485 |
|
|
wire cfg_dev_control_fatal_err_reporting_en ;
|
486 |
|
|
wire [2:0] cfg_dev_control_maxpayload ;
|
487 |
|
|
wire [2:0] cfg_dev_control_max_read_req ;
|
488 |
|
|
wire cfg_dev_control_non_fatal_reporting_en ;
|
489 |
|
|
wire cfg_dev_control_nosnoop_en ;
|
490 |
|
|
wire cfg_dev_control_phantom_en ;
|
491 |
|
|
wire cfg_dev_control_ur_err_reporting_en ;
|
492 |
|
|
wire cfg_dev_control2_cpltimeout_dis ;
|
493 |
|
|
wire [3:0] cfg_dev_control2_cpltimeout_val ;
|
494 |
|
|
wire cfg_dev_status_corr_err_detected ;
|
495 |
|
|
wire cfg_dev_status_fatal_err_detected ;
|
496 |
|
|
wire cfg_dev_status_nonfatal_err_detected ;
|
497 |
|
|
wire cfg_dev_status_ur_detected ;
|
498 |
|
|
wire cfg_link_control_auto_bandwidth_int_en ;
|
499 |
|
|
wire cfg_link_control_bandwidth_int_en ;
|
500 |
|
|
wire cfg_link_control_hw_auto_width_dis ;
|
501 |
|
|
wire cfg_link_control_clock_pm_en ;
|
502 |
|
|
wire cfg_link_control_extended_sync ;
|
503 |
|
|
wire cfg_link_control_common_clock ;
|
504 |
|
|
wire cfg_link_control_retrain_link ;
|
505 |
|
|
wire cfg_link_control_linkdisable ;
|
506 |
|
|
wire cfg_link_control_rcb ;
|
507 |
|
|
wire [1:0] cfg_link_control_aspm_control ;
|
508 |
|
|
wire cfg_link_status_autobandwidth_status ;
|
509 |
|
|
wire cfg_link_status_bandwidth_status ;
|
510 |
|
|
wire cfg_link_status_dll_active ;
|
511 |
|
|
wire cfg_link_status_link_training ;
|
512 |
|
|
wire [3:0] cfg_link_status_negotiated_link_width ;
|
513 |
|
|
wire [1:0] cfg_link_status_current_speed ;
|
514 |
|
|
wire [15:0] cfg_msg_data;
|
515 |
|
|
|
516 |
|
|
wire sys_reset_n_d;
|
517 |
|
|
wire phy_rdy_n;
|
518 |
|
|
|
519 |
|
|
wire trn_lnk_up_n_int;
|
520 |
|
|
wire trn_lnk_up_n_int1;
|
521 |
|
|
|
522 |
|
|
wire trn_reset_n_int;
|
523 |
|
|
wire trn_reset_n_int1;
|
524 |
|
|
|
525 |
|
|
wire TxOutClk;
|
526 |
|
|
wire TxOutClk_bufg;
|
527 |
|
|
|
528 |
|
|
reg [7:0] cfg_bus_number_d;
|
529 |
|
|
reg [4:0] cfg_device_number_d;
|
530 |
|
|
reg [2:0] cfg_function_number_d;
|
531 |
|
|
|
532 |
|
|
// assigns to outputs
|
533 |
|
|
|
534 |
|
|
assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to;
|
535 |
|
|
|
536 |
|
|
assign cfg_status = {16'b0};
|
537 |
|
|
|
538 |
|
|
assign cfg_command = {5'b0,
|
539 |
|
|
cfg_cmd_intdis,
|
540 |
|
|
1'b0,
|
541 |
|
|
cfg_cmd_serr_en,
|
542 |
|
|
5'b0,
|
543 |
|
|
cfg_cmd_bme,
|
544 |
|
|
cfg_cmd_mem_en,
|
545 |
|
|
cfg_cmd_io_en};
|
546 |
|
|
|
547 |
|
|
assign cfg_dstatus = {10'h0,
|
548 |
|
|
~cfg_trn_pending_n,
|
549 |
|
|
1'b0,
|
550 |
|
|
cfg_dev_status_ur_detected,
|
551 |
|
|
cfg_dev_status_fatal_err_detected,
|
552 |
|
|
cfg_dev_status_nonfatal_err_detected,
|
553 |
|
|
cfg_dev_status_corr_err_detected};
|
554 |
|
|
|
555 |
|
|
assign cfg_dcommand = {1'b0,
|
556 |
|
|
cfg_dev_control_max_read_req,
|
557 |
|
|
cfg_dev_control_nosnoop_en,
|
558 |
|
|
cfg_dev_control_aux_power_en,
|
559 |
|
|
cfg_dev_control_phantom_en,
|
560 |
|
|
cfg_dev_control_ext_tag_en,
|
561 |
|
|
cfg_dev_control_maxpayload,
|
562 |
|
|
cfg_dev_control_enable_relaxed_order,
|
563 |
|
|
cfg_dev_control_ur_err_reporting_en,
|
564 |
|
|
cfg_dev_control_fatal_err_reporting_en,
|
565 |
|
|
cfg_dev_control_non_fatal_reporting_en,
|
566 |
|
|
cfg_dev_control_corr_err_reporting_en };
|
567 |
|
|
|
568 |
|
|
assign cfg_lstatus = {cfg_link_status_autobandwidth_status,
|
569 |
|
|
cfg_link_status_bandwidth_status,
|
570 |
|
|
cfg_link_status_dll_active,
|
571 |
|
|
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
|
572 |
|
|
cfg_link_status_link_training,
|
573 |
|
|
1'b0,
|
574 |
|
|
{2'b00, cfg_link_status_negotiated_link_width},
|
575 |
|
|
{2'b00, cfg_link_status_current_speed} };
|
576 |
|
|
|
577 |
|
|
assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en,
|
578 |
|
|
cfg_link_control_bandwidth_int_en,
|
579 |
|
|
cfg_link_control_hw_auto_width_dis,
|
580 |
|
|
cfg_link_control_clock_pm_en,
|
581 |
|
|
cfg_link_control_extended_sync,
|
582 |
|
|
cfg_link_control_common_clock,
|
583 |
|
|
cfg_link_control_retrain_link,
|
584 |
|
|
cfg_link_control_linkdisable,
|
585 |
|
|
cfg_link_control_rcb,
|
586 |
|
|
1'b0,
|
587 |
|
|
cfg_link_control_aspm_control};
|
588 |
|
|
|
589 |
|
|
assign cfg_bus_number = cfg_bus_number_d;
|
590 |
|
|
|
591 |
|
|
assign cfg_device_number = cfg_device_number_d;
|
592 |
|
|
|
593 |
|
|
assign cfg_function_number = cfg_function_number_d;
|
594 |
|
|
|
595 |
|
|
assign cfg_dcommand2 = {11'b0,
|
596 |
|
|
cfg_dev_control2_cpltimeout_dis,
|
597 |
|
|
cfg_dev_control2_cpltimeout_val};
|
598 |
|
|
|
599 |
|
|
// Capture Bus/Device/Function number
|
600 |
|
|
|
601 |
|
|
always @(posedge trn_clk) begin
|
602 |
|
|
if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0;
|
603 |
|
|
else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];
|
604 |
|
|
end
|
605 |
|
|
|
606 |
|
|
always @(posedge trn_clk) begin
|
607 |
|
|
if (trn_lnk_up_n) cfg_device_number_d <= 5'b0;
|
608 |
|
|
else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];
|
609 |
|
|
end
|
610 |
|
|
|
611 |
|
|
always @(posedge trn_clk) begin
|
612 |
|
|
if (trn_lnk_up_n) cfg_function_number_d <= 3'b0;
|
613 |
|
|
else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];
|
614 |
|
|
end
|
615 |
|
|
|
616 |
|
|
// Generate trn_lnk_up_n
|
617 |
|
|
|
618 |
|
|
FDCP #(
|
619 |
|
|
|
620 |
|
|
.INIT(1'b1)
|
621 |
|
|
|
622 |
|
|
) trn_lnk_up_n_i (
|
623 |
|
|
|
624 |
|
|
.Q (trn_lnk_up_n),
|
625 |
|
|
.D (trn_lnk_up_n_int1),
|
626 |
|
|
.C (trn_clk),
|
627 |
|
|
.CLR (1'b0),
|
628 |
|
|
.PRE (1'b0)
|
629 |
|
|
|
630 |
|
|
);
|
631 |
|
|
|
632 |
|
|
FDCP #(
|
633 |
|
|
|
634 |
|
|
.INIT(1'b1)
|
635 |
|
|
|
636 |
|
|
) trn_lnk_up_n_int_i (
|
637 |
|
|
|
638 |
|
|
.Q (trn_lnk_up_n_int1),
|
639 |
|
|
.D (trn_lnk_up_n_int),
|
640 |
|
|
.C (trn_clk),
|
641 |
|
|
.CLR (1'b0),
|
642 |
|
|
.PRE (1'b0)
|
643 |
|
|
|
644 |
|
|
);
|
645 |
|
|
|
646 |
|
|
// Generate trn_reset_n
|
647 |
|
|
|
648 |
|
|
FDCP #(
|
649 |
|
|
|
650 |
|
|
.INIT(1'b0)
|
651 |
|
|
|
652 |
|
|
) trn_reset_n_i (
|
653 |
|
|
|
654 |
|
|
.Q (trn_reset_n),
|
655 |
|
|
.D (trn_reset_n_int1 & ~phy_rdy_n),
|
656 |
|
|
.C (trn_clk),
|
657 |
|
|
.CLR (~sys_reset_n_d),
|
658 |
|
|
.PRE (1'b0)
|
659 |
|
|
|
660 |
|
|
);
|
661 |
|
|
|
662 |
|
|
FDCP #(
|
663 |
|
|
|
664 |
|
|
.INIT(1'b0)
|
665 |
|
|
|
666 |
|
|
) trn_reset_n_int_i (
|
667 |
|
|
|
668 |
|
|
.Q (trn_reset_n_int1 ),
|
669 |
|
|
.D (trn_reset_n_int & ~phy_rdy_n),
|
670 |
|
|
.C (trn_clk),
|
671 |
|
|
.CLR (~sys_reset_n_d),
|
672 |
|
|
.PRE (1'b0)
|
673 |
|
|
|
674 |
|
|
);
|
675 |
|
|
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
//-------------------------------------------------------
|
679 |
|
|
// PCI Express Reset Delay Module
|
680 |
|
|
//-------------------------------------------------------
|
681 |
|
|
|
682 |
|
|
pcie_reset_delay_v6 #(
|
683 |
|
|
|
684 |
|
|
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
|
685 |
|
|
.REF_CLK_FREQ ( REF_CLK_FREQ )
|
686 |
|
|
|
687 |
|
|
)
|
688 |
|
|
pcie_reset_delay_i (
|
689 |
|
|
|
690 |
|
|
.ref_clk ( TxOutClk_bufg ),
|
691 |
|
|
.sys_reset_n ( sys_reset_n ),
|
692 |
|
|
.delayed_sys_reset_n ( sys_reset_n_d )
|
693 |
|
|
|
694 |
|
|
);
|
695 |
|
|
|
696 |
|
|
//-------------------------------------------------------
|
697 |
|
|
// PCI Express Clocking Module
|
698 |
|
|
//-------------------------------------------------------
|
699 |
|
|
|
700 |
|
|
pcie_clocking_v6 #(
|
701 |
|
|
|
702 |
|
|
.CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
|
703 |
|
|
.CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
|
704 |
|
|
.REF_CLK_FREQ(REF_CLK_FREQ),
|
705 |
|
|
.USER_CLK_FREQ(USER_CLK_FREQ)
|
706 |
|
|
|
707 |
|
|
)
|
708 |
|
|
pcie_clocking_i (
|
709 |
|
|
|
710 |
|
|
.sys_clk ( TxOutClk ),
|
711 |
|
|
.gt_pll_lock ( gt_pll_lock ),
|
712 |
|
|
.sel_lnk_rate ( pl_sel_link_rate ),
|
713 |
|
|
.sel_lnk_width ( pl_sel_link_width ),
|
714 |
|
|
|
715 |
|
|
.sys_clk_bufg ( TxOutClk_bufg ),
|
716 |
|
|
.pipe_clk ( pipe_clk ),
|
717 |
|
|
.user_clk ( user_clk ),
|
718 |
|
|
.block_clk ( block_clk ),
|
719 |
|
|
.drp_clk ( drp_clk ),
|
720 |
|
|
.clock_locked ( clock_locked )
|
721 |
|
|
|
722 |
|
|
);
|
723 |
|
|
|
724 |
|
|
//-------------------------------------------------------
|
725 |
|
|
// Virtex6 PCI Express Block Module
|
726 |
|
|
//-------------------------------------------------------
|
727 |
|
|
|
728 |
|
|
pcie_2_0_v6 #(
|
729 |
|
|
|
730 |
|
|
.REF_CLK_FREQ ( REF_CLK_FREQ ),
|
731 |
|
|
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
|
732 |
|
|
.AER_BASE_PTR ( AER_BASE_PTR ),
|
733 |
|
|
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
|
734 |
|
|
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
|
735 |
|
|
.AER_CAP_ID ( AER_CAP_ID ),
|
736 |
|
|
.AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
|
737 |
|
|
.AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
|
738 |
|
|
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
|
739 |
|
|
.AER_CAP_ON ( AER_CAP_ON ),
|
740 |
|
|
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
|
741 |
|
|
.AER_CAP_VERSION ( AER_CAP_VERSION ),
|
742 |
|
|
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
|
743 |
|
|
.BAR0 ( BAR0 ),
|
744 |
|
|
.BAR1 ( BAR1 ),
|
745 |
|
|
.BAR2 ( BAR2 ),
|
746 |
|
|
.BAR3 ( BAR3 ),
|
747 |
|
|
.BAR4 ( BAR4 ),
|
748 |
|
|
.BAR5 ( BAR5 ),
|
749 |
|
|
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
|
750 |
|
|
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
|
751 |
|
|
.CLASS_CODE ( CLASS_CODE ),
|
752 |
|
|
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
|
753 |
|
|
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
|
754 |
|
|
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
|
755 |
|
|
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
|
756 |
|
|
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
|
757 |
|
|
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
|
758 |
|
|
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
|
759 |
|
|
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
|
760 |
|
|
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
|
761 |
|
|
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
|
762 |
|
|
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
|
763 |
|
|
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
|
764 |
|
|
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
|
765 |
|
|
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
|
766 |
|
|
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
|
767 |
|
|
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
|
768 |
|
|
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
|
769 |
|
|
.DEVICE_ID ( DEVICE_ID ),
|
770 |
|
|
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
|
771 |
|
|
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
|
772 |
|
|
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
|
773 |
|
|
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
|
774 |
|
|
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
|
775 |
|
|
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
|
776 |
|
|
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
|
777 |
|
|
.DSN_BASE_PTR ( DSN_BASE_PTR ),
|
778 |
|
|
.DSN_CAP_ID ( DSN_CAP_ID ),
|
779 |
|
|
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
|
780 |
|
|
.DSN_CAP_ON ( DSN_CAP_ON ),
|
781 |
|
|
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
|
782 |
|
|
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
|
783 |
|
|
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
|
784 |
|
|
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
|
785 |
|
|
.EXPANSION_ROM ( EXPANSION_ROM ),
|
786 |
|
|
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
|
787 |
|
|
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
|
788 |
|
|
.HEADER_TYPE ( HEADER_TYPE ),
|
789 |
|
|
.INFER_EI ( INFER_EI ),
|
790 |
|
|
.INTERRUPT_PIN ( INTERRUPT_PIN ),
|
791 |
|
|
.IS_SWITCH ( IS_SWITCH ),
|
792 |
|
|
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
|
793 |
|
|
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
|
794 |
|
|
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
|
795 |
|
|
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
|
796 |
|
|
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
|
797 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
|
798 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
|
799 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
|
800 |
|
|
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
|
801 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
|
802 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
|
803 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
|
804 |
|
|
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
|
805 |
|
|
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
|
806 |
|
|
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
|
807 |
|
|
.LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
|
808 |
|
|
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
|
809 |
|
|
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
|
810 |
|
|
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
|
811 |
|
|
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
|
812 |
|
|
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
|
813 |
|
|
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
|
814 |
|
|
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
|
815 |
|
|
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
|
816 |
|
|
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
|
817 |
|
|
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
|
818 |
|
|
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
|
819 |
|
|
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
|
820 |
|
|
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
|
821 |
|
|
.MSI_BASE_PTR ( MSI_BASE_PTR ),
|
822 |
|
|
.MSI_CAP_ID ( MSI_CAP_ID ),
|
823 |
|
|
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
|
824 |
|
|
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
|
825 |
|
|
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
|
826 |
|
|
.MSI_CAP_ON ( MSI_CAP_ON ),
|
827 |
|
|
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
|
828 |
|
|
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
|
829 |
|
|
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
|
830 |
|
|
.MSIX_CAP_ID ( MSIX_CAP_ID ),
|
831 |
|
|
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
|
832 |
|
|
.MSIX_CAP_ON ( MSIX_CAP_ON ),
|
833 |
|
|
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
|
834 |
|
|
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
|
835 |
|
|
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
|
836 |
|
|
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
|
837 |
|
|
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
|
838 |
|
|
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
|
839 |
|
|
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
|
840 |
|
|
.N_FTS_GEN1 ( N_FTS_GEN1 ),
|
841 |
|
|
.N_FTS_GEN2 ( N_FTS_GEN2 ),
|
842 |
|
|
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
|
843 |
|
|
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
|
844 |
|
|
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
|
845 |
|
|
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
|
846 |
|
|
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
|
847 |
|
|
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
|
848 |
|
|
.PCIE_CAP_ON ( PCIE_CAP_ON ),
|
849 |
|
|
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
|
850 |
|
|
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
|
851 |
|
|
.PCIE_REVISION ( PCIE_REVISION ),
|
852 |
|
|
.PGL0_LANE ( PGL0_LANE ),
|
853 |
|
|
.PGL1_LANE ( PGL1_LANE ),
|
854 |
|
|
.PGL2_LANE ( PGL2_LANE ),
|
855 |
|
|
.PGL3_LANE ( PGL3_LANE ),
|
856 |
|
|
.PGL4_LANE ( PGL4_LANE ),
|
857 |
|
|
.PGL5_LANE ( PGL5_LANE ),
|
858 |
|
|
.PGL6_LANE ( PGL6_LANE ),
|
859 |
|
|
.PGL7_LANE ( PGL7_LANE ),
|
860 |
|
|
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
|
861 |
|
|
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
|
862 |
|
|
.PM_BASE_PTR ( PM_BASE_PTR ),
|
863 |
|
|
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
|
864 |
|
|
.PM_CAP_DSI ( PM_CAP_DSI ),
|
865 |
|
|
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
|
866 |
|
|
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
|
867 |
|
|
.PM_CAP_ID ( PM_CAP_ID ),
|
868 |
|
|
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
|
869 |
|
|
.PM_CAP_ON ( PM_CAP_ON ),
|
870 |
|
|
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
|
871 |
|
|
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
|
872 |
|
|
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
|
873 |
|
|
.PM_CAP_VERSION ( PM_CAP_VERSION ),
|
874 |
|
|
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
|
875 |
|
|
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
|
876 |
|
|
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
|
877 |
|
|
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
|
878 |
|
|
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
|
879 |
|
|
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
|
880 |
|
|
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
|
881 |
|
|
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
|
882 |
|
|
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
|
883 |
|
|
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
|
884 |
|
|
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
|
885 |
|
|
.PM_DATA0 ( PM_DATA0 ),
|
886 |
|
|
.PM_DATA1 ( PM_DATA1 ),
|
887 |
|
|
.PM_DATA2 ( PM_DATA2 ),
|
888 |
|
|
.PM_DATA3 ( PM_DATA3 ),
|
889 |
|
|
.PM_DATA4 ( PM_DATA4 ),
|
890 |
|
|
.PM_DATA5 ( PM_DATA5 ),
|
891 |
|
|
.PM_DATA6 ( PM_DATA6 ),
|
892 |
|
|
.PM_DATA7 ( PM_DATA7 ),
|
893 |
|
|
.RECRC_CHK ( RECRC_CHK ),
|
894 |
|
|
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
|
895 |
|
|
.REVISION_ID ( REVISION_ID ),
|
896 |
|
|
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
|
897 |
|
|
.SELECT_DLL_IF ( SELECT_DLL_IF ),
|
898 |
|
|
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
|
899 |
|
|
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
|
900 |
|
|
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
|
901 |
|
|
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
|
902 |
|
|
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
|
903 |
|
|
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
|
904 |
|
|
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
|
905 |
|
|
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
|
906 |
|
|
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
|
907 |
|
|
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
|
908 |
|
|
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
|
909 |
|
|
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
|
910 |
|
|
.SPARE_BIT0 ( SPARE_BIT0 ),
|
911 |
|
|
.SPARE_BIT1 ( SPARE_BIT1 ),
|
912 |
|
|
.SPARE_BIT2 ( SPARE_BIT2 ),
|
913 |
|
|
.SPARE_BIT3 ( SPARE_BIT3 ),
|
914 |
|
|
.SPARE_BIT4 ( SPARE_BIT4 ),
|
915 |
|
|
.SPARE_BIT5 ( SPARE_BIT5 ),
|
916 |
|
|
.SPARE_BIT6 ( SPARE_BIT6 ),
|
917 |
|
|
.SPARE_BIT7 ( SPARE_BIT7 ),
|
918 |
|
|
.SPARE_BIT8 ( SPARE_BIT8 ),
|
919 |
|
|
.SPARE_BYTE0 ( SPARE_BYTE0 ),
|
920 |
|
|
.SPARE_BYTE1 ( SPARE_BYTE1 ),
|
921 |
|
|
.SPARE_BYTE2 ( SPARE_BYTE2 ),
|
922 |
|
|
.SPARE_BYTE3 ( SPARE_BYTE3 ),
|
923 |
|
|
.SPARE_WORD0 ( SPARE_WORD0 ),
|
924 |
|
|
.SPARE_WORD1 ( SPARE_WORD1 ),
|
925 |
|
|
.SPARE_WORD2 ( SPARE_WORD2 ),
|
926 |
|
|
.SPARE_WORD3 ( SPARE_WORD3 ),
|
927 |
|
|
.SUBSYSTEM_ID ( SUBSYSTEM_ID ),
|
928 |
|
|
.SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
|
929 |
|
|
.TL_RBYPASS ( TL_RBYPASS ),
|
930 |
|
|
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
|
931 |
|
|
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
|
932 |
|
|
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
|
933 |
|
|
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
|
934 |
|
|
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
|
935 |
|
|
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
|
936 |
|
|
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
|
937 |
|
|
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
|
938 |
|
|
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
|
939 |
|
|
.UPSTREAM_FACING ( UPSTREAM_FACING ),
|
940 |
|
|
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
|
941 |
|
|
.UR_INV_REQ ( UR_INV_REQ ),
|
942 |
|
|
.USER_CLK_FREQ ( USER_CLK_FREQ ),
|
943 |
|
|
.VC_BASE_PTR ( VC_BASE_PTR ),
|
944 |
|
|
.VC_CAP_ID ( VC_CAP_ID ),
|
945 |
|
|
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
|
946 |
|
|
.VC_CAP_ON ( VC_CAP_ON ),
|
947 |
|
|
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
|
948 |
|
|
.VC_CAP_VERSION ( VC_CAP_VERSION ),
|
949 |
|
|
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
|
950 |
|
|
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
|
951 |
|
|
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
|
952 |
|
|
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
|
953 |
|
|
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
|
954 |
|
|
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
|
955 |
|
|
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
|
956 |
|
|
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
|
957 |
|
|
.VENDOR_ID ( VENDOR_ID ),
|
958 |
|
|
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
|
959 |
|
|
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
|
960 |
|
|
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
|
961 |
|
|
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
|
962 |
|
|
.VSEC_CAP_ID ( VSEC_CAP_ID ),
|
963 |
|
|
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
|
964 |
|
|
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
|
965 |
|
|
.VSEC_CAP_ON ( VSEC_CAP_ON ),
|
966 |
|
|
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
|
967 |
|
|
|
968 |
|
|
)
|
969 |
|
|
pcie_2_0_i (
|
970 |
|
|
|
971 |
|
|
.PCIEXPRXN( pci_exp_rxn ),
|
972 |
|
|
.PCIEXPRXP( pci_exp_rxp ),
|
973 |
|
|
.PCIEXPTXN( pci_exp_txn ),
|
974 |
|
|
.PCIEXPTXP( pci_exp_txp ),
|
975 |
|
|
|
976 |
|
|
.SYSCLK( sys_clk ),
|
977 |
|
|
.TRNLNKUPN( trn_lnk_up_n_int ),
|
978 |
|
|
.TRNCLK( trn_clk ),
|
979 |
|
|
|
980 |
|
|
.FUNDRSTN (sys_reset_n_d),
|
981 |
|
|
.PHYRDYN( phy_rdy_n ),
|
982 |
|
|
|
983 |
|
|
.LNKCLKEN ( ),
|
984 |
|
|
.USERRSTN( trn_reset_n_int ),
|
985 |
|
|
.RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),
|
986 |
|
|
.SYSRSTN( ~phy_rdy_n ),
|
987 |
|
|
.PLRSTN( 1'b1 ),
|
988 |
|
|
.DLRSTN( 1'b1 ),
|
989 |
|
|
.TLRSTN( 1'b1 ),
|
990 |
|
|
.FUNCLVLRSTN( 1'b1 ),
|
991 |
|
|
.CMRSTN( 1'b1 ),
|
992 |
|
|
.CMSTICKYRSTN( 1'b1 ),
|
993 |
|
|
|
994 |
|
|
.TRNRBARHITN( trn_rbar_hit_n ),
|
995 |
|
|
.TRNRD( trn_rd ),
|
996 |
|
|
.TRNRECRCERRN( ),
|
997 |
|
|
.TRNREOFN( trn_reof_n ),
|
998 |
|
|
.TRNRERRFWDN( trn_rerrfwd_n ),
|
999 |
|
|
.TRNRREMN( trn_rrem_n ),
|
1000 |
|
|
.TRNRSOFN( trn_rsof_n ),
|
1001 |
|
|
.TRNRSRCDSCN( trn_rsrc_dsc_n ),
|
1002 |
|
|
.TRNRSRCRDYN( trn_rsrc_rdy_n ),
|
1003 |
|
|
.TRNRDSTRDYN( trn_rdst_rdy_n ),
|
1004 |
|
|
.TRNRNPOKN( trn_rnp_ok_n ),
|
1005 |
|
|
|
1006 |
|
|
.TRNTBUFAV( trn_tbuf_av ),
|
1007 |
|
|
.TRNTCFGREQN( trn_tcfg_req_n ),
|
1008 |
|
|
.TRNTDLLPDSTRDYN( ),
|
1009 |
|
|
.TRNTDSTRDYN( trn_tdst_rdy_n ),
|
1010 |
|
|
.TRNTERRDROPN( trn_terr_drop_n ),
|
1011 |
|
|
.TRNTCFGGNTN( trn_tcfg_gnt_n ),
|
1012 |
|
|
.TRNTD( trn_td ),
|
1013 |
|
|
.TRNTDLLPDATA( 32'b0 ),
|
1014 |
|
|
.TRNTDLLPSRCRDYN( 1'b1 ),
|
1015 |
|
|
.TRNTECRCGENN( 1'b1 ),
|
1016 |
|
|
.TRNTEOFN( trn_teof_n ),
|
1017 |
|
|
.TRNTERRFWDN( trn_terrfwd_n ),
|
1018 |
|
|
.TRNTREMN( trn_trem_n ),
|
1019 |
|
|
.TRNTSOFN( trn_tsof_n ),
|
1020 |
|
|
.TRNTSRCDSCN( trn_tsrc_dsc_n ),
|
1021 |
|
|
.TRNTSRCRDYN( trn_tsrc_rdy_n ),
|
1022 |
|
|
.TRNTSTRN( trn_tstr_n ),
|
1023 |
|
|
|
1024 |
|
|
.TRNFCCPLD( trn_fc_cpld ),
|
1025 |
|
|
.TRNFCCPLH( trn_fc_cplh ),
|
1026 |
|
|
.TRNFCNPD( trn_fc_npd ),
|
1027 |
|
|
.TRNFCNPH( trn_fc_nph ),
|
1028 |
|
|
.TRNFCPD( trn_fc_pd ),
|
1029 |
|
|
.TRNFCPH( trn_fc_ph ),
|
1030 |
|
|
.TRNFCSEL( trn_fc_sel ),
|
1031 |
|
|
|
1032 |
|
|
.CFGAERECRCCHECKEN(),
|
1033 |
|
|
.CFGAERECRCGENEN(),
|
1034 |
|
|
.CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),
|
1035 |
|
|
.CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),
|
1036 |
|
|
.CFGCOMMANDIOENABLE( cfg_cmd_io_en ),
|
1037 |
|
|
.CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),
|
1038 |
|
|
.CFGCOMMANDSERREN( cfg_cmd_serr_en ),
|
1039 |
|
|
.CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),
|
1040 |
|
|
.CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),
|
1041 |
|
|
.CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),
|
1042 |
|
|
.CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),
|
1043 |
|
|
.CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),
|
1044 |
|
|
.CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),
|
1045 |
|
|
.CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),
|
1046 |
|
|
.CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),
|
1047 |
|
|
.CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),
|
1048 |
|
|
.CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),
|
1049 |
|
|
.CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),
|
1050 |
|
|
.CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),
|
1051 |
|
|
.CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),
|
1052 |
|
|
.CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),
|
1053 |
|
|
.CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),
|
1054 |
|
|
.CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),
|
1055 |
|
|
.CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),
|
1056 |
|
|
.CFGDO( cfg_do ),
|
1057 |
|
|
.CFGERRAERHEADERLOGSETN(),
|
1058 |
|
|
.CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),
|
1059 |
|
|
.CFGINTERRUPTDO( cfg_interrupt_do ),
|
1060 |
|
|
.CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),
|
1061 |
|
|
.CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),
|
1062 |
|
|
.CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),
|
1063 |
|
|
.CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),
|
1064 |
|
|
.CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),
|
1065 |
|
|
.CFGLINKCONTROLRCB( cfg_link_control_rcb ),
|
1066 |
|
|
.CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),
|
1067 |
|
|
.CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),
|
1068 |
|
|
.CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),
|
1069 |
|
|
.CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),
|
1070 |
|
|
.CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),
|
1071 |
|
|
.CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),
|
1072 |
|
|
.CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),
|
1073 |
|
|
.CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),
|
1074 |
|
|
.CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),
|
1075 |
|
|
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),
|
1076 |
|
|
.CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),
|
1077 |
|
|
.CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),
|
1078 |
|
|
.CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),
|
1079 |
|
|
.CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),
|
1080 |
|
|
.CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),
|
1081 |
|
|
.CFGMSGDATA( cfg_msg_data ),
|
1082 |
|
|
.CFGMSGRECEIVED( cfg_msg_received ),
|
1083 |
|
|
.CFGMSGRECEIVEDASSERTINTA(),
|
1084 |
|
|
.CFGMSGRECEIVEDASSERTINTB(),
|
1085 |
|
|
.CFGMSGRECEIVEDASSERTINTC(),
|
1086 |
|
|
.CFGMSGRECEIVEDASSERTINTD(),
|
1087 |
|
|
.CFGMSGRECEIVEDDEASSERTINTA(),
|
1088 |
|
|
.CFGMSGRECEIVEDDEASSERTINTB(),
|
1089 |
|
|
.CFGMSGRECEIVEDDEASSERTINTC(),
|
1090 |
|
|
.CFGMSGRECEIVEDDEASSERTINTD(),
|
1091 |
|
|
.CFGMSGRECEIVEDERRCOR(),
|
1092 |
|
|
.CFGMSGRECEIVEDERRFATAL(),
|
1093 |
|
|
.CFGMSGRECEIVEDERRNONFATAL(),
|
1094 |
|
|
.CFGMSGRECEIVEDPMASNAK(),
|
1095 |
|
|
.CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),
|
1096 |
|
|
.CFGMSGRECEIVEDPMETOACK(),
|
1097 |
|
|
.CFGMSGRECEIVEDPMPME(),
|
1098 |
|
|
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),
|
1099 |
|
|
.CFGMSGRECEIVEDUNLOCK(),
|
1100 |
|
|
.CFGPCIELINKSTATE( cfg_pcie_link_state_n ),
|
1101 |
|
|
.CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),
|
1102 |
|
|
.CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),
|
1103 |
|
|
.CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),
|
1104 |
|
|
.CFGPMRCVASREQL1N(),
|
1105 |
|
|
.CFGPMRCVENTERL1N(),
|
1106 |
|
|
.CFGPMRCVENTERL23N(),
|
1107 |
|
|
.CFGPMRCVREQACKN(),
|
1108 |
|
|
.CFGRDWRDONEN( cfg_rd_wr_done_n ),
|
1109 |
|
|
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(),
|
1110 |
|
|
.CFGTRANSACTION(),
|
1111 |
|
|
.CFGTRANSACTIONADDR(),
|
1112 |
|
|
.CFGTRANSACTIONTYPE(),
|
1113 |
|
|
.CFGVCTCVCMAP(),
|
1114 |
|
|
.CFGBYTEENN( cfg_byte_en_n ),
|
1115 |
|
|
.CFGDI( cfg_di ),
|
1116 |
|
|
.CFGDSBUSNUMBER( 8'b0 ),
|
1117 |
|
|
.CFGDSDEVICENUMBER( 5'b0 ),
|
1118 |
|
|
.CFGDSFUNCTIONNUMBER( 3'b0 ),
|
1119 |
|
|
.CFGDSN( cfg_dsn ),
|
1120 |
|
|
.CFGDWADDR( cfg_dwaddr ),
|
1121 |
|
|
.CFGERRACSN( 1'b1 ),
|
1122 |
|
|
.CFGERRAERHEADERLOG( 128'h0 ),
|
1123 |
|
|
.CFGERRCORN( cfg_err_cor_n ),
|
1124 |
|
|
.CFGERRCPLABORTN( cfg_err_cpl_abort_n ),
|
1125 |
|
|
.CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),
|
1126 |
|
|
.CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),
|
1127 |
|
|
.CFGERRECRCN( cfg_err_ecrc_n ),
|
1128 |
|
|
.CFGERRLOCKEDN( cfg_err_locked_n ),
|
1129 |
|
|
.CFGERRPOSTEDN( cfg_err_posted_n ),
|
1130 |
|
|
.CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),
|
1131 |
|
|
.CFGERRURN( cfg_err_ur_n ),
|
1132 |
|
|
.CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),
|
1133 |
|
|
.CFGINTERRUPTDI( cfg_interrupt_di ),
|
1134 |
|
|
.CFGINTERRUPTN( cfg_interrupt_n ),
|
1135 |
|
|
.CFGPMDIRECTASPML1N( 1'b1 ),
|
1136 |
|
|
.CFGPMSENDPMACKN( 1'b1 ),
|
1137 |
|
|
.CFGPMSENDPMETON( 1'b1 ),
|
1138 |
|
|
.CFGPMSENDPMNAKN( 1'b1 ),
|
1139 |
|
|
.CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),
|
1140 |
|
|
.CFGPMWAKEN( cfg_pm_wake_n ),
|
1141 |
|
|
.CFGPORTNUMBER( 8'h0 ),
|
1142 |
|
|
.CFGRDENN( cfg_rd_en_n ),
|
1143 |
|
|
.CFGTRNPENDINGN( cfg_trn_pending_n ),
|
1144 |
|
|
.CFGWRENN( cfg_wr_en_n ),
|
1145 |
|
|
.CFGWRREADONLYN( 1'b1 ),
|
1146 |
|
|
.CFGWRRW1CASRWN( 1'b1 ),
|
1147 |
|
|
|
1148 |
|
|
.PLINITIALLINKWIDTH( pl_initial_link_width ),
|
1149 |
|
|
.PLLANEREVERSALMODE( pl_lane_reversal_mode ),
|
1150 |
|
|
.PLLINKGEN2CAP( pl_link_gen2_capable ),
|
1151 |
|
|
.PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),
|
1152 |
|
|
.PLLINKUPCFGCAP( pl_link_upcfg_capable ),
|
1153 |
|
|
.PLLTSSMSTATE( pl_ltssm_state ),
|
1154 |
|
|
.PLPHYLNKUPN( ), // Debug
|
1155 |
|
|
.PLRECEIVEDHOTRST( pl_received_hot_rst ),
|
1156 |
|
|
.PLRXPMSTATE(), // Debug
|
1157 |
|
|
.PLSELLNKRATE( pl_sel_link_rate ),
|
1158 |
|
|
.PLSELLNKWIDTH( pl_sel_link_width ),
|
1159 |
|
|
.PLTXPMSTATE(), // Debug
|
1160 |
|
|
.PLDIRECTEDLINKAUTON( pl_directed_link_auton ),
|
1161 |
|
|
.PLDIRECTEDLINKCHANGE( pl_directed_link_change ),
|
1162 |
|
|
.PLDIRECTEDLINKSPEED( pl_directed_link_speed ),
|
1163 |
|
|
.PLDIRECTEDLINKWIDTH( pl_directed_link_width ),
|
1164 |
|
|
.PLDOWNSTREAMDEEMPHSOURCE( 1'b1 ),
|
1165 |
|
|
.PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),
|
1166 |
|
|
.PLTRANSMITHOTRST( 1'b0 ),
|
1167 |
|
|
|
1168 |
|
|
.DBGSCLRA(),
|
1169 |
|
|
.DBGSCLRB(),
|
1170 |
|
|
.DBGSCLRC(),
|
1171 |
|
|
.DBGSCLRD(),
|
1172 |
|
|
.DBGSCLRE(),
|
1173 |
|
|
.DBGSCLRF(),
|
1174 |
|
|
.DBGSCLRG(),
|
1175 |
|
|
.DBGSCLRH(),
|
1176 |
|
|
.DBGSCLRI(),
|
1177 |
|
|
.DBGSCLRJ(),
|
1178 |
|
|
.DBGSCLRK(),
|
1179 |
|
|
.DBGVECA(),
|
1180 |
|
|
.DBGVECB(),
|
1181 |
|
|
.DBGVECC(),
|
1182 |
|
|
.PLDBGVEC(),
|
1183 |
|
|
.DBGMODE( 2'b0 ),
|
1184 |
|
|
.DBGSUBMODE( 1'b0 ),
|
1185 |
|
|
.PLDBGMODE( 3'b0 ),
|
1186 |
|
|
|
1187 |
|
|
.PCIEDRPDO(),
|
1188 |
|
|
.PCIEDRPDRDY(),
|
1189 |
|
|
.PCIEDRPCLK(1'b0),
|
1190 |
|
|
.PCIEDRPDADDR(9'b0),
|
1191 |
|
|
.PCIEDRPDEN(1'b0),
|
1192 |
|
|
.PCIEDRPDI(16'b0),
|
1193 |
|
|
.PCIEDRPDWE(1'b0),
|
1194 |
|
|
|
1195 |
|
|
.GTPLLLOCK( gt_pll_lock ),
|
1196 |
|
|
.PIPECLK( pipe_clk ),
|
1197 |
|
|
.USERCLK( user_clk ),
|
1198 |
|
|
.DRPCLK(drp_clk),
|
1199 |
|
|
.CLOCKLOCKED( clock_locked ),
|
1200 |
|
|
.TxOutClk(TxOutClk)
|
1201 |
|
|
|
1202 |
|
|
|
1203 |
|
|
);
|
1204 |
|
|
|
1205 |
|
|
endmodule
|