Subversion Repositories pcie_sg_dma

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-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : PIO.vhd

-- Version    : 1.7

----

---- Description: Programmed I/O module. Design implements 8 KBytes of programmable

----              memory space. Host processor can access this memory space using

----              Memory Read 32 and Memory Write 32 TLPs. Design accepts 

----              1 Double Word (DW) payload length on Memory Write 32 TLP and

----              responds to 1 DW length Memory Read 32 TLPs with a Completion

----              with Data TLP (1DW payload).

----              

----              Module is designed to operate with 32 bit and 64 bit interfaces.

----

----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity PIO is

port (

  trn_clk                : in std_logic;

  trn_reset_n            : in std_logic;

  trn_lnk_up_n           : in std_logic;

  trn_td                 : out std_logic_vector(63 downto 0);

  trn_trem_n             : out std_logic_vector(7 downto 0);

  trn_tsof_n             : out std_logic;

  trn_teof_n             : out std_logic;

  trn_tsrc_rdy_n         : out std_logic;

  trn_tsrc_dsc_n         : out std_logic;

  trn_tdst_rdy_n         : in std_logic;

  trn_tdst_dsc_n         : in std_logic;

  trn_rd                 : in std_logic_vector(63 downto 0);

  trn_rrem_n             : in std_logic_vector(7 downto 0);

  trn_rsof_n             : in std_logic;

  trn_reof_n             : in std_logic;

  trn_rsrc_rdy_n         : in std_logic;

  trn_rsrc_dsc_n         : in std_logic;

  trn_rbar_hit_n         : in std_logic_vector(6 downto 0);

  trn_rdst_rdy_n         : out std_logic;

  cfg_to_turnoff_n       : in std_logic;

  cfg_turnoff_ok_n       : out std_logic;

  cfg_completer_id       : in std_logic_vector(15 downto 0);

  cfg_bus_mstr_enable    : in std_logic

);

end PIO;

architecture rtl of PIO is

-- Local wires

signal req_compl      : std_logic;

signal compl_done     : std_logic;

signal pio_reset_n    : std_logic;

component PIO_EP

port (

  clk                    : in std_logic;

  rst_n                  : in std_logic;

  -- LocalLink Tx

  trn_td                 : out std_logic_vector(63 downto 0);

  trn_trem_n             : out std_logic_vector(7 downto 0);

  trn_tsof_n             : out std_logic;

  trn_teof_n             : out std_logic;

  trn_tsrc_dsc_n         : out std_logic;

  trn_tsrc_rdy_n         : out std_logic;

  trn_tdst_dsc_n         : in std_logic;

  trn_tdst_rdy_n         : in std_logic;

  -- LocalLink Rx

  trn_rd                 : in std_logic_vector(63 downto 0);

  trn_rrem_n             : in std_logic_vector(7 downto 0);

  trn_rsof_n             : in std_logic;

  trn_reof_n             : in std_logic;

  trn_rsrc_rdy_n         : in std_logic;

  trn_rsrc_dsc_n         : in std_logic;

  trn_rbar_hit_n         : in std_logic_vector(6 downto 0);

  trn_rdst_rdy_n         : out std_logic;

  req_compl_o            : out std_logic;

  compl_done_o           : out std_logic;

  cfg_completer_id       : in std_logic_vector(15 downto 0);

  cfg_bus_mstr_enable    : in std_logic

);

end component;

component PIO_TO_CTRL

port (

  clk : in std_logic;

  rst_n : in std_logic;

  req_compl_i : in std_logic;

  compl_done_i : in std_logic;

  cfg_to_turnoff_n : in std_logic;

  cfg_turnoff_ok_n : out std_logic

);

end component;

begin

pio_reset_n  <= not trn_lnk_up_n;

-- PIO instance

PIO_EP_ins : PIO_EP

port map (

  clk => trn_clk,                            -- I

  rst_n => pio_reset_n,                      -- I

  trn_td => trn_td,                          -- O [127/63:0]

  trn_trem_n => trn_trem_n,                  -- O [1/0:0]

  trn_tsof_n => trn_tsof_n,                  -- O

  trn_teof_n => trn_teof_n,                  -- O

  trn_tsrc_rdy_n => trn_tsrc_rdy_n,          -- O

  trn_tsrc_dsc_n => trn_tsrc_dsc_n,          -- O

  trn_tdst_rdy_n => trn_tdst_rdy_n,          -- I

  trn_tdst_dsc_n => trn_tdst_dsc_n,          -- I

  trn_rd => trn_rd,                          -- I [127/63:0]

  trn_rrem_n => trn_rrem_n,                  -- I [1/0:0]

  trn_rsof_n => trn_rsof_n,                  -- I

  trn_reof_n => trn_reof_n,                  -- I

  trn_rsrc_rdy_n => trn_rsrc_rdy_n,          -- I

  trn_rsrc_dsc_n => trn_rsrc_dsc_n,          -- I

  trn_rbar_hit_n => trn_rbar_hit_n,          -- I

  trn_rdst_rdy_n => trn_rdst_rdy_n,          -- O

  req_compl_o => req_compl,                  -- O

  compl_done_o => compl_done,                -- O

  cfg_completer_id => cfg_completer_id,      -- I [15:0]

  cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I

);

    --

    -- Turn-Off controller

    --

PIO_TO : PIO_TO_CTRL port map   (

   clk => trn_clk,                             -- I

   rst_n => trn_reset_n,                       -- I

   req_compl_i => req_compl,                   -- I

   compl_done_i => compl_done,                 -- I

   cfg_to_turnoff_n => cfg_to_turnoff_n,       -- I

   cfg_turnoff_ok_n => cfg_turnoff_ok_n        -- O

);

end;  -- PIO