Subversion Repositories pcie_sg_dma

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-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : pci_exp_usrapp_tx.vhd

-- Version    : 1.7

-- Filename: pci_exp_usrapp_tx.vhd

--

-- Description:  PCI Express dsport Tx interface.

--

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_textio.all;

use ieee.numeric_std.all;

library std;

use std.textio.all;

entity pci_exp_usrapp_tx is

port (

  trn_td                   : out std_logic_vector (63 downto 0 );

  trn_trem_n               : out std_logic_vector (7 downto 0 );

  trn_tsof_n               : out std_logic;

  trn_teof_n               : out std_logic;

  trn_terrfwd_n            : out std_logic;

  trn_tsrc_rdy_n           : out std_logic;

  trn_tsrc_dsc_n           : out std_logic;

  trn_clk                  : in std_logic;

  trn_reset_n              : in std_logic;

  trn_lnk_up_n             : in std_logic;

  trn_tdst_rdy_n           : in std_logic;

  trn_tdst_dsc_n           : in std_logic;

  trn_tbuf_av              : in std_logic_vector (5 downto 0);

  rx_tx_read_data          : in std_logic_vector(31 downto 0);

  rx_tx_read_data_valid    : in std_logic;

  tx_rx_read_data_valid    : out std_logic

);

end pci_exp_usrapp_tx;

architecture rtl of pci_exp_usrapp_tx is

component tests

generic (

  test_selector : in string  := String'("sample_smoke_test0")

 );

port (

  trn_td                   : out std_logic_vector (63 downto 0 );

  trn_trem_n               : out std_logic_vector (7 downto 0 );

  trn_tsof_n               : out std_logic;

  trn_teof_n               : out std_logic;

  trn_terrfwd_n            : out std_logic;

  trn_tsrc_rdy_n           : out std_logic;

  trn_tsrc_dsc_n           : out std_logic;

  trn_clk                  : in std_logic;

  trn_reset_n              : in std_logic;

  trn_lnk_up_n             : in std_logic;

  trn_tdst_rdy_n           : in std_logic;

  trn_tdst_dsc_n           : in std_logic;

  trn_tbuf_av              : in std_logic_vector(5 downto 0);

  rx_tx_read_data          : in std_logic_vector(31 downto 0);

  rx_tx_read_data_valid    : in std_logic;

  tx_rx_read_data_valid    : out std_logic

);

end component;

begin

 TESTS_INST :  tests

generic map (

  test_selector => String'("sample_smoke_test0")

 )

port map (

  trn_td => trn_td,

  trn_trem_n => trn_trem_n,

  trn_tsof_n => trn_tsof_n,

  trn_teof_n => trn_teof_n,

  trn_terrfwd_n => trn_terrfwd_n,

  trn_tsrc_rdy_n => trn_tsrc_rdy_n,

  trn_tsrc_dsc_n => trn_tsrc_dsc_n,

  trn_clk => trn_clk,

  trn_reset_n => trn_reset_n,

  trn_lnk_up_n => trn_lnk_up_n,

  trn_tdst_rdy_n => trn_tdst_rdy_n,

  trn_tdst_dsc_n => trn_tdst_dsc_n,

  trn_tbuf_av => trn_tbuf_av,

  rx_tx_read_data => rx_tx_read_data,

  rx_tx_read_data_valid => rx_tx_read_data_valid,

  tx_rx_read_data_valid => tx_rx_read_data_valid

);

end; -- pci_exp_usrapp_tx