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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_7_x4/] [simulation/] [dsport/] [test_interface.vhd] - Blame information for rev 13

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1 13 barabba 
-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
11 
-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
46 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 
-- PART OF THIS FILE AT ALL TIMES.
48 
--
49 
-------------------------------------------------------------------------------
50 
-- Project    : Virtex-6 Integrated Block for PCI Express
51 
-- File       : test_interface.vhd
52 
-- Version    : 1.7
53 
---- Description:  Procedures invoked by the test program file.
54 
----
55 
----
56 
--------------------------------------------------------------------------------
57 
 
58 
library ieee;
59 
use ieee.std_logic_1164.all;
60 
use ieee.std_logic_textio.all;
61 
use ieee.numeric_std.all;
62 
 
63 
library std;
64 
use std.textio.all;
65 
 
66 
-- Package Declaration
67 
 
68 
package test_interface is
69 
 
70 
type BYTE_ARRAY             is array (999 downto 0) of std_logic_vector(7 downto 0);
71 
type DATA_ARRAY             is array (499 downto 0) of std_logic_vector(7 downto 0);
72 
type THIRTY_THREE_BIT_ARRAY is array (6 downto 0) of std_logic_vector((33 - 1) downto 0);
73 
type DWORD_ARRAY            is array (6 downto 0) of std_logic_vector((32 - 1) downto 0);
74 
type ENABLE_ARRAY           is array (6 downto 0) of INTEGER;
75 
 
76 
constant PCI_EXP_MEM_READ32            : std_logic_vector(6 downto 0) := "0000000";
77 
constant PCI_EXP_IO_READ               : std_logic_vector(6 downto 0) := "0000010";
78 
constant PCI_EXP_CFG_READ0             : std_logic_vector(6 downto 0) := "0000100";
79 
constant PCI_EXP_COMPLETION_WO_DATA    : std_logic_vector(6 downto 0) := "0001010";
80 
constant PCI_EXP_MEM_READ64            : std_logic_vector(6 downto 0) := "0100000";
81 
constant PCI_EXP_MSG_NODATA            : std_logic_vector(6 downto 3) := "0110";
82 
constant PCI_EXP_MEM_WRITE32           : std_logic_vector(6 downto 0) := "1000000";
83 
constant PCI_EXP_IO_WRITE              : std_logic_vector(6 downto 0) := "1000010";
84 
constant PCI_EXP_CFG_WRITE0            : std_logic_vector(6 downto 0) := "1000100";
85 
constant PCI_EXP_COMPLETION_DATA       : std_logic_vector(6 downto 0) := "1001010";
86 
constant PCI_EXP_MEM_WRITE64           : std_logic_vector(6 downto 0) := "1100000";
87 
constant PCI_EXP_MSG_DATA              : std_logic_vector(6 downto 3) := "1110";
88 
 
89 
constant COMPLETER_ID_CFG              : std_logic_vector(15 downto 0) := X"01A0";
90 
 
91 
constant DEV_ID                        : std_logic_vector(15 downto 0) := X"6014";
92 
constant VEN_ID                        : std_logic_vector(15 downto 0) := X"10EE";
93 
constant DEV_VEN_ID                    : std_logic_vector(31 downto 0) := (DEV_ID & VEN_ID);
94 
 
95 
signal trn_trem_n_c    : std_logic_vector ((8  - 1) downto 0 );
96 
signal trn_td_c        : std_logic_vector ((64 - 1) downto 0 );
97 
 
98 
shared variable frame_store_tx          : BYTE_ARRAY;
99 
shared variable frame_store_tx_idx      : INTEGER;
100 
shared variable DATA_STORE              : DATA_ARRAY;
101 
shared variable P_READ_DATA             : std_logic_vector(31 downto 0);
102 
shared variable Lglobal                 : line;
103 
shared variable BAR_RANGE               : DWORD_ARRAY;
104 
shared variable BAR                     : THIRTY_THREE_BIT_ARRAY;
105 
shared variable NUMBER_OF_IO_BARS       : INTEGER;
106 
shared variable NUMBER_OF_MEM64_BARS    : INTEGER;
107 
shared variable NUMBER_OF_MEM32_BARS    : INTEGER;
108 
shared variable BAR_ENABLED             : ENABLE_ARRAY;
109 
shared variable pio_check_design : boolean;
110 
shared variable i                       : INTEGER;
111 
shared variable success                 : boolean;
112 
 
113 
-- Cfg Rd/Wr interface signals
114 
type cfg_rdwr_sigs is record
115 
  trn_clk          : std_logic;
116 
  trn_reset_n      : std_logic;
117 
  cfg_rd_wr_done_n : std_logic;
118 
  cfg_dwaddr       : std_logic_vector(9 downto 0);
119 
  cfg_di           : std_logic_vector(31 downto 0);
120 
  cfg_do           : std_logic_vector(31 downto 0);
121 
  cfg_byte_en_n    : std_logic_vector(3 downto 0);
122 
  cfg_wr_en_n      : std_logic;
123 
  cfg_rd_en_n      : std_logic;
124 
end record;
125 
signal cfg_rdwr_int : cfg_rdwr_sigs := (trn_clk => 'Z', trn_reset_n => 'Z', cfg_rd_wr_done_n => '1', cfg_dwaddr => (OTHERS => '0'), cfg_di => x"00000000", cfg_do => x"00000000", cfg_byte_en_n => "1111", cfg_wr_en_n => '1', cfg_rd_en_n => '1');
126 
 
127 
 
128 
file tx_file : TEXT open write_mode is "tx.dat";
129 
 
130 
procedure writeNowToTx (  text_string     : in string);
131 
 
132 
procedure writeHexToTx (  text_string     : in string;
133 
                                               hexValue        : in std_logic_vector);
134 
 
135 
procedure writeNowToScreen (text_string     : in string);
136 
 
137 
 
138 
procedure FINISH;
139 
 
140 
procedure FINISH_FAILURE;
141 
 
142 
procedure PROC_TX_SYNCHRONIZE (
143 
 
144 
  first : in INTEGER;
145 
  last_call: in INTEGER;
146 
  signal trn_lnk_up_n : in std_logic;
147 
  signal trn_tdst_rdy_n : in std_logic;
148 
  signal trn_clk : in std_logic
149 
 
150 
);
151 
 
152 
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
153 
 
154 
  tag                      : in std_logic_vector (7 downto 0);
155 
  reg_addr                 : in std_logic_vector (11 downto 0);
156 
  first_dw_be              : in std_logic_vector (3 downto 0);
157 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
158 
  signal trn_tsof_n        : out std_logic;
159 
  signal trn_teof_n        : out std_logic;
160 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
161 
  signal trn_tsrc_rdy_n    : out std_logic;
162 
  signal trn_lnk_up_n : in std_logic;
163 
  signal trn_tdst_rdy_n : in std_logic;
164 
  signal trn_clk : in std_logic
165 
 
166 
);
167 
 
168 
 
169 
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
170 
 
171 
  tag                      : in std_logic_vector (7 downto 0);
172 
  reg_addr                 : in std_logic_vector (11 downto 0);
173 
  reg_data                 : in std_logic_vector (31 downto 0);
174 
  first_dw_be              : in std_logic_vector (3 downto 0);
175 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
176 
  signal trn_tsof_n        : out std_logic;
177 
  signal trn_teof_n        : out std_logic;
178 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
179 
  signal trn_tsrc_rdy_n    : out std_logic;
180 
  signal trn_lnk_up_n : in std_logic;
181 
  signal trn_tdst_rdy_n : in std_logic;
182 
  signal trn_clk : in std_logic
183 
 
184 
);
185 
 
186 
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
187 
 
188 
  tag                      : in std_logic_vector (7 downto 0);
189 
  reg_addr                 : in std_logic_vector (11 downto 0);
190 
  first_dw_be              : in std_logic_vector (3 downto 0);
191 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
192 
  signal trn_tsof_n        : out std_logic;
193 
  signal trn_teof_n        : out std_logic;
194 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
195 
  signal trn_tsrc_rdy_n    : out std_logic;
196 
  signal trn_lnk_up_n : in std_logic;
197 
  signal trn_tdst_rdy_n : in std_logic;
198 
  signal trn_clk : in std_logic
199 
 
200 
);
201 
 
202 
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
203 
 
204 
  tag                      : in std_logic_vector (7 downto 0);
205 
  reg_addr                 : in std_logic_vector (11 downto 0);
206 
  reg_data                 : in std_logic_vector (31 downto 0);
207 
  first_dw_be              : in std_logic_vector (3 downto 0);
208 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
209 
  signal trn_tsof_n        : out std_logic;
210 
  signal trn_teof_n        : out std_logic;
211 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
212 
  signal trn_tsrc_rdy_n    : out std_logic;
213 
  signal trn_lnk_up_n : in std_logic;
214 
  signal trn_tdst_rdy_n : in std_logic;
215 
  signal trn_clk : in std_logic
216 
 
217 
);
218 
 
219 
procedure PROC_TX_MEMORY_READ_32 (
220 
 
221 
  tag                      : in std_logic_vector (7 downto 0);
222 
  tc                       : in std_logic_vector (2 downto 0);
223 
  len                      : in std_logic_vector (9 downto 0);
224 
  addr                     : in std_logic_vector (31 downto 0);
225 
  last_dw_be               : in std_logic_vector (3 downto 0);
226 
  first_dw_be              : in std_logic_vector (3 downto 0);
227 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
228 
  signal trn_tsof_n        : out std_logic;
229 
  signal trn_teof_n        : out std_logic;
230 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
231 
  signal trn_tsrc_rdy_n    : out std_logic;
232 
  signal trn_lnk_up_n : in std_logic;
233 
  signal trn_tdst_rdy_n : in std_logic;
234 
  signal trn_clk : in std_logic
235 
 
236 
 
237 
);
238 
 
239 
procedure PROC_TX_MEMORY_READ_64 (
240 
 
241 
  tag                      : in std_logic_vector (7 downto 0);
242 
  tc                       : in std_logic_vector (2 downto 0);
243 
  len                      : in std_logic_vector (9 downto 0);
244 
  addr                     : in std_logic_vector (63 downto 0);
245 
  last_dw_be               : in std_logic_vector (3 downto 0);
246 
  first_dw_be              : in std_logic_vector (3 downto 0);
247 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
248 
  signal trn_tsof_n        : out std_logic;
249 
  signal trn_teof_n        : out std_logic;
250 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
251 
  signal trn_tsrc_rdy_n    : out std_logic;
252 
  signal trn_lnk_up_n : in std_logic;
253 
  signal trn_tdst_rdy_n : in std_logic;
254 
  signal trn_clk : in std_logic
255 
 
256 
 
257 
);
258 
 
259 
procedure PROC_TX_MEMORY_WRITE_32 (
260 
 
261 
  tag                         : in std_logic_vector (7 downto 0);
262 
  tc                          : in std_logic_vector (2 downto 0);
263 
  len                         : in std_logic_vector (9 downto 0);
264 
  addr                        : in std_logic_vector (31 downto 0);
265 
  last_dw_be                  : in std_logic_vector (3 downto 0);
266 
  first_dw_be                 : in std_logic_vector (3 downto 0);
267 
  ep                          : in std_logic;
268 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
269 
  signal trn_tsof_n           : out std_logic;
270 
  signal trn_teof_n           : out std_logic;
271 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
272 
  signal trn_tsrc_rdy_n       : out std_logic;
273 
  signal trn_terrfwd_n        : out std_logic;
274 
  signal trn_lnk_up_n : in std_logic;
275 
  signal trn_tdst_rdy_n : in std_logic;
276 
  signal trn_clk : in std_logic
277 
 
278 
 
279 
);
280 
 
281 
 
282 
procedure PROC_TX_MEMORY_WRITE_64 (
283 
 
284 
  tag                         : in std_logic_vector (7 downto 0);
285 
  tc                          : in std_logic_vector (2 downto 0);
286 
  len                         : in std_logic_vector (9 downto 0);
287 
  addr                        : in std_logic_vector (63 downto 0);
288 
  last_dw_be                  : in std_logic_vector (3 downto 0);
289 
  first_dw_be                 : in std_logic_vector (3 downto 0);
290 
  ep                          : in std_logic;
291 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
292 
  signal trn_tsof_n           : out std_logic;
293 
  signal trn_teof_n           : out std_logic;
294 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
295 
  signal trn_tsrc_rdy_n       : out std_logic;
296 
  signal trn_terrfwd_n        : out std_logic;
297 
  signal trn_lnk_up_n : in std_logic;
298 
  signal trn_tdst_rdy_n : in std_logic;
299 
  signal trn_clk : in std_logic
300 
 
301 
 
302 
);
303 
 
304 
 
305 
procedure PROC_TX_COMPLETION (
306 
 
307 
  tag                      : in std_logic_vector (7 downto 0);
308 
  tc                       : in std_logic_vector (2 downto 0);
309 
  len                      : in std_logic_vector (9 downto 0);
310 
  comp_status              : in std_logic_vector (2 downto 0);
311 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
312 
  signal trn_tsof_n        : out std_logic;
313 
  signal trn_teof_n        : out std_logic;
314 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
315 
  signal trn_tsrc_rdy_n    : out std_logic;
316 
  signal trn_lnk_up_n : in std_logic;
317 
  signal trn_tdst_rdy_n : in std_logic;
318 
  signal trn_clk : in std_logic
319 
 
320 
);
321 
 
322 
procedure PROC_TX_COMPLETION_DATA (
323 
 
324 
  tag                      : in std_logic_vector (7 downto 0);
325 
  tc                       : in std_logic_vector (2 downto 0);
326 
  len                      : in std_logic_vector (9 downto 0);
327 
  byte_count               : in std_logic_vector (11 downto 0);
328 
  lower_addr               : in std_logic_vector (6 downto 0);
329 
  comp_status              : in std_logic_vector (2 downto 0);
330 
  ep                       : in std_logic;
331 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
332 
  signal trn_tsof_n        : out std_logic;
333 
  signal trn_teof_n        : out std_logic;
334 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
335 
  signal trn_tsrc_rdy_n    : out std_logic;
336 
  signal trn_terrfwd_n     : out std_logic;
337 
  signal trn_lnk_up_n : in std_logic;
338 
  signal trn_tdst_rdy_n : in std_logic;
339 
  signal trn_clk : in std_logic
340 
 
341 
);
342 
 
343 
procedure PROC_TX_MESSAGE (
344 
 
345 
  tag                      : in std_logic_vector (7 downto 0);
346 
  tc                       : in std_logic_vector (2 downto 0);
347 
  len                      : in std_logic_vector (9 downto 0);
348 
  data                     : in std_logic_vector (63 downto 0);
349 
  message_rtg              : in std_logic_vector (2 downto 0);
350 
  message_code             : in std_logic_vector (7 downto 0);
351 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
352 
  signal trn_tsof_n        : out std_logic;
353 
  signal trn_teof_n        : out std_logic;
354 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
355 
  signal trn_tsrc_rdy_n    : out std_logic;
356 
  signal trn_lnk_up_n : in std_logic;
357 
  signal trn_tdst_rdy_n : in std_logic;
358 
  signal trn_clk : in std_logic
359 
 
360 
);
361 
 
362 
procedure PROC_TX_MESSAGE_DATA (
363 
 
364 
  tag                      : in std_logic_vector (7 downto 0);
365 
  tc                       : in std_logic_vector (2 downto 0);
366 
  len                      : in std_logic_vector (9 downto 0);
367 
  data                     : in std_logic_vector (63 downto 0);
368 
  message_rtg              : in std_logic_vector (2 downto 0);
369 
  message_code             : in std_logic_vector (7 downto 0);
370 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
371 
  signal trn_tsof_n        : out std_logic;
372 
  signal trn_teof_n        : out std_logic;
373 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
374 
  signal trn_tsrc_rdy_n    : out std_logic;
375 
  signal trn_lnk_up_n : in std_logic;
376 
  signal trn_tdst_rdy_n : in std_logic;
377 
  signal trn_clk : in std_logic
378 
 
379 
);
380 
 
381 
procedure PROC_TX_IO_READ (
382 
 
383 
  tag                      : in std_logic_vector (7 downto 0);
384 
  addr                     : in std_logic_vector (31 downto 0);
385 
  first_dw_be              : in std_logic_vector (3 downto 0);
386 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
387 
  signal trn_tsof_n        : out std_logic;
388 
  signal trn_teof_n        : out std_logic;
389 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
390 
  signal trn_tsrc_rdy_n    : out std_logic;
391 
  signal trn_lnk_up_n : in std_logic;
392 
  signal trn_tdst_rdy_n : in std_logic;
393 
  signal trn_clk : in std_logic
394 
 
395 
);
396 
 
397 
procedure PROC_TX_IO_WRITE (
398 
 
399 
  tag                      : in std_logic_vector (7 downto 0);
400 
  addr                     : in std_logic_vector (31 downto 0);
401 
  first_dw_be              : in std_logic_vector (3 downto 0);
402 
  data                     : in std_logic_vector(31 downto 0);
403 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
404 
  signal trn_tsof_n        : out std_logic;
405 
  signal trn_teof_n        : out std_logic;
406 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
407 
  signal trn_tsrc_rdy_n    : out std_logic;
408 
  signal trn_lnk_up_n : in std_logic;
409 
  signal trn_tdst_rdy_n : in std_logic;
410 
  signal trn_clk : in std_logic
411 
 
412 
);
413 
 
414 
procedure PROC_USR_DATA_SETUP_SEQ;
415 
 
416 
procedure PROC_TX_CLK_EAT  (
417 
 
418 
  clock_count : in INTEGER;
419 
  signal trn_clk : in std_logic
420 
 
421 
);
422 
 
423 
procedure PROC_SET_READ_DATA  (
424 
 
425 
  be     : in std_logic_vector(3 downto 0);
426 
  data   : in std_logic_vector(31 downto 0)
427 
 
428 
);
429 
 
430 
procedure PROC_WAIT_FOR_READ_DATA  (
431 
 
432 
  signal tx_rx_read_data_valid    : out std_logic;
433 
  signal rx_tx_read_data_valid    : in std_logic;
434 
  signal rx_tx_read_data : in std_logic_vector(31 downto 0);
435 
  signal trn_clk : in std_logic
436 
 
437 
);
438 
 
439 
procedure PROC_DISPLAY_PCIE_MAP  (
440 
 
441 
  BAR            : THIRTY_THREE_BIT_ARRAY;
442 
  BAR_ENABLED    : ENABLE_ARRAY;
443 
  BAR_RANGE      : DWORD_ARRAY
444 
 
445 
);
446 
 
447 
procedure PROC_BUILD_PCIE_MAP
448 
;
449 
 
450 
procedure PROC_BAR_SCAN  (
451 
 
452 
  signal tx_rx_read_data_valid : out std_logic;
453 
  signal rx_tx_read_data_valid : in std_logic;
454 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
455 
  signal trn_td_c : out std_logic_vector(63 downto 0);
456 
  signal trn_tsof_n : out std_logic;
457 
  signal trn_teof_n : out std_logic;
458 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
459 
  signal trn_tsrc_rdy_n : out std_logic;
460 
  signal trn_lnk_up_n : in std_logic;
461 
  signal trn_tdst_rdy_n : in std_logic;
462 
  signal trn_clk : in std_logic
463 
 
464 
);
465 
 
466 
procedure PROC_BAR_PROGRAM  (
467 
 
468 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
469 
  signal trn_tsof_n        : out std_logic;
470 
  signal trn_teof_n        : out std_logic;
471 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
472 
  signal trn_tsrc_rdy_n    : out std_logic;
473 
  signal trn_lnk_up_n : in std_logic;
474 
  signal trn_tdst_rdy_n : in std_logic;
475 
  signal trn_clk : in std_logic
476 
 
477 
);
478 
 
479 
procedure PROC_BAR_INIT  (
480 
 
481 
  signal tx_rx_read_data_valid : out std_logic;
482 
  signal rx_tx_read_data_valid : in std_logic;
483 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
484 
  signal trn_td_c : out std_logic_vector(63 downto 0);
485 
  signal trn_tsof_n : out std_logic;
486 
  signal trn_teof_n : out std_logic;
487 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
488 
  signal trn_tsrc_rdy_n : out std_logic;
489 
  signal trn_lnk_up_n : in std_logic;
490 
  signal trn_tdst_rdy_n : in std_logic;
491 
  signal trn_clk : in std_logic
492 
 
493 
 );
494 
 
495 
procedure PROC_SYSTEM_INITIALIZATION(
496 
     signal trn_reset_n: in std_logic;
497 
     signal trn_lnk_up_n: in std_logic );
498 
 
499 
 
500 
procedure PROC_READ_CFG_DW (
501 
  addr                : in    std_logic_vector(9 downto 0);
502 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
503 
);
504 
 
505 
procedure PROC_WRITE_CFG_DW (
506 
  addr                : in    std_logic_vector(9 downto 0);
507 
  data                : in    std_logic_vector(31 downto 0);
508 
  byte_en_n           : in    std_logic_vector(3 downto 0);
509 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
510 
);
511 
 
512 
end package test_interface;
513 
 
514 
 
515 
 
516 
-- Package Body
517 
 
518 
package body test_interface is
519 
 
520 
--************************************************************
521 
--     Proc : writeNowToTx
522 
--     Inputs : Text String
523 
--     Outputs : None
524 
--     Description : Displays text string to Tx file pre-appended with
525 
--         current simulation time..
526 
--*************************************************************
527 
 
528 
procedure writeNowToTx (
529 
 
530 
  text_string     : in string
531 
 
532 
) is
533 
 
534 
  variable L      : line;
535 
 
536 
begin
537 
 
538 
  write (L, String'("[ "));
539 
  write (L, now);
540 
  write (L, String'(" ] : "));
541 
  write (L, text_string);
542 
  writeline (tx_file, L);
543 
 
544 
end writeNowToTx;
545 
 
546 
 
547 
--************************************************************
548 
--     Proc : writeHexToTx
549 
--     Inputs : hex value with bit width that is multiple of 4
550 
--     Outputs : None
551 
--     Description : Displays nibble aligned hex value to Tx file
552 
--
553 
--*************************************************************
554 
 
555 
procedure writeHexToTx (
556 
 
557 
  text_string     : in string;
558 
  hexValue        : in std_logic_vector
559 
 
560 
) is
561 
 
562 
  variable L      : line;
563 
 
564 
begin
565 
 
566 
  write (L, text_string);
567 
  hwrite(L, hexValue);
568 
  writeline (tx_file, L);
569 
 
570 
end writeHexToTx;
571 
 
572 
 
573 
--************************************************************
574 
--     Proc : writeNowToScreen
575 
--     Inputs : Text String
576 
--     Outputs : None
577 
--     Description : Displays current simulation time and text string to
578 
--          standard output.
579 
--*************************************************************
580 
 
581 
procedure writeNowToScreen (
582 
 
583 
  text_string     : in string
584 
 
585 
) is
586 
 
587 
  variable L      : line;
588 
 
589 
begin
590 
 
591 
  write (L, String'("[ "));
592 
  write (L, now);
593 
  write (L, String'(" ] : "));
594 
  write (L, text_string);
595 
  writeline (output, L);
596 
 
597 
end writeNowToScreen;
598 
 
599 
 
600 
 
601 
--************************************************************
602 
--     Proc : PROC_READ_DATA
603 
--     Inputs : None
604 
--     Outputs : None
605 
--     Description : Consume clocks.
606 
--   *************************************************************/
607 
 
608 
procedure PROC_READ_DATA (
609 
 
610 
  last                  : in INTEGER;
611 
  trn_d                 : in std_logic_vector (63 downto 0);
612 
  trn_rem               : in std_logic_vector (7 downto 0)
613 
 
614 
) is
615 
 
616 
  variable i            : INTEGER;
617 
  variable data_byte    : std_logic_vector (7 downto 0);
618 
  variable remain       : INTEGER;
619 
  variable hi_index     : INTEGER;
620 
  variable low_index    : INTEGER;
621 
  variable my_line      : line;
622 
 
623 
begin
624 
 
625 
  hi_index := 63;
626 
  low_index := 56;
627 
  if (last = 1) then
628 
 
629 
    if (trn_rem = X"0F") then
630 
 
631 
      remain := 4;
632 
 
633 
    else remain := 8;
634 
 
635 
    end if;
636 
 
637 
  else
638 
 
639 
    remain := 8;
640 
 
641 
  end if;
642 
  for i in 0 to (remain - 1) loop
643 
 
644 
    data_byte := trn_d( hi_index downto low_index);
645 
    hi_index := hi_index - 8;
646 
    low_index := low_index - 8;
647 
    frame_store_tx(frame_store_tx_idx) := data_byte;
648 
    frame_store_tx_idx := frame_store_tx_idx + 1;
649 
 
650 
  end loop;
651 
 
652 
end PROC_READ_DATA;
653 
 
654 
 
655 
--************************************************************
656 
--  Proc : PROC_DECIPHER_FRAME
657 
--  Inputs : None
658 
-- Outputs : fmt, tlp_type, traffic_class, td, ep, attr, length
659 
--  Description : Deciphers frame
660 
--  *************************************************************/
661 
 
662 
 
663 
procedure PROC_DECIPHER_FRAME (
664 
 
665 
  fmt                   : out std_logic_vector (1 downto 0);
666 
  tlp_type              : out std_logic_vector (4 downto 0);
667 
  traffic_class         : out std_logic_vector (2 downto 0);
668 
  td                    : out std_logic;
669 
  ep                    : out std_logic;
670 
  attr                  : out std_logic_vector (1 downto 0);
671 
  length                : out std_logic_vector (9 downto 0)
672 
 
673 
) is
674 
 
675 
begin
676 
 
677 
  fmt := frame_store_tx(0)(6 downto 5);
678 
  tlp_type := frame_store_tx(0)(4 downto 0);
679 
  traffic_class := frame_store_tx(1)(6 downto 4);
680 
  td := frame_store_tx(2)(7);
681 
  ep := frame_store_tx(2)(6);
682 
  attr := frame_store_tx(2)(5 downto 4);
683 
  length(9 downto 8) := frame_store_tx(2)(1 downto 0);
684 
  length(7 downto 0) := frame_store_tx(3);
685 
 
686 
end PROC_DECIPHER_FRAME;
687 
 
688 
 
689 
-- ************************************************************
690 
--  Proc : PROC_3DW
691 
--  Inputs : fmt, type, traffic_class, td, ep, attr, length,
692 
--  payload,
693 
--  Outputs : None
694 
--  Description : Gets variables and prints frame
695 
--  *************************************************************/
696 
 
697 
 
698 
procedure PROC_3DW (
699 
 
700 
  fmt              : in std_logic_vector (1 downto 0);
701 
  tlp_type         : in std_logic_vector (4 downto 0);
702 
  traffic_class    : in std_logic_vector (2 downto 0);
703 
  td               : in std_logic;
704 
  ep               : in std_logic;
705 
  attr             : in std_logic_vector (1 downto 0);
706 
  length           : in std_logic_vector (9 downto 0);
707 
  payload          : in INTEGER
708 
 
709 
) is
710 
 
711 
  variable requester_id         : std_logic_vector (15 downto 0);
712 
  variable tag                  : std_logic_vector (7 downto 0);
713 
  variable byte_enables         : std_logic_vector (7 downto 0);
714 
  variable address_low          : std_logic_vector (31 downto 0);
715 
  variable completer_id         : std_logic_vector (15 downto 0);
716 
  variable register_address     : std_logic_vector (9 downto 0);
717 
  variable completion_status    : std_logic_vector (2 downto 0);
718 
  variable i                    : INTEGER;
719 
  variable L                    : line;
720 
  variable fmt_type             : std_logic_vector (6 downto 0);
721 
 
722 
begin
723 
 
724 
  writeHexToTx (String'("     Traffic Class: 0x"), '0' & traffic_class);
725 
  write (L, String'("     TD: ")); write(L,  td); writeline (tx_file, L);
726 
  write (L, String'("     EP: ")); write(L, ep); writeline (tx_file, L);
727 
  writeHexToTx (String'("     Attributes: 0x"), "00" & attr);
728 
  writeHexToTx (String'("     Length: 0x"), "00" & length);
729 
 
730 
  fmt_type := fmt & tlp_type;
731 
  case (fmt_type) is
732 
 
733 
    when PCI_EXP_CFG_READ0 | PCI_EXP_CFG_WRITE0 =>
734 
 
735 
      requester_id := frame_store_tx(4) & frame_store_tx(5);
736 
      tag := frame_store_tx(6);
737 
      byte_enables := frame_store_tx(7);
738 
      completer_id := frame_store_tx(8) & frame_store_tx(9);
739 
      register_address(9 downto 8) := frame_store_tx(10)(1 downto 0);
740 
      register_address(7 downto 0) := frame_store_tx(11);
741 
 
742 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
743 
      writeHexToTx ( String'("     Tag: 0x"), tag);
744 
      writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
745 
      writeHexToTx ( String'("     Completer Id: 0x"), completer_id);
746 
      writeHexToTx ( String'("     Register Address: 0x"), "00" & register_address);
747 
 
748 
      if (payload = 1) then
749 
 
750 
        write (L, String'("")); writeline(tx_file, L);
751 
        for i in 12 to (frame_store_tx_idx - 1) loop
752 
 
753 
          writeHexToTx ( String'("     0x"), frame_store_tx(i));
754 
 
755 
        end loop;
756 
 
757 
      end if;
758 
      write (L, String'("")); writeline(tx_file, L);
759 
 
760 
    when PCI_EXP_COMPLETION_WO_DATA | PCI_EXP_COMPLETION_DATA=>
761 
 
762 
      completer_id := frame_store_tx(4) & frame_store_tx(5);
763 
      completion_status(2 downto 0) := frame_store_tx(6)(7 downto 5);
764 
      requester_id := frame_store_tx(8) & frame_store_tx(9);
765 
      tag := frame_store_tx(10);
766 
 
767 
      writeHexToTx ( String'("     Completer Id: 0x"), completer_id);
768 
      writeHexToTx ( String'("     Completion Status: 0x"), '0' & completion_status);
769 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
770 
      writeHexToTx ( String'("     Tag: 0x"), tag);
771 
 
772 
      if (payload = 1) then
773 
 
774 
        write (L, String'("")); writeline(tx_file, L);
775 
        for i in 12 to (frame_store_tx_idx - 1) loop
776 
 
777 
                    writeHexToTx ( String'("     0x"), frame_store_tx(i));
778 
 
779 
        end loop;
780 
 
781 
      end if;
782 
      write (L, String'("")); writeline(tx_file, L);
783 
 
784 
    when others =>
785 
 
786 
      requester_id := frame_store_tx(4) & frame_store_tx(5);
787 
      tag := frame_store_tx(6);
788 
      byte_enables := frame_store_tx(7);
789 
      address_low(31 downto 24) := frame_store_tx(8);
790 
      address_low(23 downto 16) := frame_store_tx(9);
791 
      address_low(15 downto 8) := frame_store_tx(10);
792 
      address_low( 7 downto 0) := frame_store_tx(11);
793 
 
794 
      writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
795 
      writeHexToTx ( String'("     Tag: 0x"), tag);
796 
      writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
797 
      writeHexToTx ( String'("     Address Low: 0x"), address_low);
798 
 
799 
      if (payload = 1) then
800 
 
801 
        write (L, String'("")); writeline(tx_file, L);
802 
        for i in 12 to (frame_store_tx_idx - 1) loop
803 
 
804 
          writeHexToTx ( String'("     0x"), frame_store_tx(i));
805 
 
806 
        end loop;
807 
 
808 
      end if;
809 
      write (L, String'("")); writeline(tx_file, L);
810 
 
811 
  end  case;
812 
 
813 
end PROC_3DW;
814 
 
815 
 
816 
-- ************************************************************
817 
--  Proc : PROC_4DW
818 
--  Inputs : fmt, type, traffic_class, td, ep, attr, length
819 
--  payload
820 
--  Outputs : None
821 
--  Description : Gets variables and prints frame
822 
--  *************************************************************/
823 
 
824 
 
825 
procedure PROC_4DW (
826 
 
827 
  fmt              : in std_logic_vector (1 downto 0);
828 
  tlp_type         : in std_logic_vector (4 downto 0);
829 
  traffic_class    : in std_logic_vector (2 downto 0);
830 
  td               : in std_logic;
831 
  ep               : in std_logic;
832 
  attr             : in std_logic_vector (1 downto 0);
833 
  length           : in std_logic_vector (9 downto 0);
834 
  payload          : in INTEGER
835 
 
836 
) is
837 
 
838 
  variable requester_id    : std_logic_vector (15 downto 0);
839 
  variable tag             : std_logic_vector (7 downto 0);
840 
  variable byte_enables    : std_logic_vector (7 downto 0);
841 
  variable message_code    : std_logic_vector (7 downto 0);
842 
  variable address_high    : std_logic_vector (31 downto 0);
843 
  variable address_low     : std_logic_vector (31 downto 0);
844 
  variable msg_type        : std_logic_vector (2 downto 0);
845 
  variable i               : INTEGER;
846 
  variable L               : line;
847 
  variable fmt_type        : std_logic_vector (6 downto 0);
848 
 
849 
begin
850 
 
851 
  writeHexToTx (String'("     Traffic Class: 0x"), '0' & traffic_class);
852 
  write (L, String'("     TD: ")); write(L,  td); writeline (tx_file, L);
853 
  write (L, String'("     EP: ")); write(L, ep); writeline (tx_file, L);
854 
  writeHexToTx (String'("     Attributes: 0x"), "00" & attr);
855 
  writeHexToTx (String'("     Length: 0x"), "00" & length);
856 
 
857 
  requester_id := frame_store_tx(4) & frame_store_tx(5);
858 
  tag := frame_store_tx(6);
859 
  byte_enables := frame_store_tx(7);
860 
  message_code := frame_store_tx(7);
861 
  address_high(31 downto 24) := frame_store_tx(8);
862 
  address_high(23 downto 16) := frame_store_tx(9) ;
863 
  address_high(15 downto 8) := frame_store_tx(10);
864 
  address_high(7 downto 0) := frame_store_tx(11);
865 
  address_low(31 downto 24) := frame_store_tx(12);
866 
  address_low(23 downto 16) := frame_store_tx(13);
867 
  address_low(15 downto 8) := frame_store_tx(14) ;
868 
  address_low(7 downto 0) := frame_store_tx(15);
869 
 
870 
  writeHexToTx ( String'("     Requester Id: 0x"), requester_id);
871 
  writeHexToTx ( String'("     Tag: 0x"), tag);
872 
 
873 
  fmt_type := fmt & tlp_type;
874 
 
875 
  if ((fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA)
876 
     or (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA)) then
877 
 
878 
    msg_type := tlp_type(2 downto 0);
879 
    writeHexToTx ( String'("     Message Type: 0x"), '0' & msg_type);
880 
    writeHexToTx ( String'("     Message Code: 0x"), message_code);
881 
    writeHexToTx ( String'("     Address High: 0x"), address_high);
882 
    writeHexToTx ( String'("     Address Low:  0x"), address_low);
883 
 
884 
    if (payload = 1) then
885 
 
886 
      write (L, String'("")); writeline(tx_file, L);
887 
      for i in 16 to (frame_store_tx_idx - 1) loop
888 
 
889 
        writeHexToTx ( String'("     0x"), frame_store_tx(i));
890 
 
891 
      end loop;
892 
 
893 
    end if;
894 
    write (L, String'("")); writeline(tx_file, L);
895 
 
896 
  else
897 
 
898 
    case (fmt_type) is
899 
 
900 
      when PCI_EXP_MEM_READ64 | PCI_EXP_MEM_WRITE64 =>
901 
 
902 
        writeHexToTx ( String'("     Last and First Byte Enables: 0x"), byte_enables);
903 
        writeHexToTx ( String'("     Address High: 0x"), address_high);
904 
        writeHexToTx ( String'("     Address Low:  0x"), address_low);
905 
 
906 
        if (payload = 1) then
907 
 
908 
          write (L, String'("")); writeline(tx_file, L);
909 
          for i in 16 to (frame_store_tx_idx - 1) loop
910 
 
911 
            writeHexToTx ( String'("     0x"), frame_store_tx(i));
912 
 
913 
          end loop;
914 
 
915 
        end if;
916 
 
917 
        write (L, String'("")); writeline(tx_file, L);
918 
 
919 
      when others =>
920 
 
921 
        write (L, String'(": Not a vaild frame")); writeline (tx_file, L); write (L, String'("")); writeline(tx_file, L);
922 
        assert (false)
923 
          report "Simulation Ended"
924 
          severity failure;
925 
 
926 
    end  case; -- (fmt_type)
927 
 
928 
  end if;
929 
 
930 
end PROC_4DW;
931 
 
932 
 
933 
--************************************************************
934 
--  Proc : PROC_PARSE_FRAME
935 
--  Inputs : None
936 
--  Outputs : None
937 
--  Description : Parse frame data
938 
--  *************************************************************/
939 
 
940 
procedure PROC_PARSE_FRAME is
941 
 
942 
  variable fmt                  : std_logic_vector (1 downto 0);
943 
  variable tlp_type             : std_logic_vector (4 downto 0);
944 
  variable traffic_class        : std_logic_vector (2 downto 0);
945 
  variable td                   : std_logic;
946 
  variable ep                   : std_logic;
947 
  variable attr                 : std_logic_vector (1 downto 0);
948 
  variable length               : std_logic_vector (9 downto 0);
949 
  variable payload              : INTEGER;
950 
  variable reqester_id          : std_logic_vector(15 downto 0);
951 
  variable completer_id         : std_logic_vector(15 downto 0);
952 
  variable tag                  : std_logic_vector(7 downto 0);
953 
  variable byte_enables         : std_logic_vector(7 downto 0);
954 
  variable message_code         : std_logic_vector(7 downto 0);
955 
  variable address_low          : std_logic_vector(31 downto 0);
956 
  variable address_high         : std_logic_vector(31 downto 0);
957 
  variable register_address     : std_logic_vector (9 downto 0);
958 
  variable completion_status    : std_logic_vector (2 downto 0);
959 
  variable log_file_ptr         : std_logic_vector (31 downto 0);
960 
  variable frame_store_idx      : INTEGER;
961 
  variable fmt_type             : std_logic_vector (6 downto 0);
962 
  variable L                    : line;
963 
 
964 
begin
965 
 
966 
  writeNowToScreen ( String'("PROC_PARSE_FRAME on Transmit"));
967 
  PROC_DECIPHER_FRAME (fmt, tlp_type, traffic_class, td, ep, attr, length);
968 
 
969 
  -- decode the packets received based on fmt and type
970 
  fmt_type := fmt & tlp_type;
971 
 
972 
  if (fmt_type(6 downto 3) = PCI_EXP_MSG_NODATA) then
973 
 
974 
    writeNowToTx("Message With No Data Frame");
975 
    payload := 0;
976 
    PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
977 
 
978 
  elsif (fmt_type(6 downto 3) = PCI_EXP_MSG_DATA) then
979 
 
980 
    writeNowToTx("Message With Data Frame");
981 
    payload := 1;
982 
    PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
983 
 
984 
  else
985 
 
986 
    case (fmt_type) is
987 
 
988 
      when PCI_EXP_MEM_READ32 =>
989 
 
990 
        writeNowToTx("Memory Read-32 Frame");
991 
        payload := 0;
992 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
993 
 
994 
      when PCI_EXP_IO_READ =>
995 
 
996 
        writeNowToTx("IO Read Frame");
997 
        payload := 0;
998 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
999 
 
1000 
      when PCI_EXP_CFG_READ0 =>
1001 
 
1002 
        writeNowToTx("Config Read Type 0 Frame");
1003 
        payload := 0;
1004 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1005 
 
1006 
      when PCI_EXP_COMPLETION_WO_DATA =>
1007 
 
1008 
        writeNowToTx("Completion Without Data Frame");
1009 
        payload := 0;
1010 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1011 
 
1012 
      when PCI_EXP_MEM_READ64 =>
1013 
 
1014 
        writeNowToTx("Memory Read-64 Frame");
1015 
        payload := 0;
1016 
        PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1017 
 
1018 
      when PCI_EXP_MEM_WRITE32 =>
1019 
 
1020 
        writeNowToTx("Memory Write-32 Frame");
1021 
        payload := 1;
1022 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1023 
 
1024 
      when PCI_EXP_IO_WRITE =>
1025 
 
1026 
        writeNowToTx("IO Write Frame");
1027 
        payload := 1;
1028 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1029 
 
1030 
      when PCI_EXP_CFG_WRITE0 =>
1031 
 
1032 
        writeNowToTx("Config Write Type 0 Frame");
1033 
        payload := 1;
1034 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1035 
 
1036 
      when PCI_EXP_COMPLETION_DATA =>
1037 
 
1038 
        writeNowToTx("Completion With Data Frame");
1039 
        payload := 1;
1040 
        PROC_3DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1041 
 
1042 
      when PCI_EXP_MEM_WRITE64 =>
1043 
 
1044 
        writeNowToTx("Memory Write-64 Frame");
1045 
        payload := 1;
1046 
        PROC_4DW(fmt, tlp_type, traffic_class, td, ep, attr, length, payload);
1047 
 
1048 
      when others =>
1049 
 
1050 
        writeNowToTx("Not a vaild frame. fmt_type = ");
1051 
        write (L, fmt_type);
1052 
        writeline (tx_file, L);
1053 
        assert (false)
1054 
          report "Simulation Ended"
1055 
          severity failure;
1056 
 
1057 
    end  case;
1058 
 
1059 
  end if;
1060 
 
1061 
  frame_store_tx_idx := 0; -- reset frame pointer
1062 
 
1063 
end PROC_PARSE_FRAME;
1064 
 
1065 
--************************************************************
1066 
--  Proc : FINISH
1067 
--  Inputs : None
1068 
--  Outputs : None
1069 
--  Description : Ends simulation with successful message
1070 
--*************************************************************/
1071 
 
1072 
procedure FINISH is
1073 
 
1074 
  variable  L : line;
1075 
 
1076 
begin
1077 
 
1078 
  assert (false)
1079 
    report "Simulation Stopped."
1080 
    severity failure;
1081 
 
1082 
end FINISH;
1083 
 
1084 
 
1085 
--************************************************************
1086 
--  Proc : FINISH_FAILURE
1087 
--  Inputs : None
1088 
--  Outputs : None
1089 
--  Description : Ends simulation with failure message
1090 
--*************************************************************/
1091 
 
1092 
procedure FINISH_FAILURE is
1093 
 
1094 
  variable  L : line;
1095 
 
1096 
begin
1097 
 
1098 
  assert (false)
1099 
    report "Simulation Ended With 1 or more failures"
1100 
    severity failure;
1101 
 
1102 
end FINISH_FAILURE;
1103 
 
1104 
 
1105 
--************************************************************
1106 
--    Proc : PROC_TX_CLK_EAT
1107 
--    Inputs : None
1108 
--    Outputs : None
1109 
--    Description : Consume clocks.
1110 
--*************************************************************/
1111 
 
1112 
procedure PROC_TX_CLK_EAT  (
1113 
 
1114 
  clock_count : in INTEGER;
1115 
  signal trn_clk : in std_logic
1116 
 
1117 
) is
1118 
 
1119 
  variable i  : INTEGER;
1120 
 
1121 
begin
1122 
 
1123 
  for i in 0 to (clock_count - 1) loop
1124 
 
1125 
    wait until (trn_clk'event and trn_clk = '1');
1126 
 
1127 
  end loop;
1128 
 
1129 
end PROC_TX_CLK_EAT;
1130 
 
1131 
 
1132 
--************************************************************
1133 
--    Proc : PROC_TX_SYNCHRONIZE
1134 
--    Inputs : first_, last_call_
1135 
--    Outputs : None
1136 
--    Description : Synchronize with tx clock and handshake signals
1137 
--*************************************************************/
1138 
 
1139 
procedure PROC_TX_SYNCHRONIZE (
1140 
 
1141 
  first : in INTEGER;
1142 
  last_call: in INTEGER;
1143 
  signal trn_lnk_up_n : in std_logic;
1144 
  signal trn_tdst_rdy_n : in std_logic;
1145 
  signal trn_clk : in std_logic
1146 
 
1147 
) is
1148 
 
1149 
  variable last  : INTEGER;
1150 
 
1151 
begin
1152 
 
1153 
  assert (trn_lnk_up_n = '0')
1154 
    report "TX Trn interface is MIA"
1155 
    severity failure;
1156 
 
1157 
  wait until (trn_clk'event and trn_clk = '1');
1158 
 
1159 
  if ((trn_tdst_rdy_n = '1') and (first = 1)) then
1160 
 
1161 
    while (trn_tdst_rdy_n = '1') loop
1162 
 
1163 
      wait until (trn_clk'event and trn_clk = '1');
1164 
 
1165 
    end loop;
1166 
 
1167 
  end if;
1168 
  if (first = 1) then
1169 
 
1170 
    if (trn_trem_n_c = X"00") then --"00000000") then
1171 
 
1172 
      last := 0;
1173 
 
1174 
    else
1175 
 
1176 
      last := 1;
1177 
 
1178 
    end if;
1179 
 
1180 
    PROC_READ_DATA(last, trn_td_c, trn_trem_n_c);
1181 
 
1182 
  end if;
1183 
  if (last_call = 1) then
1184 
 
1185 
    PROC_PARSE_FRAME;
1186 
 
1187 
  end if;
1188 
 
1189 
end PROC_TX_SYNCHRONIZE;
1190 
 
1191 
 
1192 
 
1193 
--************************************************************
1194 
--    Proc : PROC_TX_TYPE0_CONFIGURATION_READ
1195 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1196 
--    Outputs : Transaction Tx Interface Signaling
1197 
--    Description : Generates a Type 0 Configuration Read TLP
1198 
--*************************************************************/
1199 
 
1200 
procedure PROC_TX_TYPE0_CONFIGURATION_READ (
1201 
 
1202 
  tag                      : in std_logic_vector (7 downto 0);
1203 
  reg_addr                 : in std_logic_vector (11 downto 0);
1204 
  first_dw_be              : in std_logic_vector (3 downto 0);
1205 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1206 
  signal trn_tsof_n        : out std_logic;
1207 
  signal trn_teof_n        : out std_logic;
1208 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1209 
  signal trn_tsrc_rdy_n    : out std_logic;
1210 
  signal trn_lnk_up_n : in std_logic;
1211 
  signal trn_tdst_rdy_n : in std_logic;
1212 
  signal trn_clk : in std_logic
1213 
 
1214 
) is
1215 
 
1216 
begin
1217 
 
1218 
  assert (trn_lnk_up_n = '0')
1219 
    report "TX Trn interface is MIA"
1220 
    severity failure;
1221 
 
1222 
 
1223 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1224 
 
1225 
  trn_td_c          <= '0' &
1226 
                       "00" &
1227 
                       "00100" &
1228 
                       '0' &
1229 
                       "000" &
1230 
                       "0000" &
1231 
                       '0' &
1232 
                       '0' &
1233 
                       "00" &
1234 
                       "00" &
1235 
                       "0000000001" &
1236 
                       COMPLETER_ID_CFG &
1237 
                       tag(7 downto 0) &
1238 
                       "0000" &
1239 
                       first_dw_be(3 downto 0);
1240 
  trn_tsof_n        <= '0';
1241 
  trn_teof_n        <= '1';
1242 
  trn_trem_n_c      <= X"00";
1243 
  trn_tsrc_rdy_n    <= '0';
1244 
 
1245 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1246 
 
1247 
  trn_td_c          <= COMPLETER_ID_CFG &
1248 
                       "0000" &
1249 
                       reg_addr(11 downto 2) &
1250 
                       "00" &
1251 
                       X"00000000";
1252 
  trn_tsof_n        <= '1';
1253 
  trn_teof_n        <= '0';
1254 
  trn_trem_n_c      <= X"0F";
1255 
  trn_tsrc_rdy_n    <= '0';
1256 
 
1257 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1258 
 
1259 
  trn_teof_n        <= '1';
1260 
  trn_trem_n_c      <= X"00";
1261 
  trn_tsrc_rdy_n    <= '1';
1262 
 
1263 
end PROC_TX_TYPE0_CONFIGURATION_READ;
1264 
 
1265 
 
1266 
--************************************************************
1267 
--    Proc : PROC_TX_TYPE0_CONFIGURATION_WRITE
1268 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1269 
--    Outputs : Transaction Tx Interface Signaling
1270 
--    Description : Generates a Type 0 Configuration Write TLP
1271 
--*************************************************************/
1272 
 
1273 
procedure PROC_TX_TYPE0_CONFIGURATION_WRITE (
1274 
 
1275 
  tag                      : in std_logic_vector (7 downto 0);
1276 
  reg_addr                 : in std_logic_vector (11 downto 0);
1277 
  reg_data                 : in std_logic_vector (31 downto 0);
1278 
  first_dw_be              : in std_logic_vector (3 downto 0);
1279 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1280 
  signal trn_tsof_n        : out std_logic;
1281 
  signal trn_teof_n        : out std_logic;
1282 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1283 
  signal trn_tsrc_rdy_n    : out std_logic;
1284 
  signal trn_lnk_up_n : in std_logic;
1285 
  signal trn_tdst_rdy_n : in std_logic;
1286 
  signal trn_clk : in std_logic
1287 
 
1288 
) is
1289 
 
1290 
begin
1291 
 
1292 
  assert (trn_lnk_up_n = '0')
1293 
    report "TX Trn interface is MIA"
1294 
    severity failure;
1295 
 
1296 
 
1297 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1298 
 
1299 
  trn_td_c <=          '0' &
1300 
                       "10" &
1301 
                       "00100" &
1302 
                       '0' &
1303 
                       "000" &
1304 
                       "0000" &
1305 
                       '0' &
1306 
                       '0' &
1307 
                       "00" &
1308 
                       "00" &
1309 
                       "0000000001" &
1310 
                       COMPLETER_ID_CFG &
1311 
                       tag(7 downto 0) &
1312 
                       "0000" &
1313 
                       first_dw_be(3 downto 0);
1314 
  trn_tsof_n        <= '0';
1315 
  trn_tsrc_rdy_n    <= '0';
1316 
 
1317 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1318 
 
1319 
  trn_td_c          <= COMPLETER_ID_CFG &
1320 
                       "0000" &
1321 
                       reg_addr(11 downto 2) &
1322 
                       "00" &
1323 
                       reg_data(7 downto 0) &
1324 
                       reg_data(15 downto 8) &
1325 
                       reg_data(23 downto 16) &
1326 
                       reg_data(31 downto 24);
1327 
  trn_tsof_n        <= '1';
1328 
  trn_teof_n        <= '0';
1329 
  trn_trem_n_c      <= X"00";
1330 
 
1331 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1332 
 
1333 
  trn_teof_n        <= '1';
1334 
  trn_tsrc_rdy_n    <= '1';
1335 
 
1336 
 
1337 
end PROC_TX_TYPE0_CONFIGURATION_WRITE;
1338 
 
1339 
 
1340 
--************************************************************
1341 
--    Proc : PROC_TX_TYPE1_CONFIGURATION_READ
1342 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1343 
--    Outputs : Transaction Tx Interface Signaling
1344 
--    Description : Generates a Type 1 Configuration Read TLP
1345 
--*************************************************************/
1346 
 
1347 
procedure PROC_TX_TYPE1_CONFIGURATION_READ (
1348 
 
1349 
  tag                      : in std_logic_vector (7 downto 0);
1350 
  reg_addr                 : in std_logic_vector (11 downto 0);
1351 
  first_dw_be              : in std_logic_vector (3 downto 0);
1352 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1353 
  signal trn_tsof_n        : out std_logic;
1354 
  signal trn_teof_n        : out std_logic;
1355 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1356 
  signal trn_tsrc_rdy_n    : out std_logic;
1357 
  signal trn_lnk_up_n : in std_logic;
1358 
  signal trn_tdst_rdy_n : in std_logic;
1359 
  signal trn_clk : in std_logic
1360 
 
1361 
) is
1362 
 
1363 
begin
1364 
 
1365 
  assert (trn_lnk_up_n = '0')
1366 
    report "TX Trn interface is MIA"
1367 
    severity failure;
1368 
 
1369 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1370 
 
1371 
  trn_td_c          <= '0' &
1372 
                       "00" &
1373 
                       "00101" &
1374 
                       '0' &
1375 
                       "000" &
1376 
                       "0000" &
1377 
                       '0' &
1378 
                       '0' &
1379 
                       "00" &
1380 
                       "00" &
1381 
                       "0000000001" &
1382 
                       COMPLETER_ID_CFG &
1383 
                       tag(7 downto 0) &
1384 
                       "0000" &
1385 
                       first_dw_be(3 downto 0);
1386 
  trn_tsof_n        <= '0';
1387 
  trn_teof_n        <= '1';
1388 
  trn_trem_n_c      <= X"00";
1389 
  trn_tsrc_rdy_n    <= '0';
1390 
 
1391 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1392 
 
1393 
  trn_td_c          <= COMPLETER_ID_CFG &
1394 
                       "0000" &
1395 
                       reg_addr(11 downto 2) &
1396 
                       "00" &
1397 
                       X"00000000";
1398 
                       trn_tsof_n <= '1';
1399 
                       trn_teof_n <= '0';
1400 
                       trn_trem_n_c <= X"0F";
1401 
                       trn_tsrc_rdy_n <= '0';
1402 
 
1403 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1404 
 
1405 
  trn_teof_n        <= '1';
1406 
  trn_trem_n_c      <= X"00";
1407 
  trn_tsrc_rdy_n    <= '1';
1408 
 
1409 
end PROC_TX_TYPE1_CONFIGURATION_READ;
1410 
 
1411 
 
1412 
--************************************************************
1413 
--    Proc : PROC_TX_TYPE1_CONFIGURATION_WRITE
1414 
--    Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
1415 
--    Outputs : Transaction Tx Interface Signaling
1416 
--    Description : Generates a Type 1 Configuration Write TLP
1417 
--*************************************************************/
1418 
 
1419 
procedure PROC_TX_TYPE1_CONFIGURATION_WRITE (
1420 
 
1421 
  tag                      : in std_logic_vector (7 downto 0);
1422 
  reg_addr                 : in std_logic_vector (11 downto 0);
1423 
  reg_data                 : in std_logic_vector (31 downto 0);
1424 
  first_dw_be              : in std_logic_vector (3 downto 0);
1425 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1426 
  signal trn_tsof_n        : out std_logic;
1427 
  signal trn_teof_n        : out std_logic;
1428 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1429 
  signal trn_tsrc_rdy_n    : out std_logic;
1430 
  signal trn_lnk_up_n : in std_logic;
1431 
  signal trn_tdst_rdy_n : in std_logic;
1432 
  signal trn_clk : in std_logic
1433 
 
1434 
) is
1435 
 
1436 
begin
1437 
 
1438 
  assert (trn_lnk_up_n = '0')
1439 
    report "TX Trn interface is MIA"
1440 
    severity failure;
1441 
 
1442 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1443 
 
1444 
  trn_td_c          <= '0' &
1445 
                       "10" &
1446 
                       "00101" &
1447 
                       '0' &
1448 
                       "000" &
1449 
                       "0000" &
1450 
                       '0' &
1451 
                       '0' &
1452 
                       "00" &
1453 
                       "00" &
1454 
                       "0000000001" &
1455 
                       COMPLETER_ID_CFG &
1456 
                       tag(7 downto 0) &
1457 
                       "0000" &
1458 
                       first_dw_be(3 downto 0);
1459 
  trn_tsof_n        <= '0';
1460 
  trn_tsrc_rdy_n    <= '0';
1461 
 
1462 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1463 
 
1464 
  trn_td_c          <= COMPLETER_ID_CFG &
1465 
                       "0000" &
1466 
                       reg_addr(11 downto 2) &
1467 
                       "00" &
1468 
                       reg_data(7 downto 0) &
1469 
                       reg_data(15 downto 8) &
1470 
                       reg_data(23 downto 16) &
1471 
                       reg_data(31 downto 24);
1472 
 
1473 
  trn_tsof_n       <= '1';
1474 
  trn_teof_n       <= '0';
1475 
  trn_trem_n_c     <= X"00";
1476 
 
1477 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1478 
 
1479 
  trn_teof_n       <= '1';
1480 
  trn_tsrc_rdy_n   <= '1';
1481 
 
1482 
end PROC_TX_TYPE1_CONFIGURATION_WRITE;
1483 
 
1484 
 
1485 
--************************************************************
1486 
--  Procedure : PROC_TX_MEMORY_READ_32
1487 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1488 
--  Outputs : Transaction Tx Interface Signaling
1489 
--  Description : Generates a Memory Read 32 TLP
1490 
--*************************************************************/
1491 
 
1492 
procedure PROC_TX_MEMORY_READ_32 (
1493 
 
1494 
  tag                      : in std_logic_vector (7 downto 0);
1495 
  tc                       : in std_logic_vector (2 downto 0);
1496 
  len                      : in std_logic_vector (9 downto 0);
1497 
  addr                     : in std_logic_vector (31 downto 0);
1498 
  last_dw_be               : in std_logic_vector (3 downto 0);
1499 
  first_dw_be              : in std_logic_vector (3 downto 0);
1500 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1501 
  signal trn_tsof_n        : out std_logic;
1502 
  signal trn_teof_n        : out std_logic;
1503 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1504 
  signal trn_tsrc_rdy_n    : out std_logic;
1505 
  signal trn_lnk_up_n : in std_logic;
1506 
  signal trn_tdst_rdy_n : in std_logic;
1507 
  signal trn_clk : in std_logic
1508 
 
1509 
 
1510 
) is
1511 
 
1512 
begin
1513 
 
1514 
  assert (trn_lnk_up_n = '0')
1515 
    report "TX Trn interface is MIA"
1516 
    severity failure;
1517 
 
1518 
 
1519 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1520 
 
1521 
  trn_td_c <=          '0' &
1522 
                       "00" &
1523 
                       "00000" &
1524 
                       '0' &
1525 
                       tc(2 downto 0) &
1526 
                       "0000" &
1527 
                       '0' &
1528 
                       '0' &
1529 
                       "00" &
1530 
                       "00" &
1531 
                       len(9 downto 0) &
1532 
                       COMPLETER_ID_CFG &
1533 
                       tag(7 downto 0) &
1534 
                       last_dw_be(3 downto 0) &
1535 
                       first_dw_be(3 downto 0);
1536 
  trn_tsof_n        <= '0';
1537 
  trn_teof_n        <= '1';
1538 
  trn_trem_n_c      <= X"00";
1539 
  trn_tsrc_rdy_n    <= '0';
1540 
 
1541 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1542 
 
1543 
  trn_td_c          <= addr(31 downto 2) &
1544 
                       "00" &
1545 
                       X"00000000";
1546 
  trn_tsof_n        <= '1';
1547 
  trn_teof_n        <= '0';
1548 
  trn_trem_n_c      <= X"0F";
1549 
  trn_tsrc_rdy_n    <= '0';
1550 
 
1551 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1552 
 
1553 
  trn_teof_n        <= '1';
1554 
  trn_trem_n_c      <= X"00";
1555 
  trn_tsrc_rdy_n    <= '1';
1556 
 
1557 
end PROC_TX_MEMORY_READ_32;
1558 
 
1559 
 
1560 
--************************************************************
1561 
--  Proc : PROC_TX_MEMORY_READ_64
1562 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1563 
--  Outputs : Transaction Tx Interface Signaling
1564 
--  Description : Generates a Memory Read 64 TLP
1565 
--*************************************************************/
1566 
 
1567 
procedure PROC_TX_MEMORY_READ_64 (
1568 
 
1569 
  tag                      : in std_logic_vector (7 downto 0);
1570 
  tc                       : in std_logic_vector (2 downto 0);
1571 
  len                      : in std_logic_vector (9 downto 0);
1572 
  addr                     : in std_logic_vector (63 downto 0);
1573 
  last_dw_be               : in std_logic_vector (3 downto 0);
1574 
  first_dw_be              : in std_logic_vector (3 downto 0);
1575 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1576 
  signal trn_tsof_n        : out std_logic;
1577 
  signal trn_teof_n        : out std_logic;
1578 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1579 
  signal trn_tsrc_rdy_n    : out std_logic;
1580 
  signal trn_lnk_up_n : in std_logic;
1581 
  signal trn_tdst_rdy_n : in std_logic;
1582 
  signal trn_clk : in std_logic
1583 
 
1584 
 
1585 
) is
1586 
 
1587 
begin
1588 
 
1589 
  assert (trn_lnk_up_n = '0')
1590 
    report "TX Trn interface is MIA"
1591 
    severity failure;
1592 
 
1593 
 
1594 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1595 
 
1596 
  trn_td_c <=          '0' &
1597 
                       "01" &
1598 
                       "00000" &
1599 
                       '0' &
1600 
                       tc(2 downto 0) &
1601 
                       "0000" &
1602 
                       '0' &
1603 
                       '0' &
1604 
                       "00" &
1605 
                       "00" &
1606 
                       len(9 downto 0) &
1607 
                       COMPLETER_ID_CFG &
1608 
                       tag(7 downto 0) &
1609 
                       last_dw_be(3 downto 0) &
1610 
                       first_dw_be(3 downto 0);
1611 
  trn_tsof_n        <= '0';
1612 
  trn_teof_n        <= '1';
1613 
  trn_trem_n_c      <= X"00";
1614 
  trn_tsrc_rdy_n    <= '0';
1615 
 
1616 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1617 
 
1618 
  trn_td_c          <= addr(63 downto 2) &
1619 
                       "00";
1620 
  trn_tsof_n        <= '1';
1621 
  trn_teof_n        <= '0';
1622 
  trn_trem_n_c      <= X"00";
1623 
  trn_tsrc_rdy_n    <= '0';
1624 
 
1625 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1626 
 
1627 
  trn_teof_n        <= '1';
1628 
  trn_trem_n_c      <= X"00";
1629 
  trn_tsrc_rdy_n    <= '1';
1630 
 
1631 
end PROC_TX_MEMORY_READ_64;
1632 
 
1633 
 
1634 
--************************************************************
1635 
--    Proc : PROC_TX_MEMORY_WRITE_32
1636 
--    Inputs : Tag, Length, Address, Last Byte En, First Byte En
1637 
--    Outputs : Transaction Tx Interface Signaling
1638 
--    Description : Generates a Memory Write 32 TLP
1639 
--*************************************************************/
1640 
 
1641 
procedure PROC_TX_MEMORY_WRITE_32 (
1642 
 
1643 
  tag                         : in std_logic_vector (7 downto 0);
1644 
  tc                          : in std_logic_vector (2 downto 0);
1645 
  len                         : in std_logic_vector (9 downto 0);
1646 
  addr                        : in std_logic_vector (31 downto 0);
1647 
  last_dw_be                  : in std_logic_vector (3 downto 0);
1648 
  first_dw_be                 : in std_logic_vector (3 downto 0);
1649 
  ep                          : in std_logic;
1650 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
1651 
  signal trn_tsof_n           : out std_logic;
1652 
  signal trn_teof_n           : out std_logic;
1653 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
1654 
  signal trn_tsrc_rdy_n       : out std_logic;
1655 
  signal trn_terrfwd_n        : out std_logic;
1656 
  signal trn_lnk_up_n : in std_logic;
1657 
  signal trn_tdst_rdy_n : in std_logic;
1658 
  signal trn_clk : in std_logic
1659 
 
1660 
 
1661 
) is
1662 
 
1663 
  variable length             : std_logic_vector(9 downto 0);
1664 
  variable i                  : INTEGER;
1665 
  variable int_length         : INTEGER;
1666 
  variable unsigned_length    : unsigned(9 downto 0);
1667 
 
1668 
begin
1669 
 
1670 
  assert (trn_lnk_up_n = '0')
1671 
    report "TX Trn interface is MIA"
1672 
    severity failure;
1673 
 
1674 
 
1675 
  if (len = "0000000000") then
1676 
 
1677 
    length := "1000000000"; --1024
1678 
 
1679 
  else
1680 
 
1681 
    length := len;
1682 
 
1683 
  end if;
1684 
 
1685 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1686 
 
1687 
  trn_td_c                <= '0' &
1688 
                             "10" &
1689 
                             "00000" &
1690 
                             '0' &
1691 
                             tc(2 downto 0) &
1692 
                             "0000" &
1693 
                             '0' &
1694 
                             '0' &
1695 
                             "00" &
1696 
                             "00" &
1697 
                             len(9 downto 0) &
1698 
                             COMPLETER_ID_CFG &
1699 
                             tag(7 downto 0) &
1700 
                             last_dw_be(3 downto 0) &
1701 
                             first_dw_be(3 downto 0);
1702 
  trn_tsof_n              <= '0';
1703 
  trn_teof_n              <= '1';
1704 
  trn_trem_n_c            <= X"00";
1705 
  trn_tsrc_rdy_n          <= '0';
1706 
 
1707 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1708 
 
1709 
  trn_td_c                <= addr(31 downto 2) &
1710 
                             "00" &
1711 
                             DATA_STORE(0) &
1712 
                             DATA_STORE(1) &
1713 
                             DATA_STORE(2) &
1714 
                             DATA_STORE(3);
1715 
  trn_tsof_n              <= '1';
1716 
 
1717 
  if (length /= "0000000001") then
1718 
 
1719 
    unsigned_length := unsigned(length);
1720 
    int_length := to_integer( unsigned_length);
1721 
    i := 4;
1722 
    while (i < (int_length * 4)) loop
1723 
 
1724 
      PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1725 
 
1726 
      trn_td_c            <= DATA_STORE(i+0) &
1727 
                             DATA_STORE(i+1) &
1728 
                             DATA_STORE(i+2) &
1729 
                             DATA_STORE(i+3) &
1730 
                             DATA_STORE(i+4) &
1731 
                             DATA_STORE(i+5) &
1732 
                             DATA_STORE(i+6) &
1733 
                             DATA_STORE(i+7);
1734 
 
1735 
      if ((i+7) >= ((int_length*4)-1) ) then
1736 
 
1737 
        trn_teof_n <= '0';
1738 
        if (ep = '1') then
1739 
 
1740 
          trn_terrfwd_n   <= '0';
1741 
 
1742 
        end if;
1743 
        if (((int_length - 1) mod 2) = 0) then
1744 
 
1745 
          trn_trem_n_c    <= X"00";
1746 
 
1747 
        else
1748 
 
1749 
          trn_trem_n_c    <= X"0F";
1750 
 
1751 
        end if;
1752 
 
1753 
      end if;
1754 
 
1755 
      i := i + 8;
1756 
 
1757 
    end loop;
1758 
 
1759 
  else
1760 
 
1761 
    trn_teof_n            <= '0';
1762 
    if (ep = '1') then
1763 
 
1764 
      trn_terrfwd_n       <= '0';
1765 
 
1766 
    end if;
1767 
 
1768 
    trn_trem_n_c          <= X"00";
1769 
 
1770 
  end if;
1771 
 
1772 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1773 
 
1774 
  trn_teof_n              <= '1';
1775 
  trn_trem_n_c            <= X"00";
1776 
  trn_terrfwd_n           <= '1';
1777 
  trn_tsrc_rdy_n          <= '1';
1778 
 
1779 
 
1780 
end PROC_TX_MEMORY_WRITE_32;
1781 
 
1782 
 
1783 
 
1784 
--************************************************************
1785 
--  Proc : PROC_TX_MEMORY_WRITE_64
1786 
--  Inputs : Tag, Length, Address, Last Byte En, First Byte En
1787 
--  Outputs : Transaction Tx Interface Signaling
1788 
--  Description : Generates a Memory Write 64 TLP
1789 
--*************************************************************/
1790 
 
1791 
procedure PROC_TX_MEMORY_WRITE_64 (
1792 
 
1793 
  tag                         : in std_logic_vector (7 downto 0);
1794 
  tc                          : in std_logic_vector (2 downto 0);
1795 
  len                         : in std_logic_vector (9 downto 0);
1796 
  addr                        : in std_logic_vector (63 downto 0);
1797 
  last_dw_be                  : in std_logic_vector (3 downto 0);
1798 
  first_dw_be                 : in std_logic_vector (3 downto 0);
1799 
  ep                          : in std_logic;
1800 
  signal trn_td_c             : out std_logic_vector(63 downto 0);
1801 
  signal trn_tsof_n           : out std_logic;
1802 
  signal trn_teof_n           : out std_logic;
1803 
  signal trn_trem_n_c         : out std_logic_vector(7 downto 0);
1804 
  signal trn_tsrc_rdy_n       : out std_logic;
1805 
  signal trn_terrfwd_n        : out std_logic;
1806 
  signal trn_lnk_up_n : in std_logic;
1807 
  signal trn_tdst_rdy_n : in std_logic;
1808 
  signal trn_clk : in std_logic
1809 
 
1810 
 
1811 
) is
1812 
 
1813 
  variable length             : std_logic_vector(9 downto 0);
1814 
  variable i                  : INTEGER;
1815 
  variable int_length         : INTEGER;
1816 
  variable unsigned_length    : unsigned(9 downto 0);
1817 
 
1818 
begin
1819 
 
1820 
  assert (trn_lnk_up_n = '0')
1821 
    report "TX Trn interface is MIA"
1822 
    severity failure;
1823 
 
1824 
 
1825 
  if (len = "0000000000") then
1826 
 
1827 
    length := "1000000000"; --1024
1828 
 
1829 
  else
1830 
 
1831 
    length := len;
1832 
 
1833 
  end if;
1834 
 
1835 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1836 
 
1837 
  trn_td_c               <= '0' &
1838 
                            "11" &
1839 
                            "00000" &
1840 
                            '0' &
1841 
                            tc(2 downto 0) &
1842 
                            "0000" &
1843 
                            '0' &
1844 
                            '0' &
1845 
                            "00" &
1846 
                            "00" &
1847 
                            len(9 downto 0) &
1848 
                            COMPLETER_ID_CFG &
1849 
                            tag(7 downto 0) &
1850 
                            last_dw_be(3 downto 0) &
1851 
                            first_dw_be(3 downto 0);
1852 
  trn_tsof_n             <= '0';
1853 
  trn_teof_n             <= '1';
1854 
  trn_trem_n_c           <= X"00";
1855 
  trn_tsrc_rdy_n         <= '0';
1856 
 
1857 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1858 
 
1859 
  trn_td_c               <= addr(63 downto 2) &
1860 
                            "00" ;
1861 
  trn_tsof_n             <= '1';
1862 
 
1863 
  unsigned_length := unsigned(length);
1864 
  int_length := to_integer( unsigned_length);
1865 
  if (int_length = 1) then
1866 
 
1867 
    DATA_STORE(4) := X"00";
1868 
    DATA_STORE(5) := X"00";
1869 
    DATA_STORE(6) := X"00";
1870 
    DATA_STORE(7) := X"00";
1871 
 
1872 
  end if;
1873 
  i := 0;
1874 
  while (i < (int_length * 4)) loop
1875 
 
1876 
    PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1877 
 
1878 
    trn_td_c             <= DATA_STORE(i+0) &
1879 
                            DATA_STORE(i+1) &
1880 
                            DATA_STORE(i+2) &
1881 
                            DATA_STORE(i+3) &
1882 
                            DATA_STORE(i+4) &
1883 
                            DATA_STORE(i+5) &
1884 
                            DATA_STORE(i+6) &
1885 
                            DATA_STORE(i+7);
1886 
 
1887 
    if ((i+7) >= ((int_length*4)-1) ) then
1888 
 
1889 
      trn_teof_n <= '0';
1890 
      if (ep = '1') then
1891 
 
1892 
        trn_terrfwd_n    <= '0';
1893 
 
1894 
      end if;
1895 
      if ((int_length mod 2) = 0) then
1896 
 
1897 
        trn_trem_n_c     <= X"00";
1898 
 
1899 
      else
1900 
 
1901 
        trn_trem_n_c     <= X"0F";
1902 
 
1903 
      end if;
1904 
 
1905 
    end if;
1906 
 
1907 
    i := i + 8;
1908 
 
1909 
  end loop;
1910 
 
1911 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1912 
 
1913 
  trn_teof_n             <= '1';
1914 
  trn_terrfwd_n          <= '1';
1915 
  trn_trem_n_c           <= X"00";
1916 
  trn_tsrc_rdy_n         <= '1';
1917 
 
1918 
 
1919 
end PROC_TX_MEMORY_WRITE_64;
1920 
 
1921 
 
1922 
--************************************************************
1923 
--  Proc : PROC_TX_COMPLETION_
1924 
--  Inputs : Tag, Tc, Length, Completion Status
1925 
--  Outputs : Transaction Tx Interface Signaling
1926 
--  Description : Generates a Completion TLP
1927 
--*************************************************************/
1928 
 
1929 
 
1930 
procedure PROC_TX_COMPLETION (
1931 
 
1932 
  tag                      : in std_logic_vector (7 downto 0);
1933 
  tc                       : in std_logic_vector (2 downto 0);
1934 
  len                      : in std_logic_vector (9 downto 0);
1935 
  comp_status              : in std_logic_vector (2 downto 0);
1936 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
1937 
  signal trn_tsof_n        : out std_logic;
1938 
  signal trn_teof_n        : out std_logic;
1939 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
1940 
  signal trn_tsrc_rdy_n    : out std_logic;
1941 
  signal trn_lnk_up_n : in std_logic;
1942 
  signal trn_tdst_rdy_n : in std_logic;
1943 
  signal trn_clk : in std_logic
1944 
 
1945 
) is
1946 
 
1947 
begin
1948 
 
1949 
  assert (trn_lnk_up_n = '0')
1950 
  report "TX Trn interface is MIA"
1951 
    severity failure;
1952 
 
1953 
 
1954 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1955 
 
1956 
  trn_td_c          <= '0' &
1957 
                       "00" &
1958 
                       "01010" &
1959 
                       '0' &
1960 
                       tc(2 downto 0) &
1961 
                       "0000" &
1962 
                       '0' &
1963 
                       '0' &
1964 
                       "00" &
1965 
                       "00" &
1966 
                       len(9 downto 0) &
1967 
                       COMPLETER_ID_CFG &
1968 
                       comp_status(2 downto 0) &
1969 
                       '0' &
1970 
                       X"000";
1971 
  trn_tsof_n        <= '0';
1972 
  trn_teof_n        <= '1';
1973 
  trn_trem_n_c      <= X"00";
1974 
  trn_tsrc_rdy_n    <= '0';
1975 
 
1976 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1977 
 
1978 
  trn_td_c          <= COMPLETER_ID_CFG &
1979 
                       tag(7 downto 0) &
1980 
                       X"00" &
1981 
                       X"00000000";
1982 
  trn_tsof_n        <= '1';
1983 
  trn_teof_n        <= '0';
1984 
  trn_trem_n_c      <= X"0F";
1985 
 
1986 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
1987 
 
1988 
  trn_teof_n        <= '1';
1989 
  trn_trem_n_c      <= X"00";
1990 
  trn_tsrc_rdy_n    <= '1';
1991 
 
1992 
 
1993 
end PROC_TX_COMPLETION;
1994 
 
1995 
 
1996 
--************************************************************
1997 
--  Proc : PROC_TX_COMPLETION_DATA_
1998 
--  Inputs : Tag, Tc, Length, Completion Status
1999 
--  Outputs : Transaction Tx Interface Signaling
2000 
--  Description : Generates a Completion with Data TLP
2001 
--*************************************************************/
2002 
 
2003 
procedure PROC_TX_COMPLETION_DATA (
2004 
 
2005 
  tag                      : in std_logic_vector (7 downto 0);
2006 
  tc                       : in std_logic_vector (2 downto 0);
2007 
  len                      : in std_logic_vector (9 downto 0);
2008 
  byte_count               : in std_logic_vector (11 downto 0);
2009 
  lower_addr               : in std_logic_vector (6 downto 0);
2010 
  comp_status              : in std_logic_vector (2 downto 0);
2011 
  ep                       : in std_logic;
2012 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2013 
  signal trn_tsof_n        : out std_logic;
2014 
  signal trn_teof_n        : out std_logic;
2015 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2016 
  signal trn_tsrc_rdy_n    : out std_logic;
2017 
  signal trn_terrfwd_n     : out std_logic;
2018 
  signal trn_lnk_up_n : in std_logic;
2019 
  signal trn_tdst_rdy_n : in std_logic;
2020 
  signal trn_clk : in std_logic
2021 
 
2022 
) is
2023 
 
2024 
  variable length : std_logic_vector(9 downto 0);
2025 
  variable i : INTEGER;
2026 
  variable int_length : INTEGER;
2027 
  variable unsigned_length : unsigned(9 downto 0);
2028 
 
2029 
begin
2030 
 
2031 
  assert (trn_lnk_up_n = '0')
2032 
  report "TX Trn interface is MIA"
2033 
    severity failure;
2034 
 
2035 
 
2036 
  if (len = "0000000000") then
2037 
 
2038 
    length := "1000000000"; --1024
2039 
 
2040 
  else
2041 
 
2042 
    length := len;
2043 
 
2044 
  end if;
2045 
 
2046 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2047 
 
2048 
  trn_td_c                 <= '0' &
2049 
                              "10" &
2050 
                              "01010" &
2051 
                              '0' &
2052 
                              tc(2 downto 0) &
2053 
                              "0000" &
2054 
                              '0' &
2055 
                              '0' &
2056 
                              "00" &
2057 
                              "00" &
2058 
                              len(9 downto 0) &
2059 
                              COMPLETER_ID_CFG &
2060 
                              comp_status(2 downto 0) &
2061 
                              '0' &
2062 
                              byte_count(11 downto 0);
2063 
  trn_tsof_n               <= '0';
2064 
  trn_teof_n               <= '1';
2065 
  trn_trem_n_c             <= X"00";
2066 
  trn_tsrc_rdy_n           <= '0';
2067 
 
2068 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2069 
 
2070 
  trn_td_c                 <= COMPLETER_ID_CFG &
2071 
                              tag(7 downto 0) &
2072 
                              '0' &
2073 
                              lower_addr(6 downto 0) &
2074 
                              DATA_STORE(0) &
2075 
                              DATA_STORE(1) &
2076 
                              DATA_STORE(2) &
2077 
                              DATA_STORE(3);
2078 
  trn_tsof_n               <= '1';
2079 
 
2080 
  if (length /= "0000000001") then
2081 
 
2082 
    unsigned_length := unsigned(length);
2083 
    int_length := to_integer( unsigned_length);
2084 
    i := 4;
2085 
    while (i < (int_length * 4)) loop
2086 
 
2087 
      PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2088 
      trn_td_c             <= DATA_STORE(i+0) &
2089 
                              DATA_STORE(i+1) &
2090 
                              DATA_STORE(i+2) &
2091 
                              DATA_STORE(i+3) &
2092 
                              DATA_STORE(i+4) &
2093 
                              DATA_STORE(i+5) &
2094 
                              DATA_STORE(i+6) &
2095 
                              DATA_STORE(i+7);
2096 
 
2097 
      if ((i+7) >= ((int_length*4)-1) ) then
2098 
 
2099 
        trn_teof_n         <= '0';
2100 
        if (ep = '1') then
2101 
 
2102 
          trn_terrfwd_n    <= '0';
2103 
 
2104 
        end if;
2105 
        if (((int_length - 1) mod 2) = 0) then
2106 
 
2107 
          trn_trem_n_c     <= X"00";
2108 
 
2109 
        else
2110 
 
2111 
          trn_trem_n_c     <= X"0F";
2112 
 
2113 
        end if;
2114 
 
2115 
      end if;
2116 
 
2117 
      i := i + 8;
2118 
 
2119 
    end loop;
2120 
 
2121 
  else
2122 
 
2123 
    trn_teof_n <= '0';
2124 
    if (ep = '1') then
2125 
 
2126 
      trn_terrfwd_n        <= '0';
2127 
 
2128 
    end if;
2129 
 
2130 
    trn_trem_n_c           <= X"00";
2131 
 
2132 
  end if;
2133 
 
2134 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2135 
 
2136 
  trn_teof_n               <= '1';
2137 
  trn_terrfwd_n            <= '1';
2138 
  trn_trem_n_c             <= X"00";
2139 
  trn_tsrc_rdy_n           <= '1';
2140 
 
2141 
 
2142 
end PROC_TX_COMPLETION_DATA;
2143 
 
2144 
 
2145 
--************************************************************
2146 
--    Proc : PROC_TX_MESSAGE
2147 
--    Inputs : Tag, TC, Address, Message Routing, Message Code
2148 
--    Outputs : Transaction Tx Interface Signaling
2149 
--    Description : Generates a Message TLP
2150 
--*************************************************************/
2151 
 
2152 
procedure PROC_TX_MESSAGE (
2153 
 
2154 
  tag                      : in std_logic_vector (7 downto 0);
2155 
  tc                       : in std_logic_vector (2 downto 0);
2156 
  len                      : in std_logic_vector (9 downto 0);
2157 
  data                     : in std_logic_vector (63 downto 0);
2158 
  message_rtg              : in std_logic_vector (2 downto 0);
2159 
  message_code             : in std_logic_vector (7 downto 0);
2160 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2161 
  signal trn_tsof_n        : out std_logic;
2162 
  signal trn_teof_n        : out std_logic;
2163 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2164 
  signal trn_tsrc_rdy_n    : out std_logic;
2165 
  signal trn_lnk_up_n : in std_logic;
2166 
  signal trn_tdst_rdy_n : in std_logic;
2167 
  signal trn_clk : in std_logic
2168 
 
2169 
) is
2170 
 
2171 
begin
2172 
 
2173 
  assert (trn_lnk_up_n = '0')
2174 
    report "TX Trn interface is MIA"
2175 
    severity failure;
2176 
 
2177 
 
2178 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2179 
 
2180 
  trn_td_c          <= '0' &
2181 
                       "01" &
2182 
                       "10" & message_rtg(2 downto 0) &
2183 
                       '0' &
2184 
                       tc(2 downto 0) &
2185 
                       "0000" &
2186 
                       '0' &
2187 
                       '0' &
2188 
                       "00" &
2189 
                       "00" &
2190 
                       "0000000000" &
2191 
                       COMPLETER_ID_CFG &
2192 
                       tag(7 downto 0) &
2193 
                       message_code(7 downto 0);
2194 
  trn_tsof_n        <= '0';
2195 
  trn_teof_n        <= '1';
2196 
  trn_trem_n_c      <= X"00";
2197 
  trn_tsrc_rdy_n    <= '0';
2198 
 
2199 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2200 
 
2201 
  trn_td_c          <= data;
2202 
  trn_tsof_n        <= '1';
2203 
  trn_teof_n        <= '0';
2204 
  trn_trem_n_c      <= X"00";
2205 
 
2206 
 
2207 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2208 
 
2209 
  trn_teof_n        <= '1';
2210 
  trn_trem_n_c      <= X"00";
2211 
  trn_tsrc_rdy_n    <= '1';
2212 
 
2213 
 
2214 
end PROC_TX_MESSAGE;
2215 
 
2216 
 
2217 
 
2218 
--************************************************************
2219 
--    Proc : PROC_TX_MESSAGE_DATA
2220 
--    Inputs : Tag, TC, Address, Message Routing, Message Code
2221 
--    Outputs : Transaction Tx Interface Signaling
2222 
--    Description : Generates a Message Data TLP
2223 
--*************************************************************/
2224 
 
2225 
procedure PROC_TX_MESSAGE_DATA (
2226 
 
2227 
  tag                      : in std_logic_vector (7 downto 0);
2228 
  tc                       : in std_logic_vector (2 downto 0);
2229 
  len                      : in std_logic_vector (9 downto 0);
2230 
  data                     : in std_logic_vector (63 downto 0);
2231 
  message_rtg              : in std_logic_vector (2 downto 0);
2232 
  message_code             : in std_logic_vector (7 downto 0);
2233 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2234 
  signal trn_tsof_n        : out std_logic;
2235 
  signal trn_teof_n        : out std_logic;
2236 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2237 
  signal trn_tsrc_rdy_n    : out std_logic;
2238 
  signal trn_lnk_up_n : in std_logic;
2239 
  signal trn_tdst_rdy_n : in std_logic;
2240 
  signal trn_clk : in std_logic
2241 
 
2242 
) is
2243 
 
2244 
  variable length             : std_logic_vector(9 downto 0);
2245 
  variable i                  : INTEGER;
2246 
  variable int_length         : INTEGER;
2247 
  variable unsigned_length    : unsigned(9 downto 0);
2248 
 
2249 
begin
2250 
 
2251 
  assert (trn_lnk_up_n = '0')
2252 
  report "TX Trn interface is MIA"
2253 
    severity failure;
2254 
 
2255 
 
2256 
  if (len = "0000000000") then
2257 
 
2258 
    length := "1000000000"; --1024
2259 
 
2260 
  else
2261 
 
2262 
    length := len;
2263 
 
2264 
  end if;
2265 
 
2266 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2267 
 
2268 
  trn_td_c              <= '0' &
2269 
                           "11" &
2270 
                           "10" & message_rtg(2 downto 0) &
2271 
                           '0' &
2272 
                           tc(2 downto 0) &
2273 
                           "0000" &
2274 
                           '0' &
2275 
                           '0' &
2276 
                           "00" &
2277 
                           "00" &
2278 
                           length(9 downto 0) &
2279 
                           COMPLETER_ID_CFG &
2280 
                           tag(7 downto 0) &
2281 
                           message_code(7 downto 0);
2282 
 
2283 
  trn_tsof_n            <= '0';
2284 
  trn_teof_n            <= '1';
2285 
  trn_trem_n_c          <= X"00";
2286 
  trn_tsrc_rdy_n        <= '0';
2287 
 
2288 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2289 
 
2290 
  trn_td_c              <= data;
2291 
  trn_tsof_n            <= '1';
2292 
 
2293 
  unsigned_length := unsigned(length);
2294 
  int_length := to_integer( unsigned_length);
2295 
  i := 0;
2296 
  while (i < (int_length * 4)) loop
2297 
 
2298 
    PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2299 
 
2300 
    trn_td_c            <= DATA_STORE(i+0) &
2301 
                           DATA_STORE(i+1) &
2302 
                           DATA_STORE(i+2) &
2303 
                           DATA_STORE(i+3) &
2304 
                           DATA_STORE(i+4) &
2305 
                           DATA_STORE(i+5) &
2306 
                           DATA_STORE(i+6) &
2307 
                           DATA_STORE(i+7);
2308 
 
2309 
    if ((i+7) >= ((int_length*4)-1) ) then
2310 
 
2311 
      trn_teof_n        <= '0';
2312 
      if ((int_length mod 2) = 0) then
2313 
 
2314 
        trn_trem_n_c    <= X"00";
2315 
 
2316 
      else
2317 
 
2318 
        trn_trem_n_c    <= X"0F";
2319 
 
2320 
      end if;
2321 
 
2322 
    end if;
2323 
 
2324 
    i := i + 8;
2325 
 
2326 
  end loop;
2327 
 
2328 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2329 
 
2330 
  trn_teof_n            <= '1';
2331 
  trn_trem_n_c          <= X"00";
2332 
  trn_tsrc_rdy_n        <= '1';
2333 
 
2334 
 
2335 
end PROC_TX_MESSAGE_DATA;
2336 
 
2337 
 
2338 
 
2339 
--************************************************************
2340 
--    Proc : PROC_TX_IO_READ
2341 
--    Inputs : Tag, Address
2342 
--    Outputs : Transaction Tx Interface Signaling
2343 
--    Description : Generates a IO Read TLP
2344 
--*************************************************************/
2345 
 
2346 
procedure PROC_TX_IO_READ (
2347 
 
2348 
  tag                      : in std_logic_vector (7 downto 0);
2349 
  addr                     : in std_logic_vector (31 downto 0);
2350 
  first_dw_be              : in std_logic_vector (3 downto 0);
2351 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2352 
  signal trn_tsof_n        : out std_logic;
2353 
  signal trn_teof_n        : out std_logic;
2354 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2355 
  signal trn_tsrc_rdy_n    : out std_logic;
2356 
  signal trn_lnk_up_n : in std_logic;
2357 
  signal trn_tdst_rdy_n : in std_logic;
2358 
  signal trn_clk : in std_logic
2359 
 
2360 
) is
2361 
 
2362 
begin
2363 
 
2364 
  assert (trn_lnk_up_n = '0')
2365 
    report "TX Trn interface is MIA"
2366 
    severity failure;
2367 
 
2368 
 
2369 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2370 
 
2371 
  trn_td_c          <= '0' &
2372 
                       "00" &
2373 
                       "00010" &
2374 
                       '0' &
2375 
                       "000" &
2376 
                       "0000" &
2377 
                       '0' &
2378 
                       '0' &
2379 
                       "00" &
2380 
                       "00" &
2381 
                       "0000000001" &
2382 
                       COMPLETER_ID_CFG &
2383 
                       tag(7 downto 0) &
2384 
                       "0000" &
2385 
                       first_dw_be(3 downto 0);
2386 
  trn_tsof_n        <= '0';
2387 
  trn_teof_n        <= '1';
2388 
  trn_trem_n_c      <= X"00";
2389 
  trn_tsrc_rdy_n    <= '0';
2390 
 
2391 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2392 
 
2393 
  trn_td_c          <= addr(31 downto 2) &
2394 
                      "00" &
2395 
                       X"00000000";
2396 
  trn_tsof_n        <= '1';
2397 
  trn_teof_n        <= '0';
2398 
  trn_trem_n_c      <= X"0F";
2399 
  trn_tsrc_rdy_n    <= '0';
2400 
 
2401 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2402 
 
2403 
  trn_teof_n        <= '1';
2404 
  trn_trem_n_c      <= X"00";
2405 
  trn_tsrc_rdy_n    <= '1';
2406 
 
2407 
end PROC_TX_IO_READ;
2408 
 
2409 
 
2410 
--************************************************************
2411 
--    Proc : PROC_TX_IO_WRITE
2412 
--    Inputs : Tag, Address, Data
2413 
--    Outputs : Transaction Tx Interface Signaling
2414 
--    Description : Generates a IO Read TLP
2415 
--*************************************************************/
2416 
 
2417 
procedure PROC_TX_IO_WRITE (
2418 
 
2419 
  tag                      : in std_logic_vector (7 downto 0);
2420 
  addr                     : in std_logic_vector (31 downto 0);
2421 
  first_dw_be              : in std_logic_vector (3 downto 0);
2422 
  data                     : in std_logic_vector(31 downto 0);
2423 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2424 
  signal trn_tsof_n        : out std_logic;
2425 
  signal trn_teof_n        : out std_logic;
2426 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2427 
  signal trn_tsrc_rdy_n    : out std_logic;
2428 
  signal trn_lnk_up_n : in std_logic;
2429 
  signal trn_tdst_rdy_n : in std_logic;
2430 
  signal trn_clk : in std_logic
2431 
 
2432 
) is
2433 
 
2434 
begin
2435 
 
2436 
  assert (trn_lnk_up_n = '0')
2437 
    report "TX Trn interface is MIA"
2438 
    severity failure;
2439 
 
2440 
 
2441 
  PROC_TX_SYNCHRONIZE(0, 0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2442 
 
2443 
  trn_td_c          <= '0' &
2444 
                       "10" &
2445 
                       "00010" &
2446 
                       '0' &
2447 
                       "000" &
2448 
                       "0000" &
2449 
                       '0' &
2450 
                       '0' &
2451 
                       "00" &
2452 
                       "00" &
2453 
                       "0000000001" &
2454 
                       COMPLETER_ID_CFG &
2455 
                       tag(7 downto 0) &
2456 
                       "0000" &
2457 
                       first_dw_be(3 downto 0);
2458 
  trn_tsof_n        <= '0';
2459 
  trn_teof_n        <= '1';
2460 
  trn_trem_n_c      <= X"00";
2461 
  trn_tsrc_rdy_n    <= '0';
2462 
 
2463 
  PROC_TX_SYNCHRONIZE(1,0, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2464 
 
2465 
  trn_td_c          <= addr(31 downto 2) &
2466 
                       "00" &
2467 
                       data(7 downto 0) &
2468 
                       data(15 downto 8) &
2469 
                       data(23 downto 16) &
2470 
                       data(31 downto 24);
2471 
  trn_tsof_n        <= '1';
2472 
  trn_teof_n        <= '0';
2473 
  trn_trem_n_c      <= X"00";
2474 
 
2475 
  PROC_TX_SYNCHRONIZE(1, 1, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2476 
 
2477 
  trn_teof_n        <= '1';
2478 
  trn_trem_n_c      <= X"00";
2479 
  trn_tsrc_rdy_n    <= '1';
2480 
 
2481 
 
2482 
end PROC_TX_IO_WRITE;
2483 
 
2484 
 
2485 
--************************************************************
2486 
--    Proc : PROC_USR_DATA_SETUP_SEQ
2487 
--    Inputs : None
2488 
--    Outputs : None
2489 
--    Description : Populates scratch pad data area with known good data.
2490 
--*************************************************************/
2491 
 
2492 
procedure PROC_USR_DATA_SETUP_SEQ is
2493 
 
2494 
  variable i             : INTEGER;
2495 
  variable unsigned_i    : unsigned(7 downto 0);
2496 
  variable vector_i      : std_logic_vector(7 downto 0);
2497 
 
2498 
begin
2499 
 
2500 
  for i in 0 to 4095 loop
2501 
 
2502 
    unsigned_i := to_unsigned(i, 8);
2503 
    vector_i := std_logic_vector(unsigned_i);
2504 
    DATA_STORE(i) := vector_i(7 downto 0);
2505 
 
2506 
  end loop;
2507 
 
2508 
end PROC_USR_DATA_SETUP_SEQ;
2509 
 
2510 
 
2511 
--************************************************************
2512 
--    Proc : PROC_SET_READ_DATA
2513 
--    Inputs : Data
2514 
--    Outputs : None
2515 
--    Description : Set read data to known value
2516 
--*************************************************************/
2517 
 
2518 
procedure PROC_SET_READ_DATA  (
2519 
 
2520 
  be     : in std_logic_vector(3 downto 0);
2521 
  data   : in std_logic_vector(31 downto 0)
2522 
 
2523 
) is
2524 
 
2525 
begin
2526 
 
2527 
  P_READ_DATA := data;
2528 
 
2529 
end PROC_SET_READ_DATA;
2530 
 
2531 
 
2532 
 
2533 
--************************************************************
2534 
--    Proc : PROC_WAIT_FOR_READ_DATA
2535 
--    Inputs : None
2536 
--    Outputs : Read data P_READ_DATA will be valid
2537 
--    Description : This task must be executed
2538 
--                  immediately following a read call
2539 
--                  in order for the read process to function
2540 
--                  correctly.
2541 
--*************************************************************/
2542 
 
2543 
procedure PROC_WAIT_FOR_READ_DATA  (
2544 
 
2545 
  signal tx_rx_read_data_valid    : out std_logic;
2546 
  signal rx_tx_read_data_valid    : in std_logic;
2547 
  signal rx_tx_read_data : in std_logic_vector(31 downto 0);
2548 
  signal trn_clk : in std_logic
2549 
 
2550 
) is
2551 
 
2552 
  variable j : INTEGER;
2553 
 
2554 
begin
2555 
 
2556 
  j := 10;
2557 
  tx_rx_read_data_valid <= '1';
2558 
  while (rx_tx_read_data_valid = '0') loop
2559 
 
2560 
    wait until (trn_clk'event and trn_clk = '1');
2561 
 
2562 
  end loop;
2563 
  P_READ_DATA := rx_tx_read_data;
2564 
  tx_rx_read_data_valid <= '0'; -- indicate to rx_app to make rx_tx_valid = 0
2565 
  wait until rx_tx_read_data_valid = '0';
2566 
 
2567 
end PROC_WAIT_FOR_READ_DATA;
2568 
 
2569 
 
2570 
--***********************************************************
2571 
--      Procedure : PROC_DISPLAY_PCIE_MAP
2572 
--      Inputs : none
2573 
--      Outputs : none
2574 
--      Description : Displays the Memory Manager's P_MAP calculations
2575 
--                    based on range values read from PCI_E device.
2576 
--*************************************************************/
2577 
 
2578 
procedure PROC_DISPLAY_PCIE_MAP  (
2579 
 
2580 
  BAR            : THIRTY_THREE_BIT_ARRAY;
2581 
  BAR_ENABLED    : ENABLE_ARRAY;
2582 
  BAR_RANGE      : DWORD_ARRAY
2583 
 
2584 
) is
2585 
 
2586 
  variable i              : INTEGER;
2587 
  variable L              : line;
2588 
  variable func_result    : std_logic_vector(31 downto 0);
2589 
 
2590 
begin
2591 
 
2592 
  for i in 0 to 6 loop
2593 
 
2594 
    write (L, String'("            BAR "));
2595 
    hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2596 
    write (L, String'(" = 0x"));
2597 
    hwrite(L, BAR(i)(31 downto 0));
2598 
    write (L, String'(" RANGE = 0x"));
2599 
    hwrite(L, BAR_RANGE(i)(31 downto 0));
2600 
 
2601 
    case BAR_ENABLED(i) is
2602 
 
2603 
      when 1 => write (L, String'(" IO MAPPED"));
2604 
 
2605 
      when 2 => write (L, String'(" MEM32 MAPPED"));
2606 
 
2607 
      when 3 => write (L, String'(" MEM64 MAPPED"));
2608 
 
2609 
      when others => write (L, String'(" DISABLED"));
2610 
 
2611 
    end case;
2612 
    writeline (output, L);
2613 
 
2614 
  end loop;
2615 
 
2616 
end PROC_DISPLAY_PCIE_MAP;
2617 
 
2618 
 
2619 
 
2620 
--*************************************************************
2621 
--      Procedure : PROC_BUILD_PCIE_MAP
2622 
--      Inputs :
2623 
--      Outputs :
2624 
--      Description : Looks at range values read from config space and
2625 
--                    builds corresponding mem/io map
2626 
--*************************************************************/
2627 
 
2628 
procedure PROC_BUILD_PCIE_MAP
2629 
 
2630 
is
2631 
 
2632 
  variable i    : INTEGER;
2633 
  variable L    : line;
2634 
  variable RANGE_VALUE : std_logic_vector(31 downto 0);
2635 
 
2636 
begin
2637 
 
2638 
  writeNowToScreen(String'("PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN.."));
2639 
 
2640 
  BAR(0) := '0' & X"10000000";
2641 
  BAR(1) := '0' & X"20000000";
2642 
  BAR(2) := '0' & X"30000000";
2643 
  BAR(3) := '0' & X"40000000";
2644 
  BAR(4) := '0' & X"50000000";
2645 
  BAR(5) := '0' & X"60000000";
2646 
  BAR(6) := '0' & X"70000001";  -- bit 0 must be set to enable the EROM
2647 
 
2648 
 
2649 
  i := 0;
2650 
  while (i <= 6) loop
2651 
 
2652 
    RANGE_VALUE := BAR_RANGE(i);
2653 
 
2654 
    if (RANGE_VALUE = X"00000000") then
2655 
 
2656 
      BAR_ENABLED(i) := 0; -- Disabled
2657 
      BAR(i) := '0' & X"00000000";
2658 
 
2659 
    else
2660 
 
2661 
      if ((RANGE_VALUE(0) = '1') and (i /= 6)) then
2662 
 
2663 
        BAR_ENABLED(i) := 1; -- IO
2664 
        NUMBER_OF_IO_BARS := NUMBER_OF_IO_BARS + 1;
2665 
        if (pio_check_design and (NUMBER_OF_IO_BARS >1)) then
2666 
          write (L, String'("Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR"));
2667 
          hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2668 
          writeline (output, L);
2669 
          BAR_ENABLED(i) := 0; -- Disabled
2670 
        end if;
2671 
 
2672 
      else
2673 
 
2674 
        if (RANGE_VALUE(2) = '1') then
2675 
 
2676 
          BAR_ENABLED(i) := 3; -- Mem64
2677 
          BAR_ENABLED(i+1) := 0; -- Mem64 uses upper BAR so set as disabled
2678 
 
2679 
          NUMBER_OF_MEM64_BARS := NUMBER_OF_MEM64_BARS + 1;
2680 
          if (pio_check_design and (NUMBER_OF_MEM64_BARS >1)) then
2681 
            write (L, String'("Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR"));
2682 
            hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2683 
            writeline (output, L);
2684 
            BAR_ENABLED(i) := 0; -- Disabled
2685 
          end if;
2686 
          i := i + 1;
2687 
 
2688 
        else
2689 
 
2690 
 
2691 
          if (i /= 6) then NUMBER_OF_MEM32_BARS := NUMBER_OF_MEM32_BARS + 1;
2692 
          end if;
2693 
          BAR_ENABLED(i) := 2; -- Mem32
2694 
          if (pio_check_design and (NUMBER_OF_MEM32_BARS >1)) then
2695 
            write (L, String'("Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR"));
2696 
            hwrite(L, std_logic_vector(to_unsigned(i, 4)));
2697 
            writeline (output, L);
2698 
            BAR_ENABLED(i) := 0; -- Disabled
2699 
          end if;
2700 
 
2701 
 
2702 
        end if;
2703 
 
2704 
      end if;
2705 
 
2706 
    end if;
2707 
 
2708 
    i := i + 1;
2709 
 
2710 
  end loop;
2711 
 
2712 
end PROC_BUILD_PCIE_MAP;
2713 
 
2714 
 
2715 
--***********************************************************
2716 
--        Proc : PROC_BAR_SCAN
2717 
--        Inputs : None
2718 
--        Outputs : None
2719 
--        Description : Scans PCI core's configuration registers.
2720 
--*************************************************************/
2721 
 
2722 
procedure PROC_BAR_SCAN  (
2723 
 
2724 
  signal tx_rx_read_data_valid : out std_logic;
2725 
  signal rx_tx_read_data_valid : in std_logic;
2726 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
2727 
  signal trn_td_c : out std_logic_vector(63 downto 0);
2728 
  signal trn_tsof_n : out std_logic;
2729 
  signal trn_teof_n : out std_logic;
2730 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
2731 
  signal trn_tsrc_rdy_n : out std_logic;
2732 
  signal trn_lnk_up_n : in std_logic;
2733 
  signal trn_tdst_rdy_n : in std_logic;
2734 
  signal trn_clk : in std_logic
2735 
 
2736 
) is
2737 
 
2738 
  variable P_ADDRESS_MASK : std_logic_vector((32 - 1) downto 0);
2739 
  variable L : line;
2740 
  variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
2741 
 
2742 
begin
2743 
 
2744 
 
2745 
-- TRN MODEL Initialization
2746 
  BAR_RANGE(0) := X"FFFF0000";
2747 
  BAR_RANGE(1) := X"FFF00000";
2748 
  BAR_RANGE(2) := X"FFFFF000";
2749 
  BAR_RANGE(3) := X"00000000";
2750 
  BAR_RANGE(4) := X"00000000";
2751 
  BAR_RANGE(5) := X"00000000";
2752 
  BAR_RANGE(6) := X"00000000";
2753 
 
2754 
 
2755 
end PROC_BAR_SCAN;
2756 
 
2757 
 
2758 
--************************************************************
2759 
--       Procedure : PROC_BAR_PROGRAM
2760 
--       Inputs : None
2761 
--       Outputs : None
2762 
--       Description : Program's PCI core's configuration registers.
2763 
-- ************************************************************/
2764 
 
2765 
procedure PROC_BAR_PROGRAM  (
2766 
 
2767 
  signal trn_td_c          : out std_logic_vector(63 downto 0);
2768 
  signal trn_tsof_n        : out std_logic;
2769 
  signal trn_teof_n        : out std_logic;
2770 
  signal trn_trem_n_c      : out std_logic_vector(7 downto 0);
2771 
  signal trn_tsrc_rdy_n    : out std_logic;
2772 
  signal trn_lnk_up_n : in std_logic;
2773 
  signal trn_tdst_rdy_n : in std_logic;
2774 
  signal trn_clk : in std_logic
2775 
 
2776 
) is
2777 
 
2778 
  variable L : line;
2779 
  variable DEFAULT_TAG : std_logic_vector(( 8 - 1) downto 0);
2780 
 
2781 
begin
2782 
 
2783 
  DEFAULT_TAG := X"0f";
2784 
 
2785 
  write (L, String'("[ ")); write (L, now);
2786 
  write (L, String'(" ] : Setting Core Configuration Space..."));
2787 
  writeline (output, L);
2788 
  PROC_TX_CLK_EAT(3000, trn_clk);
2789 
 
2790 
-- Program BAR0
2791 
 
2792 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2793 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2794 
    X"010",  --reg_addr 12'h10
2795 
    BAR(0)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2796 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2797 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2798 
  DEFAULT_TAG := X"10";
2799 
  PROC_TX_CLK_EAT(100, trn_clk);
2800 
 
2801 
-- Program BAR1
2802 
 
2803 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2804 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2805 
    X"014", --reg_addr 12'h14
2806 
    BAR(1)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2807 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2808 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2809 
  DEFAULT_TAG := X"11";
2810 
  PROC_TX_CLK_EAT(100, trn_clk);
2811 
 
2812 
-- Program BAR2
2813 
 
2814 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2815 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2816 
    X"018", --reg_addr 12'h18
2817 
    BAR(2)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2818 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2819 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2820 
  DEFAULT_TAG := X"12";
2821 
  PROC_TX_CLK_EAT(100, trn_clk);
2822 
 
2823 
-- Program BAR3
2824 
 
2825 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2826 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2827 
    X"01C", --reg_addr 12'h1C
2828 
    BAR(3)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2829 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2830 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2831 
  DEFAULT_TAG := X"13";
2832 
  PROC_TX_CLK_EAT(100, trn_clk);
2833 
 
2834 
-- Program BAR4
2835 
 
2836 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2837 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2838 
    X"020", --reg_addr 12'h20
2839 
    BAR(4)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2840 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2841 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2842 
  DEFAULT_TAG := X"14";
2843 
  PROC_TX_CLK_EAT(100, trn_clk);
2844 
 
2845 
-- Program BAR5
2846 
 
2847 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2848 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2849 
    X"024", --reg_addr 12'h24
2850 
    BAR(5)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2851 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2852 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2853 
  DEFAULT_TAG := X"15";
2854 
  PROC_TX_CLK_EAT(100, trn_clk);
2855 
 
2856 
-- Program Expansion ROM BAR
2857 
 
2858 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2859 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2860 
    X"030", --reg_addr 12'h30
2861 
    BAR(6)(31 downto 0), --reg_data : in std_logic_vector (31 downto 0);
2862 
    X"F", --first_dw_be : in std_logic_vector (3 downto 0);
2863 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2864 
  DEFAULT_TAG := X"16";
2865 
  PROC_TX_CLK_EAT(100, trn_clk);
2866 
 
2867 
 
2868 
-- Program PCI Command Register
2869 
 
2870 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2871 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2872 
    X"004", --reg_addr 12'h04
2873 
    X"00000003", --reg_data : in std_logic_vector (31 downto 0);
2874 
    X"1", --first_dw_be : in std_logic_vector (3 downto 0);
2875 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2876 
  DEFAULT_TAG := X"17";
2877 
  PROC_TX_CLK_EAT(100, trn_clk);
2878 
 
2879 
 
2880 
-- Program PCIe Device Control Register
2881 
 
2882 
  PROC_TX_TYPE0_CONFIGURATION_WRITE (
2883 
    DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
2884 
    X"068", --reg_addr 12'h68
2885 
    X"0000005F", --reg_data : in std_logic_vector (31 downto 0);
2886 
    X"1", --first_dw_be : in std_logic_vector (3 downto 0);
2887 
    trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2888 
  DEFAULT_TAG := X"18";
2889 
  PROC_TX_CLK_EAT(1000, trn_clk);
2890 
 
2891 
end PROC_BAR_PROGRAM;
2892 
 
2893 
 
2894 
--   ***********************************************************
2895 
--      Procedure : PROC_BAR_INIT
2896 
--      Inputs : None
2897 
--      Outputs : None
2898 
--     Description : Initialize PCI core based on core's configuration.
2899 
--   *************************************************************/
2900 
 
2901 
procedure PROC_BAR_INIT  (
2902 
 
2903 
  signal tx_rx_read_data_valid : out std_logic;
2904 
  signal rx_tx_read_data_valid : in std_logic;
2905 
  signal rx_tx_read_data : in std_logic_vector (31 downto 0);
2906 
  signal trn_td_c : out std_logic_vector(63 downto 0);
2907 
  signal trn_tsof_n : out std_logic;
2908 
  signal trn_teof_n : out std_logic;
2909 
  signal trn_trem_n_c : out std_logic_vector(7 downto 0);
2910 
  signal trn_tsrc_rdy_n : out std_logic;
2911 
  signal trn_lnk_up_n : in std_logic;
2912 
  signal trn_tdst_rdy_n : in std_logic;
2913 
  signal trn_clk : in std_logic
2914 
 
2915 
) is
2916 
 
2917 
begin
2918 
 
2919 
  PROC_BAR_SCAN(tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c, trn_tsof_n,
2920 
                trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n,trn_clk);
2921 
 
2922 
  PROC_BUILD_PCIE_MAP;
2923 
 
2924 
  PROC_DISPLAY_PCIE_MAP(BAR, BAR_ENABLED, BAR_RANGE );
2925 
 
2926 
  PROC_BAR_PROGRAM( trn_td_c, trn_tsof_n, trn_teof_n,
2927 
                    trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);
2928 
 
2929 
end PROC_BAR_INIT;
2930 
 
2931 
 
2932 
 
2933 
--************************************************************
2934 
--  Proc : PROC_SYSTEM_INITIALIZATION
2935 
--  Inputs : None
2936 
--  Outputs : None
2937 
--  Description : Waits for Reset to deassert and for Link up.
2938 
--*************************************************************/
2939 
 
2940 
procedure PROC_SYSTEM_INITIALIZATION(
2941 
   signal trn_reset_n: in std_logic;
2942 
   signal trn_lnk_up_n: in std_logic )  is
2943 
 
2944 
  variable  L : line;
2945 
 
2946 
begin
2947 
 
2948 
--------------------------------------------------------------------------
2949 
-- Wait for Transaction reset to be de-asserted..
2950 
--------------------------------------------------------------------------
2951 
 
2952 
  wait until trn_reset_n = '1';
2953 
  writeNowToScreen ( String'("Transaction Reset is De-asserted"));
2954 
 
2955 
--------------------------------------------------------------------------
2956 
-- Wait for Transaction link to be asserted..
2957 
--------------------------------------------------------------------------
2958 
 
2959 
  wait until trn_lnk_up_n = '0';
2960 
  writeNowToScreen ( String'("Transaction Link is Up"));
2961 
 
2962 
 
2963 
end PROC_SYSTEM_INITIALIZATION;
2964 
 
2965 
--************************************************************
2966 
--  Proc : PROC_READ_CFG_DW
2967 
--  Inputs : addr - 10-bit address
2968 
--  Outputs : None
2969 
--  Inouts : cfg_rdwr_int - configuration interface signals
2970 
--  Description : Read Configuration Space DW
2971 
--*************************************************************/
2972 
 
2973 
procedure PROC_READ_CFG_DW (
2974 
  addr                 : in    std_logic_vector(9 downto 0);
2975 
  signal cfg_rdwr_int  : inout cfg_rdwr_sigs
2976 
) is
2977 
    variable L : line;
2978 
  begin
2979 
 
2980 
    -- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
2981 
    cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
2982 
    cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
2983 
    cfg_rdwr_int.trn_clk <= 'Z';
2984 
    cfg_rdwr_int.trn_reset_n <= 'Z';
2985 
 
2986 
    assert (cfg_rdwr_int.trn_reset_n = '1')
2987 
    report "TX Reset is asserted"
2988 
    severity failure;
2989 
 
2990 
    if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
2991 
      wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
2992 
    end if;
2993 
 
2994 
    wait until (rising_edge(cfg_rdwr_int.trn_clk));
2995 
    cfg_rdwr_int.cfg_dwaddr <= addr;
2996 
    cfg_rdwr_int.cfg_wr_en_n <= '1';
2997 
    cfg_rdwr_int.cfg_rd_en_n <= '0';
2998 
    writeNowToScreen(String'("Reading Config space"));
2999 
    write (L, String'("  Addr: [0x"));
3000 
    hwrite(L, "00" & addr);
3001 
    write (L, String'("]"));
3002 
    writeline(output, L);
3003 
 
3004 
 
3005 
    wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
3006 
    cfg_rdwr_int.cfg_rd_en_n <= '1';
3007 
    write (L, String'("  Cfg Addr [0x"));
3008 
    hwrite(L, "00" & addr);
3009 
    write (L, String'("] -> Data [0x"));
3010 
    hwrite(L, cfg_rdwr_int.cfg_do);
3011 
    write (L, String'("]"));
3012 
    writeline(output, L);
3013 
 
3014 
  end PROC_READ_CFG_DW;
3015 
 
3016 
--************************************************************
3017 
--  Proc : PROC_WRITE_CFG_DW
3018 
--  Inputs : addr - 10-bit address
3019 
--           data - 32-bit data to write
3020 
--           byte_en_n - 4-bit active-low byte enable
3021 
--  Outputs : None
3022 
--  Inouts : cfg_rdwr_int - configuration interface signals
3023 
--  Description : Write Configuration Space DW
3024 
--*************************************************************/
3025 
 
3026 
procedure PROC_WRITE_CFG_DW (
3027 
  addr                : in    std_logic_vector(9 downto 0);
3028 
  data                : in    std_logic_vector(31 downto 0);
3029 
  byte_en_n           : in    std_logic_vector(3 downto 0);
3030 
  signal cfg_rdwr_int : inout cfg_rdwr_sigs
3031 
) is
3032 
    variable L : line;
3033 
  begin
3034 
 
3035 
    -- Because cfg_rdwr_int is an inout, we have to tri-state the sub-signals we want to read
3036 
    cfg_rdwr_int.cfg_rd_wr_done_n <= 'Z';
3037 
    cfg_rdwr_int.cfg_do <= (OTHERS => 'Z');
3038 
    cfg_rdwr_int.trn_clk <= 'Z';
3039 
    cfg_rdwr_int.trn_reset_n <= 'Z';
3040 
 
3041 
    assert (cfg_rdwr_int.trn_reset_n = '1')
3042 
    report "TX Reset is asserted"
3043 
    severity failure;
3044 
 
3045 
    if (cfg_rdwr_int.cfg_rd_wr_done_n /= '1') then
3046 
      wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '1');
3047 
    end if;
3048 
 
3049 
    wait until (rising_edge(cfg_rdwr_int.trn_clk));
3050 
    cfg_rdwr_int.cfg_dwaddr <= addr;
3051 
    cfg_rdwr_int.cfg_wr_en_n <= '0';
3052 
    cfg_rdwr_int.cfg_rd_en_n <= '1';
3053 
    cfg_rdwr_int.cfg_di <= data;
3054 
    cfg_rdwr_int.cfg_byte_en_n <= byte_en_n;
3055 
    writeNowToScreen(String'("Writing Config space"));
3056 
    write (L, String'("  Addr: [0x"));
3057 
    hwrite(L, "00" & addr);
3058 
    write (L, String'("] -> Data [0x"));
3059 
    hwrite(L, data);
3060 
    write (L, String'("]"));
3061 
    writeline(output, L);
3062 
 
3063 
    wait until (rising_edge(cfg_rdwr_int.trn_clk) and cfg_rdwr_int.cfg_rd_wr_done_n = '0');
3064 
    cfg_rdwr_int.cfg_wr_en_n <= '1';
3065 
 
3066 
  end PROC_WRITE_CFG_DW;
3067 
 
3068 
 
3069 
end package body test_interface;

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