Subversion Repositories pcie_sg_dma

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-- Project    : Virtex-6 Integrated Block for PCI Express

-- File       : sys_clk_gen_ds.vhd

-- Version    : 1.7

--

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library ieee;

use ieee.std_logic_1164.all;

entity sys_clk_gen_ds is

generic (

  CLK_FREQ     : INTEGER := 250

);

port (

  sys_clk_p    : out std_logic;

  sys_clk_n    : out std_logic

);

end sys_clk_gen_ds;

architecture rtl of sys_clk_gen_ds is

component sys_clk_gen

generic (

  CLK_FREQ     : INTEGER := 250

);

port (

  sys_clk      : out std_logic

);

end component;

signal sys_clk_p_int    : std_logic;

begin

  sys_clk_p <= sys_clk_p_int;

  clk_gen : sys_clk_gen

    generic map (

      CLK_FREQ => CLK_FREQ

    )

    port map (

      sys_clk => sys_clk_p_int

    );

  sys_clk_n <= not sys_clk_p_int;

end; -- sys_clk_gen_ds