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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_reset_delay_v6.v
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// Version : 1.7
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//--
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//-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_reset_delay_v6 # (
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parameter PL_FAST_TRAIN = "FALSE",
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parameter REF_CLK_FREQ = 0 // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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)
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(
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input wire ref_clk,
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input wire sys_reset_n,
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output delayed_sys_reset_n
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);
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parameter TCQ = 1;
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localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;
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reg [7:0] reg_count_7_0;
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reg [7:0] reg_count_15_8;
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reg [7:0] reg_count_23_16;
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wire [23:0] concat_count;
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assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};
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always @(posedge ref_clk or negedge sys_reset_n) begin
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if (!sys_reset_n) begin
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reg_count_7_0 <= #TCQ 8'h0;
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reg_count_15_8 <= #TCQ 8'h0;
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reg_count_23_16 <= #TCQ 8'h0;
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end else begin
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if (delayed_sys_reset_n != 1'b1) begin
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reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;
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reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ;
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reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;
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end
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end
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end
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assign delayed_sys_reset_n = concat_count[TBIT];
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endmodule
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