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-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: O.76xd
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-- \ \ Application: netgen
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-- / / Filename: v6_pkt_counter_1024.vhd
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-- /___/ /\ Timestamp: Mon Mar 26 16:00:40 2012
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-- \ \ / \
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-- \___\/\___\
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--
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-- Command : -w -sim -ofmt vhdl "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_pkt_counter_1024.ngc" "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_pkt_counter_1024.vhd"
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-- Device : 6vlx240tff1156-1
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-- Input file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_pkt_counter_1024.ngc
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-- Output file : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_pkt_counter_1024.vhd
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-- # of Entities : 1
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-- Design Name : v6_pkt_counter_1024
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-- Xilinx : C:\Programmi\Xilinx\13.3\ISE_DS\ISE\
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--
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-- Purpose:
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-- This VHDL netlist is a verification model and uses simulation
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-- primitives which may not represent the true implementation of the
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-- device, however the netlist is functionally correct and should not
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-- be modified. This file cannot be synthesized and should only be used
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-- with supported simulation tools.
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--
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-- Reference:
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-- Command Line Tools User Guide, Chapter 23
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-- Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity v6_pkt_counter_1024 is
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port (
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rst : in STD_LOGIC := 'X';
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wr_clk : in STD_LOGIC := 'X';
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rd_clk : in STD_LOGIC := 'X';
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wr_en : in STD_LOGIC := 'X';
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rd_en : in STD_LOGIC := 'X';
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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prog_full : out STD_LOGIC;
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prog_empty : out STD_LOGIC;
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din : in STD_LOGIC_VECTOR ( 0 downto 0 );
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dout : out STD_LOGIC_VECTOR ( 0 downto 0 )
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);
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end v6_pkt_counter_1024;
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architecture STRUCTURE of v6_pkt_counter_1024 is
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signal N0 : STD_LOGIC;
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signal N1 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
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signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_25 : STD_LOGIC;
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signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_36 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0_47 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_49 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0011 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp1 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_38_o_MUX_27_o : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp2 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1 : STD_LOGIC;
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signal write_ctrl_97 : STD_LOGIC;
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signal write_ctrl1_98 : STD_LOGIC;
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signal write_ctrl2_99 : STD_LOGIC;
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signal write_ctrl3_100 : STD_LOGIC;
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signal write_ctrl4_101 : STD_LOGIC;
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signal write_ctrl5_102 : STD_LOGIC;
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signal write_ctrl6_103 : STD_LOGIC;
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signal write_ctrl7_104 : STD_LOGIC;
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signal N11 : STD_LOGIC;
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signal N13 : STD_LOGIC;
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signal N15 : STD_LOGIC;
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signal N17 : STD_LOGIC;
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signal N19 : STD_LOGIC;
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signal N21 : STD_LOGIC;
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signal N23 : STD_LOGIC;
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signal N25 : STD_LOGIC;
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signal inst_LPM_MUX_4_113 : STD_LOGIC;
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signal inst_LPM_MUX_3_114 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_117 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_118 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_119 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_120 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_121 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_122 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_123 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_124 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_10_Q_161 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_9_Q_162 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_9_Q_163 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_8_Q_164 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_8_Q_165 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_7_Q_166 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_7_Q_167 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_6_Q_168 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_6_Q_169 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_5_Q_170 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_5_Q_171 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_4_Q_172 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_4_Q_173 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_3_Q_174 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_3_Q_175 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_2_Q_176 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_2_Q_177 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_1_Q_178 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_1_Q_179 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_0_Q_180 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_1_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_2_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_3_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_4_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_5_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_6_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_7_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_8_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_9_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_10_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT81_204 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT103 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_1_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_2_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_3_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_4_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_5_Q : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_6_Q : STD_LOGIC;
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177 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_7_Q : STD_LOGIC;
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178 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_8_Q : STD_LOGIC;
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179 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_9_Q : STD_LOGIC;
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180 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_10_Q_215 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_9_Q_216 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_9_Q_217 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_8_Q_218 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_8_Q_219 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_7_Q_220 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_7_Q_221 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_6_Q_222 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_6_Q_223 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_5_Q_224 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_5_Q_225 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_4_Q_226 : STD_LOGIC;
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_4_Q_227 : STD_LOGIC;
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205 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_3_Q_228 : STD_LOGIC;
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207 |
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208 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_3_Q_229 : STD_LOGIC;
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209 |
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210 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_2_Q_230 : STD_LOGIC;
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211 |
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212 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_2_Q_231 : STD_LOGIC;
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213 |
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214 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_1_Q_232 : STD_LOGIC;
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215 |
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216 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_1_Q_233 : STD_LOGIC;
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217 |
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218 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_0_Q_234 : STD_LOGIC;
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219 |
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220 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_4_Q : STD_LOGIC;
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221 |
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222 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_5_Q : STD_LOGIC;
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223 |
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224 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_6_Q : STD_LOGIC;
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225 |
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226 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_7_Q : STD_LOGIC;
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227 |
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228 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_8_Q : STD_LOGIC;
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229 |
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230 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_9_Q : STD_LOGIC;
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231 |
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232 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_10_Q : STD_LOGIC;
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233 |
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234 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_bdd0 : STD_LOGIC;
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235 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_1_Q : STD_LOGIC;
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236 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_2_Q : STD_LOGIC;
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237 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_Q : STD_LOGIC;
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238 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_4_Q : STD_LOGIC;
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239 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_5_Q : STD_LOGIC;
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240 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_6_Q : STD_LOGIC;
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241 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_7_Q : STD_LOGIC;
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242 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_8_Q_257 : STD_LOGIC;
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243 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_9_Q_258 : STD_LOGIC;
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244 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_11_o : STD_LOGIC;
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245 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_10_o : STD_LOGIC;
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246 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_9_o : STD_LOGIC;
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247 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_8_o : STD_LOGIC;
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248 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_7_o : STD_LOGIC;
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249 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_6_o : STD_LOGIC;
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250 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_5_o : STD_LOGIC;
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251 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_4_o : STD_LOGIC;
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252 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_24_o : STD_LOGIC;
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253 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_23_o : STD_LOGIC;
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254 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_22_o : STD_LOGIC;
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255 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_21_o : STD_LOGIC;
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256 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_20_o : STD_LOGIC;
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257 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_19_o : STD_LOGIC;
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258 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_18_o : STD_LOGIC;
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259 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_17_o : STD_LOGIC;
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260 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_63_o : STD_LOGIC;
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261 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_62_o : STD_LOGIC;
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262 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_61_o : STD_LOGIC;
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263 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_3_RD_PNTR_4_XOR_60_o : STD_LOGIC;
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264 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_4_RD_PNTR_5_XOR_59_o : STD_LOGIC;
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265 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_5_RD_PNTR_6_XOR_58_o : STD_LOGIC;
|
266 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_6_RD_PNTR_7_XOR_57_o : STD_LOGIC;
|
267 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_7_RD_PNTR_8_XOR_56_o : STD_LOGIC;
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268 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_8_RD_PNTR_9_XOR_55_o : STD_LOGIC;
|
269 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_9_o : STD_LOGIC;
|
270 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_8_o : STD_LOGIC;
|
271 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_7_o : STD_LOGIC;
|
272 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_3_WR_PNTR_4_XOR_6_o : STD_LOGIC;
|
273 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_4_WR_PNTR_5_XOR_5_o : STD_LOGIC;
|
274 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_5_WR_PNTR_6_XOR_4_o : STD_LOGIC;
|
275 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_6_WR_PNTR_7_XOR_3_o : STD_LOGIC;
|
276 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_7_WR_PNTR_8_XOR_2_o : STD_LOGIC;
|
277 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_8_WR_PNTR_9_XOR_1_o : STD_LOGIC;
|
278 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_12_o : STD_LOGIC;
|
279 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_25_o : STD_LOGIC;
|
280 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv : STD_LOGIC;
|
281 |
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signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv : STD_LOGIC;
|
282 |
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signal N01 : STD_LOGIC;
|
283 |
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signal N81 : STD_LOGIC;
|
284 |
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signal N10 : STD_LOGIC;
|
285 |
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signal N12 : STD_LOGIC;
|
286 |
|
|
signal N14 : STD_LOGIC;
|
287 |
|
|
signal N18 : STD_LOGIC;
|
288 |
|
|
signal N20 : STD_LOGIC;
|
289 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_364 : STD_LOGIC;
|
290 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i_rstpot_365 : STD_LOGIC;
|
291 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i_rstpot_366 : STD_LOGIC;
|
292 |
|
|
signal N24 : STD_LOGIC;
|
293 |
|
|
signal N28 : STD_LOGIC;
|
294 |
|
|
signal N30 : STD_LOGIC;
|
295 |
|
|
signal N32 : STD_LOGIC;
|
296 |
|
|
signal N34 : STD_LOGIC;
|
297 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC;
|
298 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC;
|
299 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC;
|
300 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC;
|
301 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED : STD_LOGIC;
|
302 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED : STD_LOGIC;
|
303 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED : STD_LOGIC;
|
304 |
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED : STD_LOGIC;
|
305 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin : STD_LOGIC_VECTOR ( 9 downto 0 );
|
306 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin : STD_LOGIC_VECTOR ( 9 downto 0 );
|
307 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2 : STD_LOGIC_VECTOR ( 9 downto 2 );
|
308 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 0 );
|
309 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
|
310 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
|
311 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 9 downto 1 );
|
312 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count : STD_LOGIC_VECTOR ( 9 downto 1 );
|
313 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 0 );
|
314 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
315 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
316 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
317 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
318 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
319 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
320 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
321 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
322 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad : STD_LOGIC_VECTOR ( 0 downto 0 );
|
323 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad : STD_LOGIC_VECTOR ( 10 downto 1 );
|
324 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_rd_pntr_inv_pad : STD_LOGIC_VECTOR ( 1 downto 1 );
|
325 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad : STD_LOGIC_VECTOR ( 10 downto 4 );
|
326 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
|
327 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last : STD_LOGIC_VECTOR ( 9 downto 0 );
|
328 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg : STD_LOGIC_VECTOR ( 9 downto 0 );
|
329 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
|
330 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last : STD_LOGIC_VECTOR ( 9 downto 0 );
|
331 |
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg : STD_LOGIC_VECTOR ( 9 downto 0 );
|
332 |
|
|
begin
|
333 |
|
|
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0_47;
|
334 |
|
|
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_25;
|
335 |
|
|
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_36;
|
336 |
|
|
prog_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i;
|
337 |
|
|
prog_empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i;
|
338 |
|
|
XST_VCC : VCC
|
339 |
|
|
port map (
|
340 |
|
|
P => N0
|
341 |
|
|
);
|
342 |
|
|
XST_GND : GND
|
343 |
|
|
port map (
|
344 |
|
|
G => N1
|
345 |
|
|
);
|
346 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
|
347 |
|
|
generic map(
|
348 |
|
|
INIT => '0'
|
349 |
|
|
)
|
350 |
|
|
port map (
|
351 |
|
|
C => rd_clk,
|
352 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
353 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0),
|
354 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0011,
|
355 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0_47
|
356 |
|
|
);
|
357 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i : FDP
|
358 |
|
|
generic map(
|
359 |
|
|
INIT => '1'
|
360 |
|
|
)
|
361 |
|
|
port map (
|
362 |
|
|
C => rd_clk,
|
363 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o,
|
364 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
365 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_i_36
|
366 |
|
|
);
|
367 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i : FDP
|
368 |
|
|
generic map(
|
369 |
|
|
INIT => '1'
|
370 |
|
|
)
|
371 |
|
|
port map (
|
372 |
|
|
C => rd_clk,
|
373 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o,
|
374 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
375 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35
|
376 |
|
|
);
|
377 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i : FDP
|
378 |
|
|
generic map(
|
379 |
|
|
INIT => '1'
|
380 |
|
|
)
|
381 |
|
|
port map (
|
382 |
|
|
C => wr_clk,
|
383 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_38_o_MUX_27_o,
|
384 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48,
|
385 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_i_25
|
386 |
|
|
);
|
387 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i : FDP
|
388 |
|
|
generic map(
|
389 |
|
|
INIT => '1'
|
390 |
|
|
)
|
391 |
|
|
port map (
|
392 |
|
|
C => wr_clk,
|
393 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_38_o_MUX_27_o,
|
394 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48,
|
395 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93
|
396 |
|
|
);
|
397 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM128X1D
|
398 |
|
|
generic map(
|
399 |
|
|
INIT => X"00000000000000000000000000000000"
|
400 |
|
|
)
|
401 |
|
|
port map (
|
402 |
|
|
WCLK => wr_clk,
|
403 |
|
|
D => din(0),
|
404 |
|
|
WE => write_ctrl1_98,
|
405 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED,
|
406 |
|
|
DPO => N13,
|
407 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
408 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
409 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
410 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
411 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
412 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
413 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
414 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
415 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
416 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
417 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
418 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
419 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
420 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
421 |
|
|
);
|
422 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM128X1D
|
423 |
|
|
generic map(
|
424 |
|
|
INIT => X"00000000000000000000000000000000"
|
425 |
|
|
)
|
426 |
|
|
port map (
|
427 |
|
|
WCLK => wr_clk,
|
428 |
|
|
D => din(0),
|
429 |
|
|
WE => write_ctrl_97,
|
430 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED,
|
431 |
|
|
DPO => N11,
|
432 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
433 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
434 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
435 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
436 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
437 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
438 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
439 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
440 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
441 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
442 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
443 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
444 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
445 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
446 |
|
|
);
|
447 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM128X1D
|
448 |
|
|
generic map(
|
449 |
|
|
INIT => X"00000000000000000000000000000000"
|
450 |
|
|
)
|
451 |
|
|
port map (
|
452 |
|
|
WCLK => wr_clk,
|
453 |
|
|
D => din(0),
|
454 |
|
|
WE => write_ctrl2_99,
|
455 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED,
|
456 |
|
|
DPO => N15,
|
457 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
458 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
459 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
460 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
461 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
462 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
463 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
464 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
465 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
466 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
467 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
468 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
469 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
470 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
471 |
|
|
);
|
472 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM128X1D
|
473 |
|
|
generic map(
|
474 |
|
|
INIT => X"00000000000000000000000000000000"
|
475 |
|
|
)
|
476 |
|
|
port map (
|
477 |
|
|
WCLK => wr_clk,
|
478 |
|
|
D => din(0),
|
479 |
|
|
WE => write_ctrl3_100,
|
480 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED,
|
481 |
|
|
DPO => N17,
|
482 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
483 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
484 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
485 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
486 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
487 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
488 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
489 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
490 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
491 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
492 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
493 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
494 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
495 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
496 |
|
|
);
|
497 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7 : RAM128X1D
|
498 |
|
|
generic map(
|
499 |
|
|
INIT => X"00000000000000000000000000000000"
|
500 |
|
|
)
|
501 |
|
|
port map (
|
502 |
|
|
WCLK => wr_clk,
|
503 |
|
|
D => din(0),
|
504 |
|
|
WE => write_ctrl6_103,
|
505 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED,
|
506 |
|
|
DPO => N23,
|
507 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
508 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
509 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
510 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
511 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
512 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
513 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
514 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
515 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
516 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
517 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
518 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
519 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
520 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
521 |
|
|
);
|
522 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5 : RAM128X1D
|
523 |
|
|
generic map(
|
524 |
|
|
INIT => X"00000000000000000000000000000000"
|
525 |
|
|
)
|
526 |
|
|
port map (
|
527 |
|
|
WCLK => wr_clk,
|
528 |
|
|
D => din(0),
|
529 |
|
|
WE => write_ctrl4_101,
|
530 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED,
|
531 |
|
|
DPO => N19,
|
532 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
533 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
534 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
535 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
536 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
537 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
538 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
539 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
540 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
541 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
542 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
543 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
544 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
545 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
546 |
|
|
);
|
547 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6 : RAM128X1D
|
548 |
|
|
generic map(
|
549 |
|
|
INIT => X"00000000000000000000000000000000"
|
550 |
|
|
)
|
551 |
|
|
port map (
|
552 |
|
|
WCLK => wr_clk,
|
553 |
|
|
D => din(0),
|
554 |
|
|
WE => write_ctrl5_102,
|
555 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED,
|
556 |
|
|
DPO => N21,
|
557 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
558 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
559 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
560 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
561 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
562 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
563 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
564 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
565 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
566 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
567 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
568 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
569 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
570 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
571 |
|
|
);
|
572 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8 : RAM128X1D
|
573 |
|
|
generic map(
|
574 |
|
|
INIT => X"00000000000000000000000000000000"
|
575 |
|
|
)
|
576 |
|
|
port map (
|
577 |
|
|
WCLK => wr_clk,
|
578 |
|
|
D => din(0),
|
579 |
|
|
WE => write_ctrl7_104,
|
580 |
|
|
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED,
|
581 |
|
|
DPO => N25,
|
582 |
|
|
A(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
583 |
|
|
A(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
584 |
|
|
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
585 |
|
|
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
586 |
|
|
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
587 |
|
|
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv,
|
588 |
|
|
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
589 |
|
|
DPRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
590 |
|
|
DPRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
591 |
|
|
DPRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
592 |
|
|
DPRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
593 |
|
|
DPRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
594 |
|
|
DPRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
595 |
|
|
DPRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
596 |
|
|
);
|
597 |
|
|
inst_LPM_MUX_2_f7 : MUXF7
|
598 |
|
|
port map (
|
599 |
|
|
I0 => inst_LPM_MUX_4_113,
|
600 |
|
|
I1 => inst_LPM_MUX_3_114,
|
601 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
602 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_n0011
|
603 |
|
|
);
|
604 |
|
|
inst_LPM_MUX_4 : LUT6
|
605 |
|
|
generic map(
|
606 |
|
|
INIT => X"FD75B931EC64A820"
|
607 |
|
|
)
|
608 |
|
|
port map (
|
609 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
610 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
611 |
|
|
I2 => N15,
|
612 |
|
|
I3 => N17,
|
613 |
|
|
I4 => N13,
|
614 |
|
|
I5 => N11,
|
615 |
|
|
O => inst_LPM_MUX_4_113
|
616 |
|
|
);
|
617 |
|
|
inst_LPM_MUX_3 : LUT6
|
618 |
|
|
generic map(
|
619 |
|
|
INIT => X"FD75B931EC64A820"
|
620 |
|
|
)
|
621 |
|
|
port map (
|
622 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
623 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
624 |
|
|
I2 => N23,
|
625 |
|
|
I3 => N25,
|
626 |
|
|
I4 => N21,
|
627 |
|
|
I5 => N19,
|
628 |
|
|
O => inst_LPM_MUX_3_114
|
629 |
|
|
);
|
630 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
|
631 |
|
|
generic map(
|
632 |
|
|
INIT => '0'
|
633 |
|
|
)
|
634 |
|
|
port map (
|
635 |
|
|
C => wr_clk,
|
636 |
|
|
CLR => rst,
|
637 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_123,
|
638 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_49
|
639 |
|
|
);
|
640 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
|
641 |
|
|
generic map(
|
642 |
|
|
INIT => '0'
|
643 |
|
|
)
|
644 |
|
|
port map (
|
645 |
|
|
C => rd_clk,
|
646 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_119,
|
647 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_118
|
648 |
|
|
);
|
649 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
|
650 |
|
|
generic map(
|
651 |
|
|
INIT => '0'
|
652 |
|
|
)
|
653 |
|
|
port map (
|
654 |
|
|
C => wr_clk,
|
655 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_122,
|
656 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_121
|
657 |
|
|
);
|
658 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3 : FDP
|
659 |
|
|
generic map(
|
660 |
|
|
INIT => '1'
|
661 |
|
|
)
|
662 |
|
|
port map (
|
663 |
|
|
C => wr_clk,
|
664 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48,
|
665 |
|
|
PRE => rst,
|
666 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_123
|
667 |
|
|
);
|
668 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
|
669 |
|
|
generic map(
|
670 |
|
|
INIT => '0'
|
671 |
|
|
)
|
672 |
|
|
port map (
|
673 |
|
|
C => rd_clk,
|
674 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_117,
|
675 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_119
|
676 |
|
|
);
|
677 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
|
678 |
|
|
generic map(
|
679 |
|
|
INIT => '0'
|
680 |
|
|
)
|
681 |
|
|
port map (
|
682 |
|
|
C => wr_clk,
|
683 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_120,
|
684 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_122
|
685 |
|
|
);
|
686 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2 : FDP
|
687 |
|
|
generic map(
|
688 |
|
|
INIT => '1'
|
689 |
|
|
)
|
690 |
|
|
port map (
|
691 |
|
|
C => wr_clk,
|
692 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_124,
|
693 |
|
|
PRE => rst,
|
694 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48
|
695 |
|
|
);
|
696 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP
|
697 |
|
|
generic map(
|
698 |
|
|
INIT => '1'
|
699 |
|
|
)
|
700 |
|
|
port map (
|
701 |
|
|
C => rd_clk,
|
702 |
|
|
D => N1,
|
703 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
704 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2)
|
705 |
|
|
);
|
706 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_1 : FDP
|
707 |
|
|
generic map(
|
708 |
|
|
INIT => '1'
|
709 |
|
|
)
|
710 |
|
|
port map (
|
711 |
|
|
C => rd_clk,
|
712 |
|
|
D => N1,
|
713 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
714 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1)
|
715 |
|
|
);
|
716 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP
|
717 |
|
|
generic map(
|
718 |
|
|
INIT => '1'
|
719 |
|
|
)
|
720 |
|
|
port map (
|
721 |
|
|
C => rd_clk,
|
722 |
|
|
D => N1,
|
723 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
724 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(0)
|
725 |
|
|
);
|
726 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
|
727 |
|
|
port map (
|
728 |
|
|
C => rd_clk,
|
729 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_119,
|
730 |
|
|
D => N1,
|
731 |
|
|
PRE => rst,
|
732 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_117
|
733 |
|
|
);
|
734 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP
|
735 |
|
|
generic map(
|
736 |
|
|
INIT => '1'
|
737 |
|
|
)
|
738 |
|
|
port map (
|
739 |
|
|
C => wr_clk,
|
740 |
|
|
D => N1,
|
741 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
|
742 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1)
|
743 |
|
|
);
|
744 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_0 : FDP
|
745 |
|
|
generic map(
|
746 |
|
|
INIT => '1'
|
747 |
|
|
)
|
748 |
|
|
port map (
|
749 |
|
|
C => wr_clk,
|
750 |
|
|
D => N1,
|
751 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
|
752 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0)
|
753 |
|
|
);
|
754 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1 : FDP
|
755 |
|
|
generic map(
|
756 |
|
|
INIT => '1'
|
757 |
|
|
)
|
758 |
|
|
port map (
|
759 |
|
|
C => wr_clk,
|
760 |
|
|
D => N1,
|
761 |
|
|
PRE => rst,
|
762 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_124
|
763 |
|
|
);
|
764 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_gm_4_gms_ms : MUXCY
|
765 |
|
|
port map (
|
766 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(3),
|
767 |
|
|
DI => N1,
|
768 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(4),
|
769 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1
|
770 |
|
|
);
|
771 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_gm_3_gms_ms : MUXCY
|
772 |
|
|
port map (
|
773 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(2),
|
774 |
|
|
DI => N1,
|
775 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(3),
|
776 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(3)
|
777 |
|
|
);
|
778 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_gm_2_gms_ms : MUXCY
|
779 |
|
|
port map (
|
780 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(1),
|
781 |
|
|
DI => N1,
|
782 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(2),
|
783 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(2)
|
784 |
|
|
);
|
785 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_gm_1_gms_ms : MUXCY
|
786 |
|
|
port map (
|
787 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(0),
|
788 |
|
|
DI => N1,
|
789 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(1),
|
790 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(1)
|
791 |
|
|
);
|
792 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
|
793 |
|
|
port map (
|
794 |
|
|
CI => N0,
|
795 |
|
|
DI => N1,
|
796 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(0),
|
797 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_gmux_carrynet(0)
|
798 |
|
|
);
|
799 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_gm_4_gms_ms : MUXCY
|
800 |
|
|
port map (
|
801 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(3),
|
802 |
|
|
DI => N1,
|
803 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(4),
|
804 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp2
|
805 |
|
|
);
|
806 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_gm_3_gms_ms : MUXCY
|
807 |
|
|
port map (
|
808 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(2),
|
809 |
|
|
DI => N1,
|
810 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(3),
|
811 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(3)
|
812 |
|
|
);
|
813 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_gm_2_gms_ms : MUXCY
|
814 |
|
|
port map (
|
815 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(1),
|
816 |
|
|
DI => N1,
|
817 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(2),
|
818 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(2)
|
819 |
|
|
);
|
820 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_gm_1_gms_ms : MUXCY
|
821 |
|
|
port map (
|
822 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(0),
|
823 |
|
|
DI => N1,
|
824 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(1),
|
825 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(1)
|
826 |
|
|
);
|
827 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_gm_0_gm1_m1 : MUXCY
|
828 |
|
|
port map (
|
829 |
|
|
CI => N0,
|
830 |
|
|
DI => N1,
|
831 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(0),
|
832 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_gmux_carrynet(0)
|
833 |
|
|
);
|
834 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_gm_4_gms_ms : MUXCY
|
835 |
|
|
port map (
|
836 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(3),
|
837 |
|
|
DI => N1,
|
838 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(4),
|
839 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0
|
840 |
|
|
);
|
841 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_gm_3_gms_ms : MUXCY
|
842 |
|
|
port map (
|
843 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(2),
|
844 |
|
|
DI => N1,
|
845 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(3),
|
846 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(3)
|
847 |
|
|
);
|
848 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_gm_2_gms_ms : MUXCY
|
849 |
|
|
port map (
|
850 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(1),
|
851 |
|
|
DI => N1,
|
852 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(2),
|
853 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(2)
|
854 |
|
|
);
|
855 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_gm_1_gms_ms : MUXCY
|
856 |
|
|
port map (
|
857 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(0),
|
858 |
|
|
DI => N1,
|
859 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(1),
|
860 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(1)
|
861 |
|
|
);
|
862 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_gm_0_gm1_m1 : MUXCY
|
863 |
|
|
port map (
|
864 |
|
|
CI => N0,
|
865 |
|
|
DI => N1,
|
866 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(0),
|
867 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_gmux_carrynet(0)
|
868 |
|
|
);
|
869 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_gm_4_gms_ms : MUXCY
|
870 |
|
|
port map (
|
871 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(3),
|
872 |
|
|
DI => N1,
|
873 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(4),
|
874 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp1
|
875 |
|
|
);
|
876 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_gm_3_gms_ms : MUXCY
|
877 |
|
|
port map (
|
878 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(2),
|
879 |
|
|
DI => N1,
|
880 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(3),
|
881 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(3)
|
882 |
|
|
);
|
883 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_gm_2_gms_ms : MUXCY
|
884 |
|
|
port map (
|
885 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(1),
|
886 |
|
|
DI => N1,
|
887 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(2),
|
888 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(2)
|
889 |
|
|
);
|
890 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_gm_1_gms_ms : MUXCY
|
891 |
|
|
port map (
|
892 |
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(0),
|
893 |
|
|
DI => N1,
|
894 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(1),
|
895 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(1)
|
896 |
|
|
);
|
897 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
|
898 |
|
|
port map (
|
899 |
|
|
CI => N0,
|
900 |
|
|
DI => N1,
|
901 |
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(0),
|
902 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_gmux_carrynet(0)
|
903 |
|
|
);
|
904 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_10_Q :
|
905 |
|
|
XORCY
|
906 |
|
|
port map (
|
907 |
|
|
CI =>
|
908 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_9_Q_162
|
909 |
|
|
,
|
910 |
|
|
LI =>
|
911 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_10_Q_161
|
912 |
|
|
,
|
913 |
|
|
O =>
|
914 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_10_Q
|
915 |
|
|
);
|
916 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_9_Q :
|
917 |
|
|
XORCY
|
918 |
|
|
port map (
|
919 |
|
|
CI =>
|
920 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_8_Q_164
|
921 |
|
|
,
|
922 |
|
|
LI =>
|
923 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_9_Q_163
|
924 |
|
|
,
|
925 |
|
|
O =>
|
926 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_9_Q
|
927 |
|
|
);
|
928 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_9_Q :
|
929 |
|
|
MUXCY
|
930 |
|
|
port map (
|
931 |
|
|
CI =>
|
932 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_8_Q_164
|
933 |
|
|
,
|
934 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(8),
|
935 |
|
|
S =>
|
936 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_9_Q_163
|
937 |
|
|
,
|
938 |
|
|
O =>
|
939 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_9_Q_162
|
940 |
|
|
|
941 |
|
|
);
|
942 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_8_Q :
|
943 |
|
|
XORCY
|
944 |
|
|
port map (
|
945 |
|
|
CI =>
|
946 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_7_Q_166
|
947 |
|
|
,
|
948 |
|
|
LI =>
|
949 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_8_Q_165
|
950 |
|
|
,
|
951 |
|
|
O =>
|
952 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_8_Q
|
953 |
|
|
);
|
954 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_8_Q :
|
955 |
|
|
MUXCY
|
956 |
|
|
port map (
|
957 |
|
|
CI =>
|
958 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_7_Q_166
|
959 |
|
|
,
|
960 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(7),
|
961 |
|
|
S =>
|
962 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_8_Q_165
|
963 |
|
|
,
|
964 |
|
|
O =>
|
965 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_8_Q_164
|
966 |
|
|
|
967 |
|
|
);
|
968 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_7_Q :
|
969 |
|
|
XORCY
|
970 |
|
|
port map (
|
971 |
|
|
CI =>
|
972 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_6_Q_168
|
973 |
|
|
,
|
974 |
|
|
LI =>
|
975 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_7_Q_167
|
976 |
|
|
,
|
977 |
|
|
O =>
|
978 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_7_Q
|
979 |
|
|
);
|
980 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_7_Q :
|
981 |
|
|
MUXCY
|
982 |
|
|
port map (
|
983 |
|
|
CI =>
|
984 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_6_Q_168
|
985 |
|
|
,
|
986 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(6),
|
987 |
|
|
S =>
|
988 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_7_Q_167
|
989 |
|
|
,
|
990 |
|
|
O =>
|
991 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_7_Q_166
|
992 |
|
|
|
993 |
|
|
);
|
994 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_6_Q :
|
995 |
|
|
XORCY
|
996 |
|
|
port map (
|
997 |
|
|
CI =>
|
998 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_5_Q_170
|
999 |
|
|
,
|
1000 |
|
|
LI =>
|
1001 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_6_Q_169
|
1002 |
|
|
,
|
1003 |
|
|
O =>
|
1004 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_6_Q
|
1005 |
|
|
);
|
1006 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_6_Q :
|
1007 |
|
|
MUXCY
|
1008 |
|
|
port map (
|
1009 |
|
|
CI =>
|
1010 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_5_Q_170
|
1011 |
|
|
,
|
1012 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(5),
|
1013 |
|
|
S =>
|
1014 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_6_Q_169
|
1015 |
|
|
,
|
1016 |
|
|
O =>
|
1017 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_6_Q_168
|
1018 |
|
|
|
1019 |
|
|
);
|
1020 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_5_Q :
|
1021 |
|
|
XORCY
|
1022 |
|
|
port map (
|
1023 |
|
|
CI =>
|
1024 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_4_Q_172
|
1025 |
|
|
,
|
1026 |
|
|
LI =>
|
1027 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_5_Q_171
|
1028 |
|
|
,
|
1029 |
|
|
O =>
|
1030 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_5_Q
|
1031 |
|
|
);
|
1032 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_5_Q :
|
1033 |
|
|
MUXCY
|
1034 |
|
|
port map (
|
1035 |
|
|
CI =>
|
1036 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_4_Q_172
|
1037 |
|
|
,
|
1038 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(4),
|
1039 |
|
|
S =>
|
1040 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_5_Q_171
|
1041 |
|
|
,
|
1042 |
|
|
O =>
|
1043 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_5_Q_170
|
1044 |
|
|
|
1045 |
|
|
);
|
1046 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_4_Q :
|
1047 |
|
|
XORCY
|
1048 |
|
|
port map (
|
1049 |
|
|
CI =>
|
1050 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_3_Q_174
|
1051 |
|
|
,
|
1052 |
|
|
LI =>
|
1053 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_4_Q_173
|
1054 |
|
|
,
|
1055 |
|
|
O =>
|
1056 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_4_Q
|
1057 |
|
|
);
|
1058 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_4_Q :
|
1059 |
|
|
MUXCY
|
1060 |
|
|
port map (
|
1061 |
|
|
CI =>
|
1062 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_3_Q_174
|
1063 |
|
|
,
|
1064 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
1065 |
|
|
S =>
|
1066 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_4_Q_173
|
1067 |
|
|
,
|
1068 |
|
|
O =>
|
1069 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_4_Q_172
|
1070 |
|
|
|
1071 |
|
|
);
|
1072 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_3_Q :
|
1073 |
|
|
XORCY
|
1074 |
|
|
port map (
|
1075 |
|
|
CI =>
|
1076 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_2_Q_176
|
1077 |
|
|
,
|
1078 |
|
|
LI =>
|
1079 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_3_Q_175
|
1080 |
|
|
,
|
1081 |
|
|
O =>
|
1082 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_3_Q
|
1083 |
|
|
);
|
1084 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_3_Q :
|
1085 |
|
|
MUXCY
|
1086 |
|
|
port map (
|
1087 |
|
|
CI =>
|
1088 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_2_Q_176
|
1089 |
|
|
,
|
1090 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
1091 |
|
|
S =>
|
1092 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_3_Q_175
|
1093 |
|
|
,
|
1094 |
|
|
O =>
|
1095 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_3_Q_174
|
1096 |
|
|
|
1097 |
|
|
);
|
1098 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_2_Q :
|
1099 |
|
|
XORCY
|
1100 |
|
|
port map (
|
1101 |
|
|
CI =>
|
1102 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_1_Q_178
|
1103 |
|
|
,
|
1104 |
|
|
LI =>
|
1105 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_2_Q_177
|
1106 |
|
|
,
|
1107 |
|
|
O =>
|
1108 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_2_Q
|
1109 |
|
|
);
|
1110 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_2_Q :
|
1111 |
|
|
MUXCY
|
1112 |
|
|
port map (
|
1113 |
|
|
CI =>
|
1114 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_1_Q_178
|
1115 |
|
|
,
|
1116 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
1117 |
|
|
S =>
|
1118 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_2_Q_177
|
1119 |
|
|
,
|
1120 |
|
|
O =>
|
1121 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_2_Q_176
|
1122 |
|
|
|
1123 |
|
|
);
|
1124 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_xor_1_Q :
|
1125 |
|
|
XORCY
|
1126 |
|
|
port map (
|
1127 |
|
|
CI =>
|
1128 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_0_Q_180
|
1129 |
|
|
,
|
1130 |
|
|
LI =>
|
1131 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_1_Q_179
|
1132 |
|
|
,
|
1133 |
|
|
O =>
|
1134 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_1_Q
|
1135 |
|
|
);
|
1136 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_1_Q :
|
1137 |
|
|
MUXCY
|
1138 |
|
|
port map (
|
1139 |
|
|
CI =>
|
1140 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_0_Q_180
|
1141 |
|
|
,
|
1142 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0),
|
1143 |
|
|
S =>
|
1144 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_1_Q_179
|
1145 |
|
|
,
|
1146 |
|
|
O =>
|
1147 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_1_Q_178
|
1148 |
|
|
|
1149 |
|
|
);
|
1150 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_0_Q :
|
1151 |
|
|
MUXCY
|
1152 |
|
|
port map (
|
1153 |
|
|
CI => N1,
|
1154 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad(0),
|
1155 |
|
|
S => N1,
|
1156 |
|
|
O =>
|
1157 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_cy_0_Q_180
|
1158 |
|
|
|
1159 |
|
|
);
|
1160 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_10 : FDC
|
1161 |
|
|
port map (
|
1162 |
|
|
C => rd_clk,
|
1163 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1164 |
|
|
D =>
|
1165 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_10_Q,
|
1166 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(10)
|
1167 |
|
|
);
|
1168 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_9 : FDC
|
1169 |
|
|
port map (
|
1170 |
|
|
C => rd_clk,
|
1171 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1172 |
|
|
D =>
|
1173 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_9_Q,
|
1174 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(9)
|
1175 |
|
|
);
|
1176 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_8 : FDC
|
1177 |
|
|
port map (
|
1178 |
|
|
C => rd_clk,
|
1179 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1180 |
|
|
D =>
|
1181 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_8_Q,
|
1182 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(8)
|
1183 |
|
|
);
|
1184 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_7 : FDC
|
1185 |
|
|
port map (
|
1186 |
|
|
C => rd_clk,
|
1187 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1188 |
|
|
D =>
|
1189 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_7_Q,
|
1190 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(7)
|
1191 |
|
|
);
|
1192 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_6 : FDC
|
1193 |
|
|
port map (
|
1194 |
|
|
C => rd_clk,
|
1195 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1196 |
|
|
D =>
|
1197 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_6_Q,
|
1198 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(6)
|
1199 |
|
|
);
|
1200 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_5 : FDC
|
1201 |
|
|
port map (
|
1202 |
|
|
C => rd_clk,
|
1203 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1204 |
|
|
D =>
|
1205 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_5_Q,
|
1206 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(5)
|
1207 |
|
|
);
|
1208 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_4 : FDC
|
1209 |
|
|
port map (
|
1210 |
|
|
C => rd_clk,
|
1211 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1212 |
|
|
D =>
|
1213 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_4_Q,
|
1214 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(4)
|
1215 |
|
|
);
|
1216 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_3 : FDC
|
1217 |
|
|
port map (
|
1218 |
|
|
C => rd_clk,
|
1219 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1220 |
|
|
D =>
|
1221 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_3_Q,
|
1222 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(3)
|
1223 |
|
|
);
|
1224 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_2 : FDC
|
1225 |
|
|
port map (
|
1226 |
|
|
C => rd_clk,
|
1227 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1228 |
|
|
D =>
|
1229 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_2_Q,
|
1230 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(2)
|
1231 |
|
|
);
|
1232 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad_1 : FDC
|
1233 |
|
|
port map (
|
1234 |
|
|
C => rd_clk,
|
1235 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1236 |
|
|
D =>
|
1237 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_1_Q,
|
1238 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(1)
|
1239 |
|
|
);
|
1240 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_9 : FDCE
|
1241 |
|
|
generic map(
|
1242 |
|
|
INIT => '0'
|
1243 |
|
|
)
|
1244 |
|
|
port map (
|
1245 |
|
|
C => rd_clk,
|
1246 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1247 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1248 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
1249 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9)
|
1250 |
|
|
);
|
1251 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_8 : FDCE
|
1252 |
|
|
generic map(
|
1253 |
|
|
INIT => '0'
|
1254 |
|
|
)
|
1255 |
|
|
port map (
|
1256 |
|
|
C => rd_clk,
|
1257 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1258 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1259 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
1260 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8)
|
1261 |
|
|
);
|
1262 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_7 : FDCE
|
1263 |
|
|
generic map(
|
1264 |
|
|
INIT => '0'
|
1265 |
|
|
)
|
1266 |
|
|
port map (
|
1267 |
|
|
C => rd_clk,
|
1268 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1269 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1270 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
1271 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7)
|
1272 |
|
|
);
|
1273 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_6 : FDCE
|
1274 |
|
|
generic map(
|
1275 |
|
|
INIT => '0'
|
1276 |
|
|
)
|
1277 |
|
|
port map (
|
1278 |
|
|
C => rd_clk,
|
1279 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1280 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1281 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
1282 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6)
|
1283 |
|
|
);
|
1284 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_5 : FDCE
|
1285 |
|
|
generic map(
|
1286 |
|
|
INIT => '0'
|
1287 |
|
|
)
|
1288 |
|
|
port map (
|
1289 |
|
|
C => rd_clk,
|
1290 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1291 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1292 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
1293 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5)
|
1294 |
|
|
);
|
1295 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_4 : FDCE
|
1296 |
|
|
generic map(
|
1297 |
|
|
INIT => '0'
|
1298 |
|
|
)
|
1299 |
|
|
port map (
|
1300 |
|
|
C => rd_clk,
|
1301 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1302 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1303 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
1304 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4)
|
1305 |
|
|
);
|
1306 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE
|
1307 |
|
|
generic map(
|
1308 |
|
|
INIT => '0'
|
1309 |
|
|
)
|
1310 |
|
|
port map (
|
1311 |
|
|
C => rd_clk,
|
1312 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1313 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1314 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
1315 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3)
|
1316 |
|
|
);
|
1317 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE
|
1318 |
|
|
generic map(
|
1319 |
|
|
INIT => '0'
|
1320 |
|
|
)
|
1321 |
|
|
port map (
|
1322 |
|
|
C => rd_clk,
|
1323 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1324 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1325 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
1326 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2)
|
1327 |
|
|
);
|
1328 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE
|
1329 |
|
|
generic map(
|
1330 |
|
|
INIT => '0'
|
1331 |
|
|
)
|
1332 |
|
|
port map (
|
1333 |
|
|
C => rd_clk,
|
1334 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1335 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1336 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
1337 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1)
|
1338 |
|
|
);
|
1339 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_0 : FDCE
|
1340 |
|
|
generic map(
|
1341 |
|
|
INIT => '0'
|
1342 |
|
|
)
|
1343 |
|
|
port map (
|
1344 |
|
|
C => rd_clk,
|
1345 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1346 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1347 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_rd_pntr_inv_pad(1),
|
1348 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
|
1349 |
|
|
);
|
1350 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9 : FDCE
|
1351 |
|
|
generic map(
|
1352 |
|
|
INIT => '0'
|
1353 |
|
|
)
|
1354 |
|
|
port map (
|
1355 |
|
|
C => rd_clk,
|
1356 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1357 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1358 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_9_Q,
|
1359 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9)
|
1360 |
|
|
);
|
1361 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_8 : FDCE
|
1362 |
|
|
generic map(
|
1363 |
|
|
INIT => '0'
|
1364 |
|
|
)
|
1365 |
|
|
port map (
|
1366 |
|
|
C => rd_clk,
|
1367 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1368 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1369 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_8_Q,
|
1370 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8)
|
1371 |
|
|
);
|
1372 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_7 : FDCE
|
1373 |
|
|
generic map(
|
1374 |
|
|
INIT => '0'
|
1375 |
|
|
)
|
1376 |
|
|
port map (
|
1377 |
|
|
C => rd_clk,
|
1378 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1379 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1380 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_7_Q,
|
1381 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7)
|
1382 |
|
|
);
|
1383 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_6 : FDCE
|
1384 |
|
|
generic map(
|
1385 |
|
|
INIT => '0'
|
1386 |
|
|
)
|
1387 |
|
|
port map (
|
1388 |
|
|
C => rd_clk,
|
1389 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1390 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1391 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_6_Q,
|
1392 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6)
|
1393 |
|
|
);
|
1394 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_5 : FDCE
|
1395 |
|
|
generic map(
|
1396 |
|
|
INIT => '0'
|
1397 |
|
|
)
|
1398 |
|
|
port map (
|
1399 |
|
|
C => rd_clk,
|
1400 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1401 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1402 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_5_Q,
|
1403 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5)
|
1404 |
|
|
);
|
1405 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_4 : FDCE
|
1406 |
|
|
generic map(
|
1407 |
|
|
INIT => '0'
|
1408 |
|
|
)
|
1409 |
|
|
port map (
|
1410 |
|
|
C => rd_clk,
|
1411 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1412 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1413 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_4_Q,
|
1414 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4)
|
1415 |
|
|
);
|
1416 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE
|
1417 |
|
|
generic map(
|
1418 |
|
|
INIT => '0'
|
1419 |
|
|
)
|
1420 |
|
|
port map (
|
1421 |
|
|
C => rd_clk,
|
1422 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1423 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1424 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_3_Q,
|
1425 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3)
|
1426 |
|
|
);
|
1427 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE
|
1428 |
|
|
generic map(
|
1429 |
|
|
INIT => '0'
|
1430 |
|
|
)
|
1431 |
|
|
port map (
|
1432 |
|
|
C => rd_clk,
|
1433 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1434 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1435 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_2_Q,
|
1436 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2)
|
1437 |
|
|
);
|
1438 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE
|
1439 |
|
|
generic map(
|
1440 |
|
|
INIT => '0'
|
1441 |
|
|
)
|
1442 |
|
|
port map (
|
1443 |
|
|
C => rd_clk,
|
1444 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
|
1445 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
1446 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_1_Q,
|
1447 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1)
|
1448 |
|
|
);
|
1449 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_10_Q :
|
1450 |
|
|
XORCY
|
1451 |
|
|
port map (
|
1452 |
|
|
CI =>
|
1453 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_9_Q_216
|
1454 |
|
|
,
|
1455 |
|
|
LI =>
|
1456 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_10_Q_215
|
1457 |
|
|
,
|
1458 |
|
|
O =>
|
1459 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_10_Q
|
1460 |
|
|
);
|
1461 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_9_Q :
|
1462 |
|
|
XORCY
|
1463 |
|
|
port map (
|
1464 |
|
|
CI =>
|
1465 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_8_Q_218
|
1466 |
|
|
,
|
1467 |
|
|
LI =>
|
1468 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_9_Q_217
|
1469 |
|
|
,
|
1470 |
|
|
O =>
|
1471 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_9_Q
|
1472 |
|
|
);
|
1473 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_9_Q :
|
1474 |
|
|
MUXCY
|
1475 |
|
|
port map (
|
1476 |
|
|
CI =>
|
1477 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_8_Q_218
|
1478 |
|
|
,
|
1479 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(8),
|
1480 |
|
|
S =>
|
1481 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_9_Q_217
|
1482 |
|
|
,
|
1483 |
|
|
O =>
|
1484 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_9_Q_216
|
1485 |
|
|
|
1486 |
|
|
);
|
1487 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_8_Q :
|
1488 |
|
|
XORCY
|
1489 |
|
|
port map (
|
1490 |
|
|
CI =>
|
1491 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_7_Q_220
|
1492 |
|
|
,
|
1493 |
|
|
LI =>
|
1494 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_8_Q_219
|
1495 |
|
|
,
|
1496 |
|
|
O =>
|
1497 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_8_Q
|
1498 |
|
|
);
|
1499 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_8_Q :
|
1500 |
|
|
MUXCY
|
1501 |
|
|
port map (
|
1502 |
|
|
CI =>
|
1503 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_7_Q_220
|
1504 |
|
|
,
|
1505 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(7),
|
1506 |
|
|
S =>
|
1507 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_8_Q_219
|
1508 |
|
|
,
|
1509 |
|
|
O =>
|
1510 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_8_Q_218
|
1511 |
|
|
|
1512 |
|
|
);
|
1513 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_7_Q :
|
1514 |
|
|
XORCY
|
1515 |
|
|
port map (
|
1516 |
|
|
CI =>
|
1517 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_6_Q_222
|
1518 |
|
|
,
|
1519 |
|
|
LI =>
|
1520 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_7_Q_221
|
1521 |
|
|
,
|
1522 |
|
|
O =>
|
1523 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_7_Q
|
1524 |
|
|
);
|
1525 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_7_Q :
|
1526 |
|
|
MUXCY
|
1527 |
|
|
port map (
|
1528 |
|
|
CI =>
|
1529 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_6_Q_222
|
1530 |
|
|
,
|
1531 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(6),
|
1532 |
|
|
S =>
|
1533 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_7_Q_221
|
1534 |
|
|
,
|
1535 |
|
|
O =>
|
1536 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_7_Q_220
|
1537 |
|
|
|
1538 |
|
|
);
|
1539 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_6_Q :
|
1540 |
|
|
XORCY
|
1541 |
|
|
port map (
|
1542 |
|
|
CI =>
|
1543 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_5_Q_224
|
1544 |
|
|
,
|
1545 |
|
|
LI =>
|
1546 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_6_Q_223
|
1547 |
|
|
,
|
1548 |
|
|
O =>
|
1549 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_6_Q
|
1550 |
|
|
);
|
1551 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_6_Q :
|
1552 |
|
|
MUXCY
|
1553 |
|
|
port map (
|
1554 |
|
|
CI =>
|
1555 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_5_Q_224
|
1556 |
|
|
,
|
1557 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(5),
|
1558 |
|
|
S =>
|
1559 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_6_Q_223
|
1560 |
|
|
,
|
1561 |
|
|
O =>
|
1562 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_6_Q_222
|
1563 |
|
|
|
1564 |
|
|
);
|
1565 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_5_Q :
|
1566 |
|
|
XORCY
|
1567 |
|
|
port map (
|
1568 |
|
|
CI =>
|
1569 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_4_Q_226
|
1570 |
|
|
,
|
1571 |
|
|
LI =>
|
1572 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_5_Q_225
|
1573 |
|
|
,
|
1574 |
|
|
O =>
|
1575 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_5_Q
|
1576 |
|
|
);
|
1577 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_5_Q :
|
1578 |
|
|
MUXCY
|
1579 |
|
|
port map (
|
1580 |
|
|
CI =>
|
1581 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_4_Q_226
|
1582 |
|
|
,
|
1583 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(4),
|
1584 |
|
|
S =>
|
1585 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_5_Q_225
|
1586 |
|
|
,
|
1587 |
|
|
O =>
|
1588 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_5_Q_224
|
1589 |
|
|
|
1590 |
|
|
);
|
1591 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_xor_4_Q :
|
1592 |
|
|
XORCY
|
1593 |
|
|
port map (
|
1594 |
|
|
CI =>
|
1595 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_3_Q_228
|
1596 |
|
|
,
|
1597 |
|
|
LI =>
|
1598 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_4_Q_227
|
1599 |
|
|
,
|
1600 |
|
|
O =>
|
1601 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_4_Q
|
1602 |
|
|
);
|
1603 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_4_Q :
|
1604 |
|
|
MUXCY
|
1605 |
|
|
port map (
|
1606 |
|
|
CI =>
|
1607 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_3_Q_228
|
1608 |
|
|
,
|
1609 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
1610 |
|
|
S =>
|
1611 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_4_Q_227
|
1612 |
|
|
,
|
1613 |
|
|
O =>
|
1614 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_4_Q_226
|
1615 |
|
|
|
1616 |
|
|
);
|
1617 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_3_Q :
|
1618 |
|
|
MUXCY
|
1619 |
|
|
port map (
|
1620 |
|
|
CI =>
|
1621 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_2_Q_230
|
1622 |
|
|
,
|
1623 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
1624 |
|
|
S =>
|
1625 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_3_Q_229
|
1626 |
|
|
,
|
1627 |
|
|
O =>
|
1628 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_3_Q_228
|
1629 |
|
|
|
1630 |
|
|
);
|
1631 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_2_Q :
|
1632 |
|
|
MUXCY
|
1633 |
|
|
port map (
|
1634 |
|
|
CI =>
|
1635 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_1_Q_232
|
1636 |
|
|
,
|
1637 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1),
|
1638 |
|
|
S =>
|
1639 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_2_Q_231
|
1640 |
|
|
,
|
1641 |
|
|
O =>
|
1642 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_2_Q_230
|
1643 |
|
|
|
1644 |
|
|
);
|
1645 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_1_Q :
|
1646 |
|
|
MUXCY
|
1647 |
|
|
port map (
|
1648 |
|
|
CI =>
|
1649 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_0_Q_234
|
1650 |
|
|
,
|
1651 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
1652 |
|
|
S =>
|
1653 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_1_Q_233
|
1654 |
|
|
,
|
1655 |
|
|
O =>
|
1656 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_1_Q_232
|
1657 |
|
|
|
1658 |
|
|
);
|
1659 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_0_Q :
|
1660 |
|
|
MUXCY
|
1661 |
|
|
port map (
|
1662 |
|
|
CI => N1,
|
1663 |
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1664 |
|
|
S => N1,
|
1665 |
|
|
O =>
|
1666 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_cy_0_Q_234
|
1667 |
|
|
|
1668 |
|
|
);
|
1669 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_10 : FDC
|
1670 |
|
|
port map (
|
1671 |
|
|
C => wr_clk,
|
1672 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1673 |
|
|
D =>
|
1674 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_10_Q,
|
1675 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(10)
|
1676 |
|
|
);
|
1677 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_9 : FDC
|
1678 |
|
|
port map (
|
1679 |
|
|
C => wr_clk,
|
1680 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1681 |
|
|
D =>
|
1682 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_9_Q,
|
1683 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(9)
|
1684 |
|
|
);
|
1685 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_8 : FDC
|
1686 |
|
|
port map (
|
1687 |
|
|
C => wr_clk,
|
1688 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1689 |
|
|
D =>
|
1690 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_8_Q,
|
1691 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(8)
|
1692 |
|
|
);
|
1693 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_7 : FDC
|
1694 |
|
|
port map (
|
1695 |
|
|
C => wr_clk,
|
1696 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1697 |
|
|
D =>
|
1698 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_7_Q,
|
1699 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(7)
|
1700 |
|
|
);
|
1701 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_6 : FDC
|
1702 |
|
|
port map (
|
1703 |
|
|
C => wr_clk,
|
1704 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1705 |
|
|
D =>
|
1706 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_6_Q,
|
1707 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(6)
|
1708 |
|
|
);
|
1709 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_5 : FDC
|
1710 |
|
|
port map (
|
1711 |
|
|
C => wr_clk,
|
1712 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1713 |
|
|
D =>
|
1714 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_5_Q,
|
1715 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(5)
|
1716 |
|
|
);
|
1717 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad_4 : FDC
|
1718 |
|
|
port map (
|
1719 |
|
|
C => wr_clk,
|
1720 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1721 |
|
|
D =>
|
1722 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_4_Q,
|
1723 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(4)
|
1724 |
|
|
);
|
1725 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_9 : FDCE
|
1726 |
|
|
generic map(
|
1727 |
|
|
INIT => '0'
|
1728 |
|
|
)
|
1729 |
|
|
port map (
|
1730 |
|
|
C => wr_clk,
|
1731 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1732 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1733 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(9),
|
1734 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9)
|
1735 |
|
|
);
|
1736 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_8 : FDCE
|
1737 |
|
|
generic map(
|
1738 |
|
|
INIT => '0'
|
1739 |
|
|
)
|
1740 |
|
|
port map (
|
1741 |
|
|
C => wr_clk,
|
1742 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1743 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1744 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(8),
|
1745 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8)
|
1746 |
|
|
);
|
1747 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_7 : FDCE
|
1748 |
|
|
generic map(
|
1749 |
|
|
INIT => '0'
|
1750 |
|
|
)
|
1751 |
|
|
port map (
|
1752 |
|
|
C => wr_clk,
|
1753 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1754 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1755 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(7),
|
1756 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7)
|
1757 |
|
|
);
|
1758 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_6 : FDCE
|
1759 |
|
|
generic map(
|
1760 |
|
|
INIT => '0'
|
1761 |
|
|
)
|
1762 |
|
|
port map (
|
1763 |
|
|
C => wr_clk,
|
1764 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1765 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1766 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(6),
|
1767 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6)
|
1768 |
|
|
);
|
1769 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_5 : FDCE
|
1770 |
|
|
generic map(
|
1771 |
|
|
INIT => '0'
|
1772 |
|
|
)
|
1773 |
|
|
port map (
|
1774 |
|
|
C => wr_clk,
|
1775 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1776 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1777 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(5),
|
1778 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5)
|
1779 |
|
|
);
|
1780 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_4 : FDCE
|
1781 |
|
|
generic map(
|
1782 |
|
|
INIT => '0'
|
1783 |
|
|
)
|
1784 |
|
|
port map (
|
1785 |
|
|
C => wr_clk,
|
1786 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1787 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1788 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(4),
|
1789 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4)
|
1790 |
|
|
);
|
1791 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_3 : FDCE
|
1792 |
|
|
generic map(
|
1793 |
|
|
INIT => '0'
|
1794 |
|
|
)
|
1795 |
|
|
port map (
|
1796 |
|
|
C => wr_clk,
|
1797 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1798 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1799 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
1800 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3)
|
1801 |
|
|
);
|
1802 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2_2 : FDCE
|
1803 |
|
|
generic map(
|
1804 |
|
|
INIT => '0'
|
1805 |
|
|
)
|
1806 |
|
|
port map (
|
1807 |
|
|
C => wr_clk,
|
1808 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1809 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1810 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
1811 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2)
|
1812 |
|
|
);
|
1813 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_9 : FDCE
|
1814 |
|
|
generic map(
|
1815 |
|
|
INIT => '0'
|
1816 |
|
|
)
|
1817 |
|
|
port map (
|
1818 |
|
|
C => wr_clk,
|
1819 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1820 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1821 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(9),
|
1822 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(9)
|
1823 |
|
|
);
|
1824 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_8 : FDCE
|
1825 |
|
|
generic map(
|
1826 |
|
|
INIT => '0'
|
1827 |
|
|
)
|
1828 |
|
|
port map (
|
1829 |
|
|
C => wr_clk,
|
1830 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1831 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1832 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(8),
|
1833 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(8)
|
1834 |
|
|
);
|
1835 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_7 : FDCE
|
1836 |
|
|
generic map(
|
1837 |
|
|
INIT => '0'
|
1838 |
|
|
)
|
1839 |
|
|
port map (
|
1840 |
|
|
C => wr_clk,
|
1841 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1842 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1843 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7),
|
1844 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(7)
|
1845 |
|
|
);
|
1846 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_6 : FDCE
|
1847 |
|
|
generic map(
|
1848 |
|
|
INIT => '0'
|
1849 |
|
|
)
|
1850 |
|
|
port map (
|
1851 |
|
|
C => wr_clk,
|
1852 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1853 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1854 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
1855 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(6)
|
1856 |
|
|
);
|
1857 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_5 : FDCE
|
1858 |
|
|
generic map(
|
1859 |
|
|
INIT => '0'
|
1860 |
|
|
)
|
1861 |
|
|
port map (
|
1862 |
|
|
C => wr_clk,
|
1863 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1864 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1865 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
1866 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(5)
|
1867 |
|
|
);
|
1868 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_4 : FDCE
|
1869 |
|
|
generic map(
|
1870 |
|
|
INIT => '0'
|
1871 |
|
|
)
|
1872 |
|
|
port map (
|
1873 |
|
|
C => wr_clk,
|
1874 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1875 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1876 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
1877 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(4)
|
1878 |
|
|
);
|
1879 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_3 : FDCE
|
1880 |
|
|
generic map(
|
1881 |
|
|
INIT => '0'
|
1882 |
|
|
)
|
1883 |
|
|
port map (
|
1884 |
|
|
C => wr_clk,
|
1885 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1886 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1887 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
1888 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3)
|
1889 |
|
|
);
|
1890 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_2 : FDCE
|
1891 |
|
|
generic map(
|
1892 |
|
|
INIT => '0'
|
1893 |
|
|
)
|
1894 |
|
|
port map (
|
1895 |
|
|
C => wr_clk,
|
1896 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1897 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1898 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
1899 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2)
|
1900 |
|
|
);
|
1901 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_1 : FDCE
|
1902 |
|
|
generic map(
|
1903 |
|
|
INIT => '0'
|
1904 |
|
|
)
|
1905 |
|
|
port map (
|
1906 |
|
|
C => wr_clk,
|
1907 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1908 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1909 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
1910 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1)
|
1911 |
|
|
);
|
1912 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1_0 : FDPE
|
1913 |
|
|
generic map(
|
1914 |
|
|
INIT => '1'
|
1915 |
|
|
)
|
1916 |
|
|
port map (
|
1917 |
|
|
C => wr_clk,
|
1918 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1919 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv,
|
1920 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1921 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0)
|
1922 |
|
|
);
|
1923 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9 : FDCE
|
1924 |
|
|
generic map(
|
1925 |
|
|
INIT => '0'
|
1926 |
|
|
)
|
1927 |
|
|
port map (
|
1928 |
|
|
C => wr_clk,
|
1929 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1930 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1931 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_9_Q_258,
|
1932 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(9)
|
1933 |
|
|
);
|
1934 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_8 : FDCE
|
1935 |
|
|
generic map(
|
1936 |
|
|
INIT => '0'
|
1937 |
|
|
)
|
1938 |
|
|
port map (
|
1939 |
|
|
C => wr_clk,
|
1940 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1941 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1942 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_8_Q_257,
|
1943 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(8)
|
1944 |
|
|
);
|
1945 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_7 : FDCE
|
1946 |
|
|
generic map(
|
1947 |
|
|
INIT => '0'
|
1948 |
|
|
)
|
1949 |
|
|
port map (
|
1950 |
|
|
C => wr_clk,
|
1951 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1952 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1953 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_7_Q,
|
1954 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7)
|
1955 |
|
|
);
|
1956 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_6 : FDCE
|
1957 |
|
|
generic map(
|
1958 |
|
|
INIT => '0'
|
1959 |
|
|
)
|
1960 |
|
|
port map (
|
1961 |
|
|
C => wr_clk,
|
1962 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1963 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1964 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_6_Q,
|
1965 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6)
|
1966 |
|
|
);
|
1967 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_5 : FDCE
|
1968 |
|
|
generic map(
|
1969 |
|
|
INIT => '0'
|
1970 |
|
|
)
|
1971 |
|
|
port map (
|
1972 |
|
|
C => wr_clk,
|
1973 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1974 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1975 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_5_Q,
|
1976 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5)
|
1977 |
|
|
);
|
1978 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_4 : FDCE
|
1979 |
|
|
generic map(
|
1980 |
|
|
INIT => '0'
|
1981 |
|
|
)
|
1982 |
|
|
port map (
|
1983 |
|
|
C => wr_clk,
|
1984 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1985 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1986 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_4_Q,
|
1987 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4)
|
1988 |
|
|
);
|
1989 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_3 : FDCE
|
1990 |
|
|
generic map(
|
1991 |
|
|
INIT => '0'
|
1992 |
|
|
)
|
1993 |
|
|
port map (
|
1994 |
|
|
C => wr_clk,
|
1995 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
1996 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
1997 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_Q,
|
1998 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3)
|
1999 |
|
|
);
|
2000 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_2 : FDCE
|
2001 |
|
|
generic map(
|
2002 |
|
|
INIT => '0'
|
2003 |
|
|
)
|
2004 |
|
|
port map (
|
2005 |
|
|
C => wr_clk,
|
2006 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
2007 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
2008 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_2_Q,
|
2009 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2)
|
2010 |
|
|
);
|
2011 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_1 : FDPE
|
2012 |
|
|
generic map(
|
2013 |
|
|
INIT => '1'
|
2014 |
|
|
)
|
2015 |
|
|
port map (
|
2016 |
|
|
C => wr_clk,
|
2017 |
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
2018 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_1_Q,
|
2019 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
2020 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1)
|
2021 |
|
|
);
|
2022 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_9 : FDC
|
2023 |
|
|
generic map(
|
2024 |
|
|
INIT => '0'
|
2025 |
|
|
)
|
2026 |
|
|
port map (
|
2027 |
|
|
C => rd_clk,
|
2028 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2029 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
2030 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(9)
|
2031 |
|
|
);
|
2032 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_8 : FDC
|
2033 |
|
|
generic map(
|
2034 |
|
|
INIT => '0'
|
2035 |
|
|
)
|
2036 |
|
|
port map (
|
2037 |
|
|
C => rd_clk,
|
2038 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2039 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_4_o,
|
2040 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(8)
|
2041 |
|
|
);
|
2042 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_7 : FDC
|
2043 |
|
|
generic map(
|
2044 |
|
|
INIT => '0'
|
2045 |
|
|
)
|
2046 |
|
|
port map (
|
2047 |
|
|
C => rd_clk,
|
2048 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2049 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_5_o,
|
2050 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(7)
|
2051 |
|
|
);
|
2052 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_6 : FDC
|
2053 |
|
|
generic map(
|
2054 |
|
|
INIT => '0'
|
2055 |
|
|
)
|
2056 |
|
|
port map (
|
2057 |
|
|
C => rd_clk,
|
2058 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2059 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_6_o,
|
2060 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(6)
|
2061 |
|
|
);
|
2062 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_5 : FDC
|
2063 |
|
|
generic map(
|
2064 |
|
|
INIT => '0'
|
2065 |
|
|
)
|
2066 |
|
|
port map (
|
2067 |
|
|
C => rd_clk,
|
2068 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2069 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_7_o,
|
2070 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(5)
|
2071 |
|
|
);
|
2072 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_4 : FDC
|
2073 |
|
|
generic map(
|
2074 |
|
|
INIT => '0'
|
2075 |
|
|
)
|
2076 |
|
|
port map (
|
2077 |
|
|
C => rd_clk,
|
2078 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2079 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_8_o,
|
2080 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(4)
|
2081 |
|
|
);
|
2082 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_3 : FDC
|
2083 |
|
|
generic map(
|
2084 |
|
|
INIT => '0'
|
2085 |
|
|
)
|
2086 |
|
|
port map (
|
2087 |
|
|
C => rd_clk,
|
2088 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2089 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_9_o,
|
2090 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3)
|
2091 |
|
|
);
|
2092 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_2 : FDC
|
2093 |
|
|
generic map(
|
2094 |
|
|
INIT => '0'
|
2095 |
|
|
)
|
2096 |
|
|
port map (
|
2097 |
|
|
C => rd_clk,
|
2098 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2099 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_10_o,
|
2100 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2)
|
2101 |
|
|
);
|
2102 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_1 : FDC
|
2103 |
|
|
generic map(
|
2104 |
|
|
INIT => '0'
|
2105 |
|
|
)
|
2106 |
|
|
port map (
|
2107 |
|
|
C => rd_clk,
|
2108 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2109 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_11_o,
|
2110 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1)
|
2111 |
|
|
);
|
2112 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin_0 : FDC
|
2113 |
|
|
generic map(
|
2114 |
|
|
INIT => '0'
|
2115 |
|
|
)
|
2116 |
|
|
port map (
|
2117 |
|
|
C => rd_clk,
|
2118 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2119 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_12_o,
|
2120 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0)
|
2121 |
|
|
);
|
2122 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_9 : FDC
|
2123 |
|
|
generic map(
|
2124 |
|
|
INIT => '0'
|
2125 |
|
|
)
|
2126 |
|
|
port map (
|
2127 |
|
|
C => wr_clk,
|
2128 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2129 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
2130 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(9)
|
2131 |
|
|
);
|
2132 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_8 : FDC
|
2133 |
|
|
generic map(
|
2134 |
|
|
INIT => '0'
|
2135 |
|
|
)
|
2136 |
|
|
port map (
|
2137 |
|
|
C => wr_clk,
|
2138 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2139 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_17_o,
|
2140 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(8)
|
2141 |
|
|
);
|
2142 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_7 : FDC
|
2143 |
|
|
generic map(
|
2144 |
|
|
INIT => '0'
|
2145 |
|
|
)
|
2146 |
|
|
port map (
|
2147 |
|
|
C => wr_clk,
|
2148 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2149 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_18_o,
|
2150 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(7)
|
2151 |
|
|
);
|
2152 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_6 : FDC
|
2153 |
|
|
generic map(
|
2154 |
|
|
INIT => '0'
|
2155 |
|
|
)
|
2156 |
|
|
port map (
|
2157 |
|
|
C => wr_clk,
|
2158 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2159 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_19_o,
|
2160 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(6)
|
2161 |
|
|
);
|
2162 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_5 : FDC
|
2163 |
|
|
generic map(
|
2164 |
|
|
INIT => '0'
|
2165 |
|
|
)
|
2166 |
|
|
port map (
|
2167 |
|
|
C => wr_clk,
|
2168 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2169 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_20_o,
|
2170 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(5)
|
2171 |
|
|
);
|
2172 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_4 : FDC
|
2173 |
|
|
generic map(
|
2174 |
|
|
INIT => '0'
|
2175 |
|
|
)
|
2176 |
|
|
port map (
|
2177 |
|
|
C => wr_clk,
|
2178 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2179 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_21_o,
|
2180 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(4)
|
2181 |
|
|
);
|
2182 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_3 : FDC
|
2183 |
|
|
generic map(
|
2184 |
|
|
INIT => '0'
|
2185 |
|
|
)
|
2186 |
|
|
port map (
|
2187 |
|
|
C => wr_clk,
|
2188 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2189 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_22_o,
|
2190 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3)
|
2191 |
|
|
);
|
2192 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_2 : FDC
|
2193 |
|
|
generic map(
|
2194 |
|
|
INIT => '0'
|
2195 |
|
|
)
|
2196 |
|
|
port map (
|
2197 |
|
|
C => wr_clk,
|
2198 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2199 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_23_o,
|
2200 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2)
|
2201 |
|
|
);
|
2202 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_1 : FDC
|
2203 |
|
|
generic map(
|
2204 |
|
|
INIT => '0'
|
2205 |
|
|
)
|
2206 |
|
|
port map (
|
2207 |
|
|
C => wr_clk,
|
2208 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2209 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_24_o,
|
2210 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1)
|
2211 |
|
|
);
|
2212 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin_0 : FDC
|
2213 |
|
|
generic map(
|
2214 |
|
|
INIT => '0'
|
2215 |
|
|
)
|
2216 |
|
|
port map (
|
2217 |
|
|
C => wr_clk,
|
2218 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2219 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_25_o,
|
2220 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0)
|
2221 |
|
|
);
|
2222 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9 : FDC
|
2223 |
|
|
generic map(
|
2224 |
|
|
INIT => '0'
|
2225 |
|
|
)
|
2226 |
|
|
port map (
|
2227 |
|
|
C => rd_clk,
|
2228 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2229 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(9),
|
2230 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9)
|
2231 |
|
|
);
|
2232 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_8 : FDC
|
2233 |
|
|
generic map(
|
2234 |
|
|
INIT => '0'
|
2235 |
|
|
)
|
2236 |
|
|
port map (
|
2237 |
|
|
C => rd_clk,
|
2238 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2239 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(8),
|
2240 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8)
|
2241 |
|
|
);
|
2242 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_7 : FDC
|
2243 |
|
|
generic map(
|
2244 |
|
|
INIT => '0'
|
2245 |
|
|
)
|
2246 |
|
|
port map (
|
2247 |
|
|
C => rd_clk,
|
2248 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2249 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(7),
|
2250 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7)
|
2251 |
|
|
);
|
2252 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_6 : FDC
|
2253 |
|
|
generic map(
|
2254 |
|
|
INIT => '0'
|
2255 |
|
|
)
|
2256 |
|
|
port map (
|
2257 |
|
|
C => rd_clk,
|
2258 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2259 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(6),
|
2260 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6)
|
2261 |
|
|
);
|
2262 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_5 : FDC
|
2263 |
|
|
generic map(
|
2264 |
|
|
INIT => '0'
|
2265 |
|
|
)
|
2266 |
|
|
port map (
|
2267 |
|
|
C => rd_clk,
|
2268 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2269 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(5),
|
2270 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5)
|
2271 |
|
|
);
|
2272 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_4 : FDC
|
2273 |
|
|
generic map(
|
2274 |
|
|
INIT => '0'
|
2275 |
|
|
)
|
2276 |
|
|
port map (
|
2277 |
|
|
C => rd_clk,
|
2278 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2279 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(4),
|
2280 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4)
|
2281 |
|
|
);
|
2282 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_3 : FDC
|
2283 |
|
|
generic map(
|
2284 |
|
|
INIT => '0'
|
2285 |
|
|
)
|
2286 |
|
|
port map (
|
2287 |
|
|
C => rd_clk,
|
2288 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2289 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(3),
|
2290 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3)
|
2291 |
|
|
);
|
2292 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_2 : FDC
|
2293 |
|
|
generic map(
|
2294 |
|
|
INIT => '0'
|
2295 |
|
|
)
|
2296 |
|
|
port map (
|
2297 |
|
|
C => rd_clk,
|
2298 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2299 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(2),
|
2300 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2)
|
2301 |
|
|
);
|
2302 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_1 : FDC
|
2303 |
|
|
generic map(
|
2304 |
|
|
INIT => '0'
|
2305 |
|
|
)
|
2306 |
|
|
port map (
|
2307 |
|
|
C => rd_clk,
|
2308 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2309 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(1),
|
2310 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1)
|
2311 |
|
|
);
|
2312 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_0 : FDC
|
2313 |
|
|
generic map(
|
2314 |
|
|
INIT => '0'
|
2315 |
|
|
)
|
2316 |
|
|
port map (
|
2317 |
|
|
C => rd_clk,
|
2318 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2319 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(0),
|
2320 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(0)
|
2321 |
|
|
);
|
2322 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9 : FDC
|
2323 |
|
|
generic map(
|
2324 |
|
|
INIT => '0'
|
2325 |
|
|
)
|
2326 |
|
|
port map (
|
2327 |
|
|
C => wr_clk,
|
2328 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2329 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(9),
|
2330 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9)
|
2331 |
|
|
);
|
2332 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_8 : FDC
|
2333 |
|
|
generic map(
|
2334 |
|
|
INIT => '0'
|
2335 |
|
|
)
|
2336 |
|
|
port map (
|
2337 |
|
|
C => wr_clk,
|
2338 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2339 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(8),
|
2340 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8)
|
2341 |
|
|
);
|
2342 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_7 : FDC
|
2343 |
|
|
generic map(
|
2344 |
|
|
INIT => '0'
|
2345 |
|
|
)
|
2346 |
|
|
port map (
|
2347 |
|
|
C => wr_clk,
|
2348 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2349 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(7),
|
2350 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7)
|
2351 |
|
|
);
|
2352 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_6 : FDC
|
2353 |
|
|
generic map(
|
2354 |
|
|
INIT => '0'
|
2355 |
|
|
)
|
2356 |
|
|
port map (
|
2357 |
|
|
C => wr_clk,
|
2358 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2359 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(6),
|
2360 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6)
|
2361 |
|
|
);
|
2362 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_5 : FDC
|
2363 |
|
|
generic map(
|
2364 |
|
|
INIT => '0'
|
2365 |
|
|
)
|
2366 |
|
|
port map (
|
2367 |
|
|
C => wr_clk,
|
2368 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2369 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(5),
|
2370 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5)
|
2371 |
|
|
);
|
2372 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_4 : FDC
|
2373 |
|
|
generic map(
|
2374 |
|
|
INIT => '0'
|
2375 |
|
|
)
|
2376 |
|
|
port map (
|
2377 |
|
|
C => wr_clk,
|
2378 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2379 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(4),
|
2380 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4)
|
2381 |
|
|
);
|
2382 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_3 : FDC
|
2383 |
|
|
generic map(
|
2384 |
|
|
INIT => '0'
|
2385 |
|
|
)
|
2386 |
|
|
port map (
|
2387 |
|
|
C => wr_clk,
|
2388 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2389 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(3),
|
2390 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3)
|
2391 |
|
|
);
|
2392 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_2 : FDC
|
2393 |
|
|
generic map(
|
2394 |
|
|
INIT => '0'
|
2395 |
|
|
)
|
2396 |
|
|
port map (
|
2397 |
|
|
C => wr_clk,
|
2398 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2399 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(2),
|
2400 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2)
|
2401 |
|
|
);
|
2402 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_1 : FDC
|
2403 |
|
|
generic map(
|
2404 |
|
|
INIT => '0'
|
2405 |
|
|
)
|
2406 |
|
|
port map (
|
2407 |
|
|
C => wr_clk,
|
2408 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2409 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(1),
|
2410 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1)
|
2411 |
|
|
);
|
2412 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_0 : FDC
|
2413 |
|
|
generic map(
|
2414 |
|
|
INIT => '0'
|
2415 |
|
|
)
|
2416 |
|
|
port map (
|
2417 |
|
|
C => wr_clk,
|
2418 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2419 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(0),
|
2420 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(0)
|
2421 |
|
|
);
|
2422 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_9 : FDC
|
2423 |
|
|
generic map(
|
2424 |
|
|
INIT => '0'
|
2425 |
|
|
)
|
2426 |
|
|
port map (
|
2427 |
|
|
C => rd_clk,
|
2428 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2429 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(9),
|
2430 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(9)
|
2431 |
|
|
);
|
2432 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_8 : FDC
|
2433 |
|
|
generic map(
|
2434 |
|
|
INIT => '0'
|
2435 |
|
|
)
|
2436 |
|
|
port map (
|
2437 |
|
|
C => rd_clk,
|
2438 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2439 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(8),
|
2440 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(8)
|
2441 |
|
|
);
|
2442 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_7 : FDC
|
2443 |
|
|
generic map(
|
2444 |
|
|
INIT => '0'
|
2445 |
|
|
)
|
2446 |
|
|
port map (
|
2447 |
|
|
C => rd_clk,
|
2448 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2449 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(7),
|
2450 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(7)
|
2451 |
|
|
);
|
2452 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_6 : FDC
|
2453 |
|
|
generic map(
|
2454 |
|
|
INIT => '0'
|
2455 |
|
|
)
|
2456 |
|
|
port map (
|
2457 |
|
|
C => rd_clk,
|
2458 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2459 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(6),
|
2460 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(6)
|
2461 |
|
|
);
|
2462 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_5 : FDC
|
2463 |
|
|
generic map(
|
2464 |
|
|
INIT => '0'
|
2465 |
|
|
)
|
2466 |
|
|
port map (
|
2467 |
|
|
C => rd_clk,
|
2468 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2469 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(5),
|
2470 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(5)
|
2471 |
|
|
);
|
2472 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_4 : FDC
|
2473 |
|
|
generic map(
|
2474 |
|
|
INIT => '0'
|
2475 |
|
|
)
|
2476 |
|
|
port map (
|
2477 |
|
|
C => rd_clk,
|
2478 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2479 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(4),
|
2480 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(4)
|
2481 |
|
|
);
|
2482 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_3 : FDC
|
2483 |
|
|
generic map(
|
2484 |
|
|
INIT => '0'
|
2485 |
|
|
)
|
2486 |
|
|
port map (
|
2487 |
|
|
C => rd_clk,
|
2488 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2489 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(3),
|
2490 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(3)
|
2491 |
|
|
);
|
2492 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_2 : FDC
|
2493 |
|
|
generic map(
|
2494 |
|
|
INIT => '0'
|
2495 |
|
|
)
|
2496 |
|
|
port map (
|
2497 |
|
|
C => rd_clk,
|
2498 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2499 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(2),
|
2500 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(2)
|
2501 |
|
|
);
|
2502 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_1 : FDC
|
2503 |
|
|
generic map(
|
2504 |
|
|
INIT => '0'
|
2505 |
|
|
)
|
2506 |
|
|
port map (
|
2507 |
|
|
C => rd_clk,
|
2508 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2509 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(1),
|
2510 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(1)
|
2511 |
|
|
);
|
2512 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_0 : FDC
|
2513 |
|
|
generic map(
|
2514 |
|
|
INIT => '0'
|
2515 |
|
|
)
|
2516 |
|
|
port map (
|
2517 |
|
|
C => rd_clk,
|
2518 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2519 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(0),
|
2520 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg(0)
|
2521 |
|
|
);
|
2522 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_9 : FDC
|
2523 |
|
|
generic map(
|
2524 |
|
|
INIT => '0'
|
2525 |
|
|
)
|
2526 |
|
|
port map (
|
2527 |
|
|
C => wr_clk,
|
2528 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2529 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(9),
|
2530 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(9)
|
2531 |
|
|
);
|
2532 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_8 : FDC
|
2533 |
|
|
generic map(
|
2534 |
|
|
INIT => '0'
|
2535 |
|
|
)
|
2536 |
|
|
port map (
|
2537 |
|
|
C => wr_clk,
|
2538 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2539 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(8),
|
2540 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(8)
|
2541 |
|
|
);
|
2542 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_7 : FDC
|
2543 |
|
|
generic map(
|
2544 |
|
|
INIT => '0'
|
2545 |
|
|
)
|
2546 |
|
|
port map (
|
2547 |
|
|
C => wr_clk,
|
2548 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2549 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(7),
|
2550 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(7)
|
2551 |
|
|
);
|
2552 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_6 : FDC
|
2553 |
|
|
generic map(
|
2554 |
|
|
INIT => '0'
|
2555 |
|
|
)
|
2556 |
|
|
port map (
|
2557 |
|
|
C => wr_clk,
|
2558 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2559 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(6),
|
2560 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(6)
|
2561 |
|
|
);
|
2562 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_5 : FDC
|
2563 |
|
|
generic map(
|
2564 |
|
|
INIT => '0'
|
2565 |
|
|
)
|
2566 |
|
|
port map (
|
2567 |
|
|
C => wr_clk,
|
2568 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2569 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(5),
|
2570 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(5)
|
2571 |
|
|
);
|
2572 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_4 : FDC
|
2573 |
|
|
generic map(
|
2574 |
|
|
INIT => '0'
|
2575 |
|
|
)
|
2576 |
|
|
port map (
|
2577 |
|
|
C => wr_clk,
|
2578 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2579 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(4),
|
2580 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(4)
|
2581 |
|
|
);
|
2582 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_3 : FDC
|
2583 |
|
|
generic map(
|
2584 |
|
|
INIT => '0'
|
2585 |
|
|
)
|
2586 |
|
|
port map (
|
2587 |
|
|
C => wr_clk,
|
2588 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2589 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(3),
|
2590 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(3)
|
2591 |
|
|
);
|
2592 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_2 : FDC
|
2593 |
|
|
generic map(
|
2594 |
|
|
INIT => '0'
|
2595 |
|
|
)
|
2596 |
|
|
port map (
|
2597 |
|
|
C => wr_clk,
|
2598 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2599 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(2),
|
2600 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(2)
|
2601 |
|
|
);
|
2602 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_1 : FDC
|
2603 |
|
|
generic map(
|
2604 |
|
|
INIT => '0'
|
2605 |
|
|
)
|
2606 |
|
|
port map (
|
2607 |
|
|
C => wr_clk,
|
2608 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2609 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(1),
|
2610 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(1)
|
2611 |
|
|
);
|
2612 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_0 : FDC
|
2613 |
|
|
generic map(
|
2614 |
|
|
INIT => '0'
|
2615 |
|
|
)
|
2616 |
|
|
port map (
|
2617 |
|
|
C => wr_clk,
|
2618 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2619 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(0),
|
2620 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg(0)
|
2621 |
|
|
);
|
2622 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_9 : FDC
|
2623 |
|
|
generic map(
|
2624 |
|
|
INIT => '0'
|
2625 |
|
|
)
|
2626 |
|
|
port map (
|
2627 |
|
|
C => rd_clk,
|
2628 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2629 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
2630 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(9)
|
2631 |
|
|
);
|
2632 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_8 : FDC
|
2633 |
|
|
generic map(
|
2634 |
|
|
INIT => '0'
|
2635 |
|
|
)
|
2636 |
|
|
port map (
|
2637 |
|
|
C => rd_clk,
|
2638 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2639 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_8_RD_PNTR_9_XOR_55_o,
|
2640 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(8)
|
2641 |
|
|
);
|
2642 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_7 : FDC
|
2643 |
|
|
generic map(
|
2644 |
|
|
INIT => '0'
|
2645 |
|
|
)
|
2646 |
|
|
port map (
|
2647 |
|
|
C => rd_clk,
|
2648 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2649 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_7_RD_PNTR_8_XOR_56_o,
|
2650 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(7)
|
2651 |
|
|
);
|
2652 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_6 : FDC
|
2653 |
|
|
generic map(
|
2654 |
|
|
INIT => '0'
|
2655 |
|
|
)
|
2656 |
|
|
port map (
|
2657 |
|
|
C => rd_clk,
|
2658 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2659 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_6_RD_PNTR_7_XOR_57_o,
|
2660 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(6)
|
2661 |
|
|
);
|
2662 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_5 : FDC
|
2663 |
|
|
generic map(
|
2664 |
|
|
INIT => '0'
|
2665 |
|
|
)
|
2666 |
|
|
port map (
|
2667 |
|
|
C => rd_clk,
|
2668 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2669 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_5_RD_PNTR_6_XOR_58_o,
|
2670 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(5)
|
2671 |
|
|
);
|
2672 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_4 : FDC
|
2673 |
|
|
generic map(
|
2674 |
|
|
INIT => '0'
|
2675 |
|
|
)
|
2676 |
|
|
port map (
|
2677 |
|
|
C => rd_clk,
|
2678 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2679 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_4_RD_PNTR_5_XOR_59_o,
|
2680 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(4)
|
2681 |
|
|
);
|
2682 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_3 : FDC
|
2683 |
|
|
generic map(
|
2684 |
|
|
INIT => '0'
|
2685 |
|
|
)
|
2686 |
|
|
port map (
|
2687 |
|
|
C => rd_clk,
|
2688 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2689 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_3_RD_PNTR_4_XOR_60_o,
|
2690 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(3)
|
2691 |
|
|
);
|
2692 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_2 : FDC
|
2693 |
|
|
generic map(
|
2694 |
|
|
INIT => '0'
|
2695 |
|
|
)
|
2696 |
|
|
port map (
|
2697 |
|
|
C => rd_clk,
|
2698 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2699 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_61_o,
|
2700 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(2)
|
2701 |
|
|
);
|
2702 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_1 : FDC
|
2703 |
|
|
generic map(
|
2704 |
|
|
INIT => '0'
|
2705 |
|
|
)
|
2706 |
|
|
port map (
|
2707 |
|
|
C => rd_clk,
|
2708 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2709 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_62_o,
|
2710 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(1)
|
2711 |
|
|
);
|
2712 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_0 : FDC
|
2713 |
|
|
generic map(
|
2714 |
|
|
INIT => '0'
|
2715 |
|
|
)
|
2716 |
|
|
port map (
|
2717 |
|
|
C => rd_clk,
|
2718 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(1),
|
2719 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_63_o,
|
2720 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc(0)
|
2721 |
|
|
);
|
2722 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_9 : FDC
|
2723 |
|
|
generic map(
|
2724 |
|
|
INIT => '0'
|
2725 |
|
|
)
|
2726 |
|
|
port map (
|
2727 |
|
|
C => wr_clk,
|
2728 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2729 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
2730 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(9)
|
2731 |
|
|
);
|
2732 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_8 : FDC
|
2733 |
|
|
generic map(
|
2734 |
|
|
INIT => '0'
|
2735 |
|
|
)
|
2736 |
|
|
port map (
|
2737 |
|
|
C => wr_clk,
|
2738 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2739 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_8_WR_PNTR_9_XOR_1_o,
|
2740 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(8)
|
2741 |
|
|
);
|
2742 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_7 : FDC
|
2743 |
|
|
generic map(
|
2744 |
|
|
INIT => '0'
|
2745 |
|
|
)
|
2746 |
|
|
port map (
|
2747 |
|
|
C => wr_clk,
|
2748 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2749 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_7_WR_PNTR_8_XOR_2_o,
|
2750 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(7)
|
2751 |
|
|
);
|
2752 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_6 : FDC
|
2753 |
|
|
generic map(
|
2754 |
|
|
INIT => '0'
|
2755 |
|
|
)
|
2756 |
|
|
port map (
|
2757 |
|
|
C => wr_clk,
|
2758 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2759 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_6_WR_PNTR_7_XOR_3_o,
|
2760 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(6)
|
2761 |
|
|
);
|
2762 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_5 : FDC
|
2763 |
|
|
generic map(
|
2764 |
|
|
INIT => '0'
|
2765 |
|
|
)
|
2766 |
|
|
port map (
|
2767 |
|
|
C => wr_clk,
|
2768 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2769 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_5_WR_PNTR_6_XOR_4_o,
|
2770 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(5)
|
2771 |
|
|
);
|
2772 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_4 : FDC
|
2773 |
|
|
generic map(
|
2774 |
|
|
INIT => '0'
|
2775 |
|
|
)
|
2776 |
|
|
port map (
|
2777 |
|
|
C => wr_clk,
|
2778 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2779 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_4_WR_PNTR_5_XOR_5_o,
|
2780 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(4)
|
2781 |
|
|
);
|
2782 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_3 : FDC
|
2783 |
|
|
generic map(
|
2784 |
|
|
INIT => '0'
|
2785 |
|
|
)
|
2786 |
|
|
port map (
|
2787 |
|
|
C => wr_clk,
|
2788 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2789 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_3_WR_PNTR_4_XOR_6_o,
|
2790 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(3)
|
2791 |
|
|
);
|
2792 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_2 : FDC
|
2793 |
|
|
generic map(
|
2794 |
|
|
INIT => '0'
|
2795 |
|
|
)
|
2796 |
|
|
port map (
|
2797 |
|
|
C => wr_clk,
|
2798 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2799 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_7_o,
|
2800 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(2)
|
2801 |
|
|
);
|
2802 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_1 : FDC
|
2803 |
|
|
generic map(
|
2804 |
|
|
INIT => '0'
|
2805 |
|
|
)
|
2806 |
|
|
port map (
|
2807 |
|
|
C => wr_clk,
|
2808 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2809 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_8_o,
|
2810 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(1)
|
2811 |
|
|
);
|
2812 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_0 : FDC
|
2813 |
|
|
generic map(
|
2814 |
|
|
INIT => '0'
|
2815 |
|
|
)
|
2816 |
|
|
port map (
|
2817 |
|
|
C => wr_clk,
|
2818 |
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
2819 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_9_o,
|
2820 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc(0)
|
2821 |
|
|
);
|
2822 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
|
2823 |
|
|
generic map(
|
2824 |
|
|
INIT => X"2"
|
2825 |
|
|
)
|
2826 |
|
|
port map (
|
2827 |
|
|
I0 => rd_en,
|
2828 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35,
|
2829 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
|
2830 |
|
|
);
|
2831 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
|
2832 |
|
|
generic map(
|
2833 |
|
|
INIT => X"2"
|
2834 |
|
|
)
|
2835 |
|
|
port map (
|
2836 |
|
|
I0 => wr_en,
|
2837 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
2838 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
|
2839 |
|
|
);
|
2840 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o1 : LUT4
|
2841 |
|
|
generic map(
|
2842 |
|
|
INIT => X"F2F0"
|
2843 |
|
|
)
|
2844 |
|
|
port map (
|
2845 |
|
|
I0 => rd_en,
|
2846 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35,
|
2847 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0,
|
2848 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp1,
|
2849 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_comp0_comp1_OR_3_o
|
2850 |
|
|
);
|
2851 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_Mmux_comp1_GND_38_o_MUX_27_o11 : LUT5
|
2852 |
|
|
generic map(
|
2853 |
|
|
INIT => X"33023300"
|
2854 |
|
|
)
|
2855 |
|
|
port map (
|
2856 |
|
|
I0 => wr_en,
|
2857 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_49,
|
2858 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
2859 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1,
|
2860 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp2,
|
2861 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_comp1_GND_38_o_MUX_27_o
|
2862 |
|
|
);
|
2863 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
|
2864 |
|
|
generic map(
|
2865 |
|
|
INIT => X"2"
|
2866 |
|
|
)
|
2867 |
|
|
port map (
|
2868 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_117,
|
2869 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_118,
|
2870 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
|
2871 |
|
|
);
|
2872 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
|
2873 |
|
|
generic map(
|
2874 |
|
|
INIT => X"2"
|
2875 |
|
|
)
|
2876 |
|
|
port map (
|
2877 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_120,
|
2878 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_121,
|
2879 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
|
2880 |
|
|
);
|
2881 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1_4_1 : LUT4
|
2882 |
|
|
generic map(
|
2883 |
|
|
INIT => X"9009"
|
2884 |
|
|
)
|
2885 |
|
|
port map (
|
2886 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(9),
|
2887 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(9),
|
2888 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(8),
|
2889 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(8),
|
2890 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(4)
|
2891 |
|
|
);
|
2892 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1_3_1 : LUT4
|
2893 |
|
|
generic map(
|
2894 |
|
|
INIT => X"9009"
|
2895 |
|
|
)
|
2896 |
|
|
port map (
|
2897 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(7),
|
2898 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(7),
|
2899 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(6),
|
2900 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(6),
|
2901 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(3)
|
2902 |
|
|
);
|
2903 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1_2_1 : LUT4
|
2904 |
|
|
generic map(
|
2905 |
|
|
INIT => X"9009"
|
2906 |
|
|
)
|
2907 |
|
|
port map (
|
2908 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(5),
|
2909 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(5),
|
2910 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(4),
|
2911 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(4),
|
2912 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(2)
|
2913 |
|
|
);
|
2914 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1_1_1 : LUT4
|
2915 |
|
|
generic map(
|
2916 |
|
|
INIT => X"9009"
|
2917 |
|
|
)
|
2918 |
|
|
port map (
|
2919 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3),
|
2920 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
2921 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2),
|
2922 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
2923 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(1)
|
2924 |
|
|
);
|
2925 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1_0_1 : LUT4
|
2926 |
|
|
generic map(
|
2927 |
|
|
INIT => X"9009"
|
2928 |
|
|
)
|
2929 |
|
|
port map (
|
2930 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1),
|
2931 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1),
|
2932 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0),
|
2933 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
2934 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c1_v1(0)
|
2935 |
|
|
);
|
2936 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1_4_1 : LUT4
|
2937 |
|
|
generic map(
|
2938 |
|
|
INIT => X"9009"
|
2939 |
|
|
)
|
2940 |
|
|
port map (
|
2941 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(9),
|
2942 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(9),
|
2943 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(8),
|
2944 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(8),
|
2945 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(4)
|
2946 |
|
|
);
|
2947 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1_3_1 : LUT4
|
2948 |
|
|
generic map(
|
2949 |
|
|
INIT => X"9009"
|
2950 |
|
|
)
|
2951 |
|
|
port map (
|
2952 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(7),
|
2953 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7),
|
2954 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(6),
|
2955 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
2956 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(3)
|
2957 |
|
|
);
|
2958 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1_2_1 : LUT4
|
2959 |
|
|
generic map(
|
2960 |
|
|
INIT => X"9009"
|
2961 |
|
|
)
|
2962 |
|
|
port map (
|
2963 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(5),
|
2964 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
2965 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(4),
|
2966 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
2967 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(2)
|
2968 |
|
|
);
|
2969 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1_1_1 : LUT4
|
2970 |
|
|
generic map(
|
2971 |
|
|
INIT => X"9009"
|
2972 |
|
|
)
|
2973 |
|
|
port map (
|
2974 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3),
|
2975 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
2976 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2),
|
2977 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
2978 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(1)
|
2979 |
|
|
);
|
2980 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1_4_1 : LUT4
|
2981 |
|
|
generic map(
|
2982 |
|
|
INIT => X"9009"
|
2983 |
|
|
)
|
2984 |
|
|
port map (
|
2985 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
2986 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(9),
|
2987 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
2988 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(8),
|
2989 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(4)
|
2990 |
|
|
);
|
2991 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1_3_1 : LUT4
|
2992 |
|
|
generic map(
|
2993 |
|
|
INIT => X"9009"
|
2994 |
|
|
)
|
2995 |
|
|
port map (
|
2996 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
2997 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(7),
|
2998 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
2999 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(6),
|
3000 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(3)
|
3001 |
|
|
);
|
3002 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1_2_1 : LUT4
|
3003 |
|
|
generic map(
|
3004 |
|
|
INIT => X"9009"
|
3005 |
|
|
)
|
3006 |
|
|
port map (
|
3007 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
3008 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(5),
|
3009 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
3010 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(4),
|
3011 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(2)
|
3012 |
|
|
);
|
3013 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1_1_1 : LUT4
|
3014 |
|
|
generic map(
|
3015 |
|
|
INIT => X"9009"
|
3016 |
|
|
)
|
3017 |
|
|
port map (
|
3018 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
3019 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
3020 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
3021 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
3022 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(1)
|
3023 |
|
|
);
|
3024 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1_0_1 : LUT4
|
3025 |
|
|
generic map(
|
3026 |
|
|
INIT => X"9009"
|
3027 |
|
|
)
|
3028 |
|
|
port map (
|
3029 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
3030 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
3031 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
3032 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0),
|
3033 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c0_v1(0)
|
3034 |
|
|
);
|
3035 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1_4_1 : LUT4
|
3036 |
|
|
generic map(
|
3037 |
|
|
INIT => X"9009"
|
3038 |
|
|
)
|
3039 |
|
|
port map (
|
3040 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
3041 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(9),
|
3042 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
3043 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(8),
|
3044 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(4)
|
3045 |
|
|
);
|
3046 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1_3_1 : LUT4
|
3047 |
|
|
generic map(
|
3048 |
|
|
INIT => X"9009"
|
3049 |
|
|
)
|
3050 |
|
|
port map (
|
3051 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
3052 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(7),
|
3053 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
3054 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(6),
|
3055 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(3)
|
3056 |
|
|
);
|
3057 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1_2_1 : LUT4
|
3058 |
|
|
generic map(
|
3059 |
|
|
INIT => X"8241"
|
3060 |
|
|
)
|
3061 |
|
|
port map (
|
3062 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(4),
|
3063 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(5),
|
3064 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
3065 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
3066 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(2)
|
3067 |
|
|
);
|
3068 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1_1_1 : LUT4
|
3069 |
|
|
generic map(
|
3070 |
|
|
INIT => X"8421"
|
3071 |
|
|
)
|
3072 |
|
|
port map (
|
3073 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
3074 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
3075 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
3076 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
3077 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(1)
|
3078 |
|
|
);
|
3079 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT811 : LUT5
|
3080 |
|
|
generic map(
|
3081 |
|
|
INIT => X"FFFF7FFF"
|
3082 |
|
|
)
|
3083 |
|
|
port map (
|
3084 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
3085 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
3086 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
3087 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
3088 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41,
|
3089 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT81_204
|
3090 |
|
|
);
|
3091 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT1031 : LUT5
|
3092 |
|
|
generic map(
|
3093 |
|
|
INIT => X"00008000"
|
3094 |
|
|
)
|
3095 |
|
|
port map (
|
3096 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
3097 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
3098 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
3099 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
3100 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41,
|
3101 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT103
|
3102 |
|
|
);
|
3103 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT71 : LUT5
|
3104 |
|
|
generic map(
|
3105 |
|
|
INIT => X"AAAA6AAA"
|
3106 |
|
|
)
|
3107 |
|
|
port map (
|
3108 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
3109 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
3110 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
3111 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
3112 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41,
|
3113 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_6_Q
|
3114 |
|
|
);
|
3115 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT101 : LUT5
|
3116 |
|
|
generic map(
|
3117 |
|
|
INIT => X"EAAA6A2A"
|
3118 |
|
|
)
|
3119 |
|
|
port map (
|
3120 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
3121 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
3122 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
3123 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT103,
|
3124 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT81_204,
|
3125 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_9_Q
|
3126 |
|
|
);
|
3127 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_6_1 : LUT5
|
3128 |
|
|
generic map(
|
3129 |
|
|
INIT => X"AAAA6AAA"
|
3130 |
|
|
)
|
3131 |
|
|
port map (
|
3132 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
3133 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
3134 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
3135 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
3136 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_bdd0,
|
3137 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_6_Q
|
3138 |
|
|
);
|
3139 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_7_1 : LUT6
|
3140 |
|
|
generic map(
|
3141 |
|
|
INIT => X"CCCCCCCC6CCCCCCC"
|
3142 |
|
|
)
|
3143 |
|
|
port map (
|
3144 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
3145 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7),
|
3146 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
3147 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
3148 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
3149 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_bdd0,
|
3150 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_7_Q
|
3151 |
|
|
);
|
3152 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_17_o1 : LUT2
|
3153 |
|
|
generic map(
|
3154 |
|
|
INIT => X"6"
|
3155 |
|
|
)
|
3156 |
|
|
port map (
|
3157 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3158 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3159 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_17_o
|
3160 |
|
|
);
|
3161 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_18_o1 : LUT3
|
3162 |
|
|
generic map(
|
3163 |
|
|
INIT => X"96"
|
3164 |
|
|
)
|
3165 |
|
|
port map (
|
3166 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3167 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3168 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3169 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_18_o
|
3170 |
|
|
);
|
3171 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_4_o1 : LUT2
|
3172 |
|
|
generic map(
|
3173 |
|
|
INIT => X"6"
|
3174 |
|
|
)
|
3175 |
|
|
port map (
|
3176 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3177 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3178 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_4_o
|
3179 |
|
|
);
|
3180 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_5_o1 : LUT3
|
3181 |
|
|
generic map(
|
3182 |
|
|
INIT => X"96"
|
3183 |
|
|
)
|
3184 |
|
|
port map (
|
3185 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3186 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3187 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3188 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_5_o
|
3189 |
|
|
);
|
3190 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_8_WR_PNTR_9_XOR_1_o_xo_0_1 : LUT2
|
3191 |
|
|
generic map(
|
3192 |
|
|
INIT => X"6"
|
3193 |
|
|
)
|
3194 |
|
|
port map (
|
3195 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3196 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3197 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_8_WR_PNTR_9_XOR_1_o
|
3198 |
|
|
);
|
3199 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_7_WR_PNTR_8_XOR_2_o_xo_0_1 : LUT2
|
3200 |
|
|
generic map(
|
3201 |
|
|
INIT => X"6"
|
3202 |
|
|
)
|
3203 |
|
|
port map (
|
3204 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3205 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3206 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_7_WR_PNTR_8_XOR_2_o
|
3207 |
|
|
);
|
3208 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_6_WR_PNTR_7_XOR_3_o_xo_0_1 : LUT2
|
3209 |
|
|
generic map(
|
3210 |
|
|
INIT => X"6"
|
3211 |
|
|
)
|
3212 |
|
|
port map (
|
3213 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
3214 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3215 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_6_WR_PNTR_7_XOR_3_o
|
3216 |
|
|
);
|
3217 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_5_WR_PNTR_6_XOR_4_o_xo_0_1 : LUT2
|
3218 |
|
|
generic map(
|
3219 |
|
|
INIT => X"6"
|
3220 |
|
|
)
|
3221 |
|
|
port map (
|
3222 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
3223 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(6),
|
3224 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_5_WR_PNTR_6_XOR_4_o
|
3225 |
|
|
);
|
3226 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_4_WR_PNTR_5_XOR_5_o_xo_0_1 : LUT2
|
3227 |
|
|
generic map(
|
3228 |
|
|
INIT => X"6"
|
3229 |
|
|
)
|
3230 |
|
|
port map (
|
3231 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
3232 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(5),
|
3233 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_4_WR_PNTR_5_XOR_5_o
|
3234 |
|
|
);
|
3235 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_3_WR_PNTR_4_XOR_6_o_xo_0_1 : LUT2
|
3236 |
|
|
generic map(
|
3237 |
|
|
INIT => X"6"
|
3238 |
|
|
)
|
3239 |
|
|
port map (
|
3240 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
3241 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(4),
|
3242 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_3_WR_PNTR_4_XOR_6_o
|
3243 |
|
|
);
|
3244 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_2_WR_PNTR_3_XOR_7_o_xo_0_1 : LUT2
|
3245 |
|
|
generic map(
|
3246 |
|
|
INIT => X"6"
|
3247 |
|
|
)
|
3248 |
|
|
port map (
|
3249 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
3250 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(3),
|
3251 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_2_WR_PNTR_3_XOR_7_o
|
3252 |
|
|
);
|
3253 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_8_RD_PNTR_9_XOR_55_o_xo_0_1 : LUT2
|
3254 |
|
|
generic map(
|
3255 |
|
|
INIT => X"6"
|
3256 |
|
|
)
|
3257 |
|
|
port map (
|
3258 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
3259 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
3260 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_8_RD_PNTR_9_XOR_55_o
|
3261 |
|
|
);
|
3262 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_7_RD_PNTR_8_XOR_56_o_xo_0_1 : LUT2
|
3263 |
|
|
generic map(
|
3264 |
|
|
INIT => X"6"
|
3265 |
|
|
)
|
3266 |
|
|
port map (
|
3267 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
3268 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
3269 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_7_RD_PNTR_8_XOR_56_o
|
3270 |
|
|
);
|
3271 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_6_RD_PNTR_7_XOR_57_o_xo_0_1 : LUT2
|
3272 |
|
|
generic map(
|
3273 |
|
|
INIT => X"6"
|
3274 |
|
|
)
|
3275 |
|
|
port map (
|
3276 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
3277 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
3278 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_6_RD_PNTR_7_XOR_57_o
|
3279 |
|
|
);
|
3280 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_5_RD_PNTR_6_XOR_58_o_xo_0_1 : LUT2
|
3281 |
|
|
generic map(
|
3282 |
|
|
INIT => X"6"
|
3283 |
|
|
)
|
3284 |
|
|
port map (
|
3285 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
3286 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
3287 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_5_RD_PNTR_6_XOR_58_o
|
3288 |
|
|
);
|
3289 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_4_RD_PNTR_5_XOR_59_o_xo_0_1 : LUT2
|
3290 |
|
|
generic map(
|
3291 |
|
|
INIT => X"6"
|
3292 |
|
|
)
|
3293 |
|
|
port map (
|
3294 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
3295 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
3296 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_4_RD_PNTR_5_XOR_59_o
|
3297 |
|
|
);
|
3298 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_3_RD_PNTR_4_XOR_60_o_xo_0_1 : LUT2
|
3299 |
|
|
generic map(
|
3300 |
|
|
INIT => X"6"
|
3301 |
|
|
)
|
3302 |
|
|
port map (
|
3303 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
3304 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
3305 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_3_RD_PNTR_4_XOR_60_o
|
3306 |
|
|
);
|
3307 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_2_RD_PNTR_3_XOR_61_o_xo_0_1 : LUT2
|
3308 |
|
|
generic map(
|
3309 |
|
|
INIT => X"6"
|
3310 |
|
|
)
|
3311 |
|
|
port map (
|
3312 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
3313 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
3314 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_2_RD_PNTR_3_XOR_61_o
|
3315 |
|
|
);
|
3316 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_1_RD_PNTR_2_XOR_62_o_xo_0_1 : LUT2
|
3317 |
|
|
generic map(
|
3318 |
|
|
INIT => X"6"
|
3319 |
|
|
)
|
3320 |
|
|
port map (
|
3321 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
3322 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
3323 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_1_RD_PNTR_2_XOR_62_o
|
3324 |
|
|
);
|
3325 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_RD_PNTR_0_RD_PNTR_1_XOR_63_o_xo_0_1 : LUT2
|
3326 |
|
|
generic map(
|
3327 |
|
|
INIT => X"6"
|
3328 |
|
|
)
|
3329 |
|
|
port map (
|
3330 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
3331 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
3332 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_RD_PNTR_0_RD_PNTR_1_XOR_63_o
|
3333 |
|
|
);
|
3334 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_191_xo_0_1 : LUT4
|
3335 |
|
|
generic map(
|
3336 |
|
|
INIT => X"6996"
|
3337 |
|
|
)
|
3338 |
|
|
port map (
|
3339 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3340 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3341 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3342 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3343 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_19_o
|
3344 |
|
|
);
|
3345 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_201_xo_0_1 : LUT5
|
3346 |
|
|
generic map(
|
3347 |
|
|
INIT => X"96696996"
|
3348 |
|
|
)
|
3349 |
|
|
port map (
|
3350 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3351 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3352 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3353 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3354 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3355 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_20_o
|
3356 |
|
|
);
|
3357 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_211_xo_0_1 : LUT6
|
3358 |
|
|
generic map(
|
3359 |
|
|
INIT => X"6996966996696996"
|
3360 |
|
|
)
|
3361 |
|
|
port map (
|
3362 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4),
|
3363 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3364 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3365 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3366 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3367 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3368 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_21_o
|
3369 |
|
|
);
|
3370 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_61_xo_0_1 : LUT4
|
3371 |
|
|
generic map(
|
3372 |
|
|
INIT => X"6996"
|
3373 |
|
|
)
|
3374 |
|
|
port map (
|
3375 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3376 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3377 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3378 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3379 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_6_o
|
3380 |
|
|
);
|
3381 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_71_xo_0_1 : LUT5
|
3382 |
|
|
generic map(
|
3383 |
|
|
INIT => X"96696996"
|
3384 |
|
|
)
|
3385 |
|
|
port map (
|
3386 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3387 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3388 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3389 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3390 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3391 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_7_o
|
3392 |
|
|
);
|
3393 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_81_xo_0_1 : LUT6
|
3394 |
|
|
generic map(
|
3395 |
|
|
INIT => X"6996966996696996"
|
3396 |
|
|
)
|
3397 |
|
|
port map (
|
3398 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4),
|
3399 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3400 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3401 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3402 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3403 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3404 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_8_o
|
3405 |
|
|
);
|
3406 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_9_GND_33_o_LessThan_7_o1_SW0 : LUT5
|
3407 |
|
|
generic map(
|
3408 |
|
|
INIT => X"FFFFFFFE"
|
3409 |
|
|
)
|
3410 |
|
|
port map (
|
3411 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(4),
|
3412 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(7),
|
3413 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(3),
|
3414 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(6),
|
3415 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(10),
|
3416 |
|
|
O => N01
|
3417 |
|
|
);
|
3418 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_251_xo_0_SW0 : LUT5
|
3419 |
|
|
generic map(
|
3420 |
|
|
INIT => X"69969669"
|
3421 |
|
|
)
|
3422 |
|
|
port map (
|
3423 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(0),
|
3424 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3425 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3426 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3427 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3428 |
|
|
O => N81
|
3429 |
|
|
);
|
3430 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_251_xo_0_Q : LUT6
|
3431 |
|
|
generic map(
|
3432 |
|
|
INIT => X"9669699669969669"
|
3433 |
|
|
)
|
3434 |
|
|
port map (
|
3435 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
3436 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
3437 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3438 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4),
|
3439 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1),
|
3440 |
|
|
I5 => N81,
|
3441 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_25_o
|
3442 |
|
|
);
|
3443 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_121_xo_0_SW0 : LUT5
|
3444 |
|
|
generic map(
|
3445 |
|
|
INIT => X"69969669"
|
3446 |
|
|
)
|
3447 |
|
|
port map (
|
3448 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(0),
|
3449 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3450 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3451 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3452 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3453 |
|
|
O => N10
|
3454 |
|
|
);
|
3455 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_121_xo_0_Q : LUT6
|
3456 |
|
|
generic map(
|
3457 |
|
|
INIT => X"9669699669969669"
|
3458 |
|
|
)
|
3459 |
|
|
port map (
|
3460 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
3461 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
3462 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3463 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4),
|
3464 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1),
|
3465 |
|
|
I5 => N10,
|
3466 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_12_o
|
3467 |
|
|
);
|
3468 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_221_xo_0_SW0 : LUT2
|
3469 |
|
|
generic map(
|
3470 |
|
|
INIT => X"6"
|
3471 |
|
|
)
|
3472 |
|
|
port map (
|
3473 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3474 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3475 |
|
|
O => N12
|
3476 |
|
|
);
|
3477 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_221_xo_0_Q : LUT6
|
3478 |
|
|
generic map(
|
3479 |
|
|
INIT => X"6996966996696996"
|
3480 |
|
|
)
|
3481 |
|
|
port map (
|
3482 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
3483 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3484 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4),
|
3485 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3486 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3487 |
|
|
I5 => N12,
|
3488 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_22_o
|
3489 |
|
|
);
|
3490 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_231_xo_0_SW0 : LUT3
|
3491 |
|
|
generic map(
|
3492 |
|
|
INIT => X"69"
|
3493 |
|
|
)
|
3494 |
|
|
port map (
|
3495 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(8),
|
3496 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(7),
|
3497 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(6),
|
3498 |
|
|
O => N14
|
3499 |
|
|
);
|
3500 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_231_xo_0_Q : LUT6
|
3501 |
|
|
generic map(
|
3502 |
|
|
INIT => X"9669699669969669"
|
3503 |
|
|
)
|
3504 |
|
|
port map (
|
3505 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
3506 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
3507 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3508 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4),
|
3509 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(9),
|
3510 |
|
|
I5 => N14,
|
3511 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_23_o
|
3512 |
|
|
);
|
3513 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_241_xo_0_Q : LUT6
|
3514 |
|
|
generic map(
|
3515 |
|
|
INIT => X"6996966996696996"
|
3516 |
|
|
)
|
3517 |
|
|
port map (
|
3518 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(3),
|
3519 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(2),
|
3520 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(5),
|
3521 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(4),
|
3522 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last(1),
|
3523 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_19_o,
|
3524 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_gc_asreg_last_9_reduce_xor_24_o
|
3525 |
|
|
);
|
3526 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_91_xo_0_SW0 : LUT2
|
3527 |
|
|
generic map(
|
3528 |
|
|
INIT => X"6"
|
3529 |
|
|
)
|
3530 |
|
|
port map (
|
3531 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3532 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3533 |
|
|
O => N18
|
3534 |
|
|
);
|
3535 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_91_xo_0_Q : LUT6
|
3536 |
|
|
generic map(
|
3537 |
|
|
INIT => X"6996966996696996"
|
3538 |
|
|
)
|
3539 |
|
|
port map (
|
3540 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
3541 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3542 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4),
|
3543 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3544 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3545 |
|
|
I5 => N18,
|
3546 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_9_o
|
3547 |
|
|
);
|
3548 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_101_xo_0_SW0 : LUT3
|
3549 |
|
|
generic map(
|
3550 |
|
|
INIT => X"69"
|
3551 |
|
|
)
|
3552 |
|
|
port map (
|
3553 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(8),
|
3554 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(7),
|
3555 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(6),
|
3556 |
|
|
O => N20
|
3557 |
|
|
);
|
3558 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_101_xo_0_Q : LUT6
|
3559 |
|
|
generic map(
|
3560 |
|
|
INIT => X"9669699669969669"
|
3561 |
|
|
)
|
3562 |
|
|
port map (
|
3563 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
3564 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
3565 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3566 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4),
|
3567 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(9),
|
3568 |
|
|
I5 => N20,
|
3569 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_10_o
|
3570 |
|
|
);
|
3571 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_111_xo_0_Q : LUT6
|
3572 |
|
|
generic map(
|
3573 |
|
|
INIT => X"6996966996696996"
|
3574 |
|
|
)
|
3575 |
|
|
port map (
|
3576 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(3),
|
3577 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(2),
|
3578 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(5),
|
3579 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(4),
|
3580 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last(1),
|
3581 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_6_o,
|
3582 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_gc_asreg_last_9_reduce_xor_11_o
|
3583 |
|
|
);
|
3584 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot : LUT3
|
3585 |
|
|
generic map(
|
3586 |
|
|
INIT => X"D8"
|
3587 |
|
|
)
|
3588 |
|
|
port map (
|
3589 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_122,
|
3590 |
|
|
I1 => N1,
|
3591 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_120,
|
3592 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_364
|
3593 |
|
|
);
|
3594 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDP
|
3595 |
|
|
port map (
|
3596 |
|
|
C => wr_clk,
|
3597 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_rstpot_364,
|
3598 |
|
|
PRE => rst,
|
3599 |
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_120
|
3600 |
|
|
);
|
3601 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i : FDP
|
3602 |
|
|
generic map(
|
3603 |
|
|
INIT => '1'
|
3604 |
|
|
)
|
3605 |
|
|
port map (
|
3606 |
|
|
C => rd_clk,
|
3607 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i_rstpot_365,
|
3608 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg(2),
|
3609 |
|
|
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i
|
3610 |
|
|
);
|
3611 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i : FDP
|
3612 |
|
|
generic map(
|
3613 |
|
|
INIT => '1'
|
3614 |
|
|
)
|
3615 |
|
|
port map (
|
3616 |
|
|
C => wr_clk,
|
3617 |
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i_rstpot_366,
|
3618 |
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_48,
|
3619 |
|
|
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i
|
3620 |
|
|
);
|
3621 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1_0_1 : LUT4
|
3622 |
|
|
generic map(
|
3623 |
|
|
INIT => X"0990"
|
3624 |
|
|
)
|
3625 |
|
|
port map (
|
3626 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1),
|
3627 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
3628 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0),
|
3629 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
3630 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_c2_v1(0)
|
3631 |
|
|
);
|
3632 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1_0_1 : LUT4
|
3633 |
|
|
generic map(
|
3634 |
|
|
INIT => X"4182"
|
3635 |
|
|
)
|
3636 |
|
|
port map (
|
3637 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0),
|
3638 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
3639 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
3640 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
3641 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_c1_v1(0)
|
3642 |
|
|
);
|
3643 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT81 : LUT6
|
3644 |
|
|
generic map(
|
3645 |
|
|
INIT => X"CCCCCCCC6CCCCCCC"
|
3646 |
|
|
)
|
3647 |
|
|
port map (
|
3648 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
3649 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
3650 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
3651 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
3652 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
3653 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41,
|
3654 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_7_Q
|
3655 |
|
|
);
|
3656 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT411 : LUT3
|
3657 |
|
|
generic map(
|
3658 |
|
|
INIT => X"DF"
|
3659 |
|
|
)
|
3660 |
|
|
port map (
|
3661 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
3662 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
3663 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
3664 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41
|
3665 |
|
|
);
|
3666 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_1_Q :
|
3667 |
|
|
LUT2
|
3668 |
|
|
generic map(
|
3669 |
|
|
INIT => X"9"
|
3670 |
|
|
)
|
3671 |
|
|
port map (
|
3672 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
3673 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(0),
|
3674 |
|
|
O =>
|
3675 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_1_Q_233
|
3676 |
|
|
|
3677 |
|
|
);
|
3678 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_2_Q :
|
3679 |
|
|
LUT2
|
3680 |
|
|
generic map(
|
3681 |
|
|
INIT => X"9"
|
3682 |
|
|
)
|
3683 |
|
|
port map (
|
3684 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(1),
|
3685 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
3686 |
|
|
O =>
|
3687 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_2_Q_177
|
3688 |
|
|
|
3689 |
|
|
);
|
3690 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_2_Q :
|
3691 |
|
|
LUT2
|
3692 |
|
|
generic map(
|
3693 |
|
|
INIT => X"9"
|
3694 |
|
|
)
|
3695 |
|
|
port map (
|
3696 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(1),
|
3697 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(1),
|
3698 |
|
|
O =>
|
3699 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_2_Q_231
|
3700 |
|
|
|
3701 |
|
|
);
|
3702 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_3_Q :
|
3703 |
|
|
LUT2
|
3704 |
|
|
generic map(
|
3705 |
|
|
INIT => X"9"
|
3706 |
|
|
)
|
3707 |
|
|
port map (
|
3708 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(2),
|
3709 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
3710 |
|
|
O =>
|
3711 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_3_Q_175
|
3712 |
|
|
|
3713 |
|
|
);
|
3714 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_3_Q :
|
3715 |
|
|
LUT2
|
3716 |
|
|
generic map(
|
3717 |
|
|
INIT => X"9"
|
3718 |
|
|
)
|
3719 |
|
|
port map (
|
3720 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(2),
|
3721 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(2),
|
3722 |
|
|
O =>
|
3723 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_3_Q_229
|
3724 |
|
|
|
3725 |
|
|
);
|
3726 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_4_Q :
|
3727 |
|
|
LUT2
|
3728 |
|
|
generic map(
|
3729 |
|
|
INIT => X"9"
|
3730 |
|
|
)
|
3731 |
|
|
port map (
|
3732 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(3),
|
3733 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
3734 |
|
|
O =>
|
3735 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_4_Q_173
|
3736 |
|
|
|
3737 |
|
|
);
|
3738 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_4_Q :
|
3739 |
|
|
LUT2
|
3740 |
|
|
generic map(
|
3741 |
|
|
INIT => X"9"
|
3742 |
|
|
)
|
3743 |
|
|
port map (
|
3744 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(3),
|
3745 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(3),
|
3746 |
|
|
O =>
|
3747 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_4_Q_227
|
3748 |
|
|
|
3749 |
|
|
);
|
3750 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_5_Q :
|
3751 |
|
|
LUT2
|
3752 |
|
|
generic map(
|
3753 |
|
|
INIT => X"9"
|
3754 |
|
|
)
|
3755 |
|
|
port map (
|
3756 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(4),
|
3757 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
3758 |
|
|
O =>
|
3759 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_5_Q_171
|
3760 |
|
|
|
3761 |
|
|
);
|
3762 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_5_Q :
|
3763 |
|
|
LUT2
|
3764 |
|
|
generic map(
|
3765 |
|
|
INIT => X"9"
|
3766 |
|
|
)
|
3767 |
|
|
port map (
|
3768 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(4),
|
3769 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(4),
|
3770 |
|
|
O =>
|
3771 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_5_Q_225
|
3772 |
|
|
|
3773 |
|
|
);
|
3774 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_1_Q :
|
3775 |
|
|
LUT2
|
3776 |
|
|
generic map(
|
3777 |
|
|
INIT => X"9"
|
3778 |
|
|
)
|
3779 |
|
|
port map (
|
3780 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(0),
|
3781 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
3782 |
|
|
O =>
|
3783 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_1_Q_179
|
3784 |
|
|
|
3785 |
|
|
);
|
3786 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad_0_1 : LUT2
|
3787 |
|
|
generic map(
|
3788 |
|
|
INIT => X"D"
|
3789 |
|
|
)
|
3790 |
|
|
port map (
|
3791 |
|
|
I0 => rd_en,
|
3792 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35,
|
3793 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_adjusted_wr_pntr_rd_pad(0)
|
3794 |
|
|
);
|
3795 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i_rstpot_SW0 : LUT3
|
3796 |
|
|
generic map(
|
3797 |
|
|
INIT => X"FE"
|
3798 |
|
|
)
|
3799 |
|
|
port map (
|
3800 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(5),
|
3801 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(8),
|
3802 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(9),
|
3803 |
|
|
O => N24
|
3804 |
|
|
);
|
3805 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i_rstpot : LUT6
|
3806 |
|
|
generic map(
|
3807 |
|
|
INIT => X"AA00AA00AA00AA3F"
|
3808 |
|
|
)
|
3809 |
|
|
port map (
|
3810 |
|
|
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i,
|
3811 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(1),
|
3812 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_diff_pntr_pad(2),
|
3813 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_rsts_ram_empty_fb_i_35,
|
3814 |
|
|
I4 => N24,
|
3815 |
|
|
I5 => N01,
|
3816 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_prog_empty_i_rstpot_365
|
3817 |
|
|
);
|
3818 |
|
|
write_ctrl : LUT5
|
3819 |
|
|
generic map(
|
3820 |
|
|
INIT => X"00000002"
|
3821 |
|
|
)
|
3822 |
|
|
port map (
|
3823 |
|
|
I0 => wr_en,
|
3824 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3825 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3826 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3827 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3828 |
|
|
O => write_ctrl_97
|
3829 |
|
|
);
|
3830 |
|
|
write_ctrl1 : LUT5
|
3831 |
|
|
generic map(
|
3832 |
|
|
INIT => X"00000200"
|
3833 |
|
|
)
|
3834 |
|
|
port map (
|
3835 |
|
|
I0 => wr_en,
|
3836 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3837 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3838 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3839 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3840 |
|
|
O => write_ctrl1_98
|
3841 |
|
|
);
|
3842 |
|
|
write_ctrl2 : LUT5
|
3843 |
|
|
generic map(
|
3844 |
|
|
INIT => X"00000200"
|
3845 |
|
|
)
|
3846 |
|
|
port map (
|
3847 |
|
|
I0 => wr_en,
|
3848 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3849 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3850 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3851 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3852 |
|
|
O => write_ctrl2_99
|
3853 |
|
|
);
|
3854 |
|
|
write_ctrl3 : LUT5
|
3855 |
|
|
generic map(
|
3856 |
|
|
INIT => X"00002000"
|
3857 |
|
|
)
|
3858 |
|
|
port map (
|
3859 |
|
|
I0 => wr_en,
|
3860 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3861 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3862 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3863 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3864 |
|
|
O => write_ctrl3_100
|
3865 |
|
|
);
|
3866 |
|
|
write_ctrl4 : LUT5
|
3867 |
|
|
generic map(
|
3868 |
|
|
INIT => X"00000200"
|
3869 |
|
|
)
|
3870 |
|
|
port map (
|
3871 |
|
|
I0 => wr_en,
|
3872 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3873 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3874 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3875 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3876 |
|
|
O => write_ctrl4_101
|
3877 |
|
|
);
|
3878 |
|
|
write_ctrl5 : LUT5
|
3879 |
|
|
generic map(
|
3880 |
|
|
INIT => X"00002000"
|
3881 |
|
|
)
|
3882 |
|
|
port map (
|
3883 |
|
|
I0 => wr_en,
|
3884 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3885 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3886 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3887 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3888 |
|
|
O => write_ctrl5_102
|
3889 |
|
|
);
|
3890 |
|
|
write_ctrl6 : LUT5
|
3891 |
|
|
generic map(
|
3892 |
|
|
INIT => X"00002000"
|
3893 |
|
|
)
|
3894 |
|
|
port map (
|
3895 |
|
|
I0 => wr_en,
|
3896 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3897 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3898 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3899 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3900 |
|
|
O => write_ctrl6_103
|
3901 |
|
|
);
|
3902 |
|
|
write_ctrl7 : LUT5
|
3903 |
|
|
generic map(
|
3904 |
|
|
INIT => X"00008000"
|
3905 |
|
|
)
|
3906 |
|
|
port map (
|
3907 |
|
|
I0 => wr_en,
|
3908 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(7),
|
3909 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(8),
|
3910 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(9),
|
3911 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
3912 |
|
|
O => write_ctrl7_104
|
3913 |
|
|
);
|
3914 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_6_Q :
|
3915 |
|
|
LUT2
|
3916 |
|
|
generic map(
|
3917 |
|
|
INIT => X"9"
|
3918 |
|
|
)
|
3919 |
|
|
port map (
|
3920 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(5),
|
3921 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
3922 |
|
|
O =>
|
3923 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_6_Q_169
|
3924 |
|
|
|
3925 |
|
|
);
|
3926 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_6_Q :
|
3927 |
|
|
LUT2
|
3928 |
|
|
generic map(
|
3929 |
|
|
INIT => X"9"
|
3930 |
|
|
)
|
3931 |
|
|
port map (
|
3932 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(5),
|
3933 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(5),
|
3934 |
|
|
O =>
|
3935 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_6_Q_223
|
3936 |
|
|
|
3937 |
|
|
);
|
3938 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_7_Q :
|
3939 |
|
|
LUT2
|
3940 |
|
|
generic map(
|
3941 |
|
|
INIT => X"9"
|
3942 |
|
|
)
|
3943 |
|
|
port map (
|
3944 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(6),
|
3945 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
3946 |
|
|
O =>
|
3947 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_7_Q_167
|
3948 |
|
|
|
3949 |
|
|
);
|
3950 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_7_Q :
|
3951 |
|
|
LUT2
|
3952 |
|
|
generic map(
|
3953 |
|
|
INIT => X"9"
|
3954 |
|
|
)
|
3955 |
|
|
port map (
|
3956 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(6),
|
3957 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(6),
|
3958 |
|
|
O =>
|
3959 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_7_Q_221
|
3960 |
|
|
|
3961 |
|
|
);
|
3962 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_8_Q :
|
3963 |
|
|
LUT2
|
3964 |
|
|
generic map(
|
3965 |
|
|
INIT => X"9"
|
3966 |
|
|
)
|
3967 |
|
|
port map (
|
3968 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(7),
|
3969 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
3970 |
|
|
O =>
|
3971 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_8_Q_165
|
3972 |
|
|
|
3973 |
|
|
);
|
3974 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_8_Q :
|
3975 |
|
|
LUT2
|
3976 |
|
|
generic map(
|
3977 |
|
|
INIT => X"9"
|
3978 |
|
|
)
|
3979 |
|
|
port map (
|
3980 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(7),
|
3981 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(7),
|
3982 |
|
|
O =>
|
3983 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_8_Q_219
|
3984 |
|
|
|
3985 |
|
|
);
|
3986 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_9_Q :
|
3987 |
|
|
LUT2
|
3988 |
|
|
generic map(
|
3989 |
|
|
INIT => X"9"
|
3990 |
|
|
)
|
3991 |
|
|
port map (
|
3992 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(8),
|
3993 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
3994 |
|
|
O =>
|
3995 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_9_Q_163
|
3996 |
|
|
|
3997 |
|
|
);
|
3998 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_9_Q :
|
3999 |
|
|
LUT2
|
4000 |
|
|
generic map(
|
4001 |
|
|
INIT => X"9"
|
4002 |
|
|
)
|
4003 |
|
|
port map (
|
4004 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(8),
|
4005 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(8),
|
4006 |
|
|
O =>
|
4007 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_9_Q_217
|
4008 |
|
|
|
4009 |
|
|
);
|
4010 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_10_Q :
|
4011 |
|
|
LUT2
|
4012 |
|
|
generic map(
|
4013 |
|
|
INIT => X"9"
|
4014 |
|
|
)
|
4015 |
|
|
port map (
|
4016 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_wr_pntr_bin(9),
|
4017 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
4018 |
|
|
O =>
|
4019 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_Madd_adjusted_wr_pntr_rd_pad_10_rd_pntr_inv_pad_10_add_3_OUT_lut_10_Q_161
|
4020 |
|
|
|
4021 |
|
|
);
|
4022 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_10_Q :
|
4023 |
|
|
LUT2
|
4024 |
|
|
generic map(
|
4025 |
|
|
INIT => X"9"
|
4026 |
|
|
)
|
4027 |
|
|
port map (
|
4028 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(9),
|
4029 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_rd_pntr_bin(9),
|
4030 |
|
|
O =>
|
4031 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_adjusted_rd_pntr_wr_inv_pad_10_add_3_OUT_lut_10_Q_215
|
4032 |
|
|
|
4033 |
|
|
);
|
4034 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_0_WR_PNTR_1_XOR_9_o_xo_0_1 : LUT2
|
4035 |
|
|
generic map(
|
4036 |
|
|
INIT => X"6"
|
4037 |
|
|
)
|
4038 |
|
|
port map (
|
4039 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4040 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4041 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_0_WR_PNTR_1_XOR_9_o
|
4042 |
|
|
);
|
4043 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT61 : LUT6
|
4044 |
|
|
generic map(
|
4045 |
|
|
INIT => X"CCCCCCCC6CCCCCCC"
|
4046 |
|
|
)
|
4047 |
|
|
port map (
|
4048 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
4049 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
4050 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
4051 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
4052 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
4053 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4054 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_5_Q
|
4055 |
|
|
);
|
4056 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT42 : LUT4
|
4057 |
|
|
generic map(
|
4058 |
|
|
INIT => X"AA6A"
|
4059 |
|
|
)
|
4060 |
|
|
port map (
|
4061 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
4062 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
4063 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
4064 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4065 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_3_Q
|
4066 |
|
|
);
|
4067 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT51 : LUT5
|
4068 |
|
|
generic map(
|
4069 |
|
|
INIT => X"AAAA6AAA"
|
4070 |
|
|
)
|
4071 |
|
|
port map (
|
4072 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
4073 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
4074 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
4075 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
4076 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4077 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_4_Q
|
4078 |
|
|
);
|
4079 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT21 : LUT2
|
4080 |
|
|
generic map(
|
4081 |
|
|
INIT => X"9"
|
4082 |
|
|
)
|
4083 |
|
|
port map (
|
4084 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4085 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
4086 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_1_Q
|
4087 |
|
|
);
|
4088 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT31 : LUT3
|
4089 |
|
|
generic map(
|
4090 |
|
|
INIT => X"A6"
|
4091 |
|
|
)
|
4092 |
|
|
port map (
|
4093 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
4094 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
4095 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4096 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_2_Q
|
4097 |
|
|
);
|
4098 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gic0_gc0_count_9_GND_36_o_mux_2_OUT31 : LUT3
|
4099 |
|
|
generic map(
|
4100 |
|
|
INIT => X"A6"
|
4101 |
|
|
)
|
4102 |
|
|
port map (
|
4103 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4104 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4105 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4106 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_2_Q
|
4107 |
|
|
);
|
4108 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gic0_gc0_count_9_GND_36_o_mux_2_OUT21 : LUT2
|
4109 |
|
|
generic map(
|
4110 |
|
|
INIT => X"9"
|
4111 |
|
|
)
|
4112 |
|
|
port map (
|
4113 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4114 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4115 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_1_Q
|
4116 |
|
|
);
|
4117 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_Mxor_WR_PNTR_1_WR_PNTR_2_XOR_8_o_xo_0_1 : LUT2
|
4118 |
|
|
generic map(
|
4119 |
|
|
INIT => X"9"
|
4120 |
|
|
)
|
4121 |
|
|
port map (
|
4122 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4123 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d2(2),
|
4124 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gcx_clkx_WR_PNTR_1_WR_PNTR_2_XOR_8_o
|
4125 |
|
|
);
|
4126 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i_rstpot_SW1 : LUT5
|
4127 |
|
|
generic map(
|
4128 |
|
|
INIT => X"80000000"
|
4129 |
|
|
)
|
4130 |
|
|
port map (
|
4131 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(5),
|
4132 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(6),
|
4133 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(7),
|
4134 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(8),
|
4135 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(9),
|
4136 |
|
|
O => N28
|
4137 |
|
|
);
|
4138 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i_rstpot : LUT6
|
4139 |
|
|
generic map(
|
4140 |
|
|
INIT => X"5444444410000000"
|
4141 |
|
|
)
|
4142 |
|
|
port map (
|
4143 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_49,
|
4144 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_wsts_ram_full_fb_i_93,
|
4145 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(10),
|
4146 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_diff_pntr_pad(4),
|
4147 |
|
|
I4 => N28,
|
4148 |
|
|
I5 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i,
|
4149 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwas_gpf_wrpf_prog_full_i_rstpot_366
|
4150 |
|
|
);
|
4151 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_11 : LUT3
|
4152 |
|
|
generic map(
|
4153 |
|
|
INIT => X"DF"
|
4154 |
|
|
)
|
4155 |
|
|
port map (
|
4156 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4157 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4158 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4159 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_bdd0
|
4160 |
|
|
);
|
4161 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_2 : LUT4
|
4162 |
|
|
generic map(
|
4163 |
|
|
INIT => X"AA6A"
|
4164 |
|
|
)
|
4165 |
|
|
port map (
|
4166 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
4167 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4168 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4169 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4170 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_3_Q
|
4171 |
|
|
);
|
4172 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_4_1 : LUT5
|
4173 |
|
|
generic map(
|
4174 |
|
|
INIT => X"AAAA6AAA"
|
4175 |
|
|
)
|
4176 |
|
|
port map (
|
4177 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
4178 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4179 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
4180 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4181 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4182 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_4_Q
|
4183 |
|
|
);
|
4184 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_5_1 : LUT6
|
4185 |
|
|
generic map(
|
4186 |
|
|
INIT => X"CCCCCCCC6CCCCCCC"
|
4187 |
|
|
)
|
4188 |
|
|
port map (
|
4189 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4190 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
4191 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
4192 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
4193 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4194 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4195 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_5_Q
|
4196 |
|
|
);
|
4197 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_9_SW1 : LUT5
|
4198 |
|
|
generic map(
|
4199 |
|
|
INIT => X"FFFF7FFF"
|
4200 |
|
|
)
|
4201 |
|
|
port map (
|
4202 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
4203 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
4204 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
4205 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4206 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4207 |
|
|
O => N30
|
4208 |
|
|
);
|
4209 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_9_Q : LUT6
|
4210 |
|
|
generic map(
|
4211 |
|
|
INIT => X"CCCCCCCC6CCCCCCC"
|
4212 |
|
|
)
|
4213 |
|
|
port map (
|
4214 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
4215 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(9),
|
4216 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7),
|
4217 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(8),
|
4218 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4219 |
|
|
I5 => N30,
|
4220 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_9_Q_258
|
4221 |
|
|
);
|
4222 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_8_SW1 : LUT4
|
4223 |
|
|
generic map(
|
4224 |
|
|
INIT => X"0080"
|
4225 |
|
|
)
|
4226 |
|
|
port map (
|
4227 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(5),
|
4228 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(6),
|
4229 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(7),
|
4230 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4231 |
|
|
O => N32
|
4232 |
|
|
);
|
4233 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_8_Q : LUT6
|
4234 |
|
|
generic map(
|
4235 |
|
|
INIT => X"6AAAAAAAAAAAAAAA"
|
4236 |
|
|
)
|
4237 |
|
|
port map (
|
4238 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(8),
|
4239 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4240 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(2),
|
4241 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(3),
|
4242 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(4),
|
4243 |
|
|
I5 => N32,
|
4244 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_9_GND_36_o_mux_2_OUT_8_Q_257
|
4245 |
|
|
);
|
4246 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT91_F : LUT6
|
4247 |
|
|
generic map(
|
4248 |
|
|
INIT => X"6AAAAAAAAAAAAAAA"
|
4249 |
|
|
)
|
4250 |
|
|
port map (
|
4251 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
4252 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
4253 |
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
4254 |
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
4255 |
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
4256 |
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
4257 |
|
|
O => N34
|
4258 |
|
|
);
|
4259 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_rd_pntr_inv_pad_10_1_0_1_INV_0 : INV
|
4260 |
|
|
port map (
|
4261 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
|
4262 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_gras_gpe_rdpe_rd_pntr_inv_pad(1)
|
4263 |
|
|
);
|
4264 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv1_INV_0 : INV
|
4265 |
|
|
port map (
|
4266 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count_d1(0),
|
4267 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1_0_inv
|
4268 |
|
|
);
|
4269 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv1_INV_0 : INV
|
4270 |
|
|
port map (
|
4271 |
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gic0_gc0_count(1),
|
4272 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus2_1_inv
|
4273 |
|
|
);
|
4274 |
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT911 : LUT3
|
4275 |
|
|
generic map(
|
4276 |
|
|
INIT => X"D8"
|
4277 |
|
|
)
|
4278 |
|
|
port map (
|
4279 |
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_22_o_mux_2_OUT41,
|
4280 |
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
4281 |
|
|
I2 => N34,
|
4282 |
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_22_o_mux_2_OUT_8_Q
|
4283 |
|
|
);
|
4284 |
|
|
|
4285 |
|
|
end STRUCTURE;
|
4286 |
|
|
|
4287 |
|
|
-- synthesis translate_on
|