Subversion Repositories pcie_sg_dma

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set device xc6vlx240tff1156-1

set projName v6_pkt_counter_1024

set design v6_pkt_counter_1024

set projDir [file dirname [info script]]

create_project $projName $projDir/results/$projName -part $device -force

set_property design_mode RTL [current_fileset -srcset]

set top_module v6_pkt_counter_1024_top

add_files -norecurse {../../example_design/v6_pkt_counter_1024_top.vhd}

add_files -norecurse {./v6_pkt_counter_1024.edf}

import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/v6_pkt_counter_1024_top.xdc}

set_property top v6_pkt_counter_1024_top [get_property srcset [current_run]]

synth_design

opt_design

place_design

route_design

set_param sta.dlyMediator true

write_sdf -rename_top_module v6_pkt_counter_1024_top -file routed.sdf

write_verilog -mode sim -sdf_anno false -rename_top_module v6_pkt_counter_1024_top routed.vhd

report_timing -nworst 30 -path_type full -file routed.twr

report_drc -file routed.drc