OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_prime_fifo_plain.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 barabba 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: O.76xd
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: v6_prime_fifo_plain.vhd
10 
-- /___/   /\     Timestamp: Mon Mar 26 16:03:44 2012
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -w -sim -ofmt vhdl "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_prime_fifo_plain.ngc" "C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_prime_fifo_plain.vhd"
15 
-- Device       : 6vlx240tff1156-1
16 
-- Input file   : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_prime_fifo_plain.ngc
17 
-- Output file  : C:/Temp/Xilinx PCI Express/ML605_ISE13.3/ipcore_dir_ISE13.3/tmp/_cg/v6_prime_fifo_plain.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : v6_prime_fifo_plain
20 
-- Xilinx       : C:\Programmi\Xilinx\13.3\ISE_DS\ISE\
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Command Line Tools User Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity v6_prime_fifo_plain is
44 
  port (
45 
    rst : in STD_LOGIC := 'X';
46 
    wr_clk : in STD_LOGIC := 'X';
47 
    rd_clk : in STD_LOGIC := 'X';
48 
    wr_en : in STD_LOGIC := 'X';
49 
    rd_en : in STD_LOGIC := 'X';
50 
    full : out STD_LOGIC;
51 
    empty : out STD_LOGIC;
52 
    prog_full : out STD_LOGIC;
53 
    din : in STD_LOGIC_VECTOR ( 71 downto 0 );
54 
    dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
55 
  );
56 
end v6_prime_fifo_plain;
57 
 
58 
architecture STRUCTURE of v6_prime_fifo_plain is
59 
  signal N1 : STD_LOGIC;
60 
  signal NlwRenamedSig_OI_empty : STD_LOGIC;
61 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_154 : STD_LOGIC;
62 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
63 
  signal N2 : STD_LOGIC;
64 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163 : STD_LOGIC;
65 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
66 
 
67 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
68 
 
69 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
70 
 
71 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
72 
 
73 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
74 
 
75 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
76 
 
77 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
78 
 
79 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
80 
 
81 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
82 
 
83 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
84 
 
85 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
86 
 
87 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
88 
 
89 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
90 
 
91 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
92 
 
93 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
94 
 
95 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
96 
 
97 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
98 
 
99 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
100 
 
101 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
102 
 
103 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
104 
 
105 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
106 
 
107 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
108 
 
109 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
110 
 
111 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
112 
 
113 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
114 
 
115 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
116 
 
117 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
118 
 
119 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
120 
 
121 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
122 
 
123 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
124 
 
125 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
126 
 
127 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
128 
 
129 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
130 
 
131 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
132 
 
133 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
134 
 
135 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
136 
 
137 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
138 
 
139 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
140 
 
141 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
142 
 
143 
  signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED : STD_LOGIC;
144 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
145 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst : STD_LOGIC_VECTOR ( 0 downto 0 );
146 
  signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
147 
begin
148 
  empty <= NlwRenamedSig_OI_empty;
149 
  XST_GND : GND
150 
    port map (
151 
      G => N1
152 
    );
153 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_4 : FD
154 
    generic map(
155 
      INIT => '0'
156 
    )
157 
    port map (
158 
      C => wr_clk,
159 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_154,
160 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(4)
161 
    );
162 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_3 : FD
163 
    generic map(
164 
      INIT => '0'
165 
    )
166 
    port map (
167 
      C => wr_clk,
168 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(4),
169 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(3)
170 
    );
171 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_2 : FD
172 
    generic map(
173 
      INIT => '0'
174 
    )
175 
    port map (
176 
      C => wr_clk,
177 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(3),
178 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(2)
179 
    );
180 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_1 : FD
181 
    generic map(
182 
      INIT => '0'
183 
    )
184 
    port map (
185 
      C => wr_clk,
186 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(2),
187 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(1)
188 
    );
189 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb_0 : FD
190 
    generic map(
191 
      INIT => '0'
192 
    )
193 
    port map (
194 
      C => wr_clk,
195 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(1),
196 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(0)
197 
    );
198 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg : FDPE
199 
    generic map(
200 
      INIT => '0'
201 
    )
202 
    port map (
203 
      C => wr_clk,
204 
      CE => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_fb(0),
205 
      D => N1,
206 
      PRE => rst,
207 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_154
208 
    );
209 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
210 
    generic map(
211 
      ALMOST_EMPTY_OFFSET => X"0005",
212 
      ALMOST_FULL_OFFSET => X"0011",
213 
      DATA_WIDTH => 72,
214 
      DO_REG => 1,
215 
      EN_ECC_READ => FALSE,
216 
      EN_ECC_WRITE => FALSE,
217 
      EN_SYN => FALSE,
218 
      FIFO_MODE => "FIFO36_72",
219 
      FIRST_WORD_FALL_THROUGH => FALSE,
220 
      INIT => X"000000000000000000",
221 
      SIM_DEVICE => "VIRTEX6",
222 
      SRVAL => X"000000000000000000"
223 
    )
224 
    port map (
225 
      ALMOSTEMPTY =>
226 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
227 
,
228 
      ALMOSTFULL => prog_full,
229 
      DBITERR =>
230 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
231 
      EMPTY => NlwRenamedSig_OI_empty,
232 
      FULL => full,
233 
      INJECTDBITERR => N1,
234 
      INJECTSBITERR => N1,
235 
      RDCLK => rd_clk,
236 
      RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
237 
      RDERR =>
238 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
239 
      REGCE => N1,
240 
      RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
241 
      RSTREG => N1,
242 
      SBITERR =>
243 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
244 
      WRCLK => wr_clk,
245 
      WREN => wr_en,
246 
      WRERR =>
247 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
248 
      DI(63) => din(67),
249 
      DI(62) => din(66),
250 
      DI(61) => din(65),
251 
      DI(60) => din(64),
252 
      DI(59) => din(63),
253 
      DI(58) => din(62),
254 
      DI(57) => din(61),
255 
      DI(56) => din(60),
256 
      DI(55) => din(59),
257 
      DI(54) => din(58),
258 
      DI(53) => din(57),
259 
      DI(52) => din(56),
260 
      DI(51) => din(55),
261 
      DI(50) => din(54),
262 
      DI(49) => din(53),
263 
      DI(48) => din(52),
264 
      DI(47) => din(51),
265 
      DI(46) => din(50),
266 
      DI(45) => din(49),
267 
      DI(44) => din(48),
268 
      DI(43) => din(47),
269 
      DI(42) => din(46),
270 
      DI(41) => din(45),
271 
      DI(40) => din(44),
272 
      DI(39) => din(43),
273 
      DI(38) => din(42),
274 
      DI(37) => din(41),
275 
      DI(36) => din(40),
276 
      DI(35) => din(39),
277 
      DI(34) => din(38),
278 
      DI(33) => din(37),
279 
      DI(32) => din(36),
280 
      DI(31) => din(31),
281 
      DI(30) => din(30),
282 
      DI(29) => din(29),
283 
      DI(28) => din(28),
284 
      DI(27) => din(27),
285 
      DI(26) => din(26),
286 
      DI(25) => din(25),
287 
      DI(24) => din(24),
288 
      DI(23) => din(23),
289 
      DI(22) => din(22),
290 
      DI(21) => din(21),
291 
      DI(20) => din(20),
292 
      DI(19) => din(19),
293 
      DI(18) => din(18),
294 
      DI(17) => din(17),
295 
      DI(16) => din(16),
296 
      DI(15) => din(15),
297 
      DI(14) => din(14),
298 
      DI(13) => din(13),
299 
      DI(12) => din(12),
300 
      DI(11) => din(11),
301 
      DI(10) => din(10),
302 
      DI(9) => din(9),
303 
      DI(8) => din(8),
304 
      DI(7) => din(7),
305 
      DI(6) => din(6),
306 
      DI(5) => din(5),
307 
      DI(4) => din(4),
308 
      DI(3) => din(3),
309 
      DI(2) => din(2),
310 
      DI(1) => din(1),
311 
      DI(0) => din(0),
312 
      DIP(7) => din(71),
313 
      DIP(6) => din(70),
314 
      DIP(5) => din(69),
315 
      DIP(4) => din(68),
316 
      DIP(3) => din(35),
317 
      DIP(2) => din(34),
318 
      DIP(1) => din(33),
319 
      DIP(0) => din(32),
320 
      DO(63) => dout(67),
321 
      DO(62) => dout(66),
322 
      DO(61) => dout(65),
323 
      DO(60) => dout(64),
324 
      DO(59) => dout(63),
325 
      DO(58) => dout(62),
326 
      DO(57) => dout(61),
327 
      DO(56) => dout(60),
328 
      DO(55) => dout(59),
329 
      DO(54) => dout(58),
330 
      DO(53) => dout(57),
331 
      DO(52) => dout(56),
332 
      DO(51) => dout(55),
333 
      DO(50) => dout(54),
334 
      DO(49) => dout(53),
335 
      DO(48) => dout(52),
336 
      DO(47) => dout(51),
337 
      DO(46) => dout(50),
338 
      DO(45) => dout(49),
339 
      DO(44) => dout(48),
340 
      DO(43) => dout(47),
341 
      DO(42) => dout(46),
342 
      DO(41) => dout(45),
343 
      DO(40) => dout(44),
344 
      DO(39) => dout(43),
345 
      DO(38) => dout(42),
346 
      DO(37) => dout(41),
347 
      DO(36) => dout(40),
348 
      DO(35) => dout(39),
349 
      DO(34) => dout(38),
350 
      DO(33) => dout(37),
351 
      DO(32) => dout(36),
352 
      DO(31) => dout(31),
353 
      DO(30) => dout(30),
354 
      DO(29) => dout(29),
355 
      DO(28) => dout(28),
356 
      DO(27) => dout(27),
357 
      DO(26) => dout(26),
358 
      DO(25) => dout(25),
359 
      DO(24) => dout(24),
360 
      DO(23) => dout(23),
361 
      DO(22) => dout(22),
362 
      DO(21) => dout(21),
363 
      DO(20) => dout(20),
364 
      DO(19) => dout(19),
365 
      DO(18) => dout(18),
366 
      DO(17) => dout(17),
367 
      DO(16) => dout(16),
368 
      DO(15) => dout(15),
369 
      DO(14) => dout(14),
370 
      DO(13) => dout(13),
371 
      DO(12) => dout(12),
372 
      DO(11) => dout(11),
373 
      DO(10) => dout(10),
374 
      DO(9) => dout(9),
375 
      DO(8) => dout(8),
376 
      DO(7) => dout(7),
377 
      DO(6) => dout(6),
378 
      DO(5) => dout(5),
379 
      DO(4) => dout(4),
380 
      DO(3) => dout(3),
381 
      DO(2) => dout(2),
382 
      DO(1) => dout(1),
383 
      DO(0) => dout(0),
384 
      DOP(7) => dout(71),
385 
      DOP(6) => dout(70),
386 
      DOP(5) => dout(69),
387 
      DOP(4) => dout(68),
388 
      DOP(3) => dout(35),
389 
      DOP(2) => dout(34),
390 
      DOP(1) => dout(33),
391 
      DOP(0) => dout(32),
392 
      ECCPARITY(7) =>
393 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
394 
,
395 
      ECCPARITY(6) =>
396 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
397 
,
398 
      ECCPARITY(5) =>
399 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
400 
,
401 
      ECCPARITY(4) =>
402 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
403 
,
404 
      ECCPARITY(3) =>
405 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
406 
,
407 
      ECCPARITY(2) =>
408 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
409 
,
410 
      ECCPARITY(1) =>
411 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
412 
,
413 
      ECCPARITY(0) =>
414 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
415 
,
416 
      RDCOUNT(12) =>
417 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
418 
,
419 
      RDCOUNT(11) =>
420 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
421 
,
422 
      RDCOUNT(10) =>
423 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
424 
,
425 
      RDCOUNT(9) =>
426 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
427 
,
428 
      RDCOUNT(8) =>
429 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
430 
,
431 
      RDCOUNT(7) =>
432 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
433 
,
434 
      RDCOUNT(6) =>
435 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
436 
,
437 
      RDCOUNT(5) =>
438 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
439 
,
440 
      RDCOUNT(4) =>
441 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
442 
,
443 
      RDCOUNT(3) =>
444 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
445 
,
446 
      RDCOUNT(2) =>
447 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
448 
,
449 
      RDCOUNT(1) =>
450 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
451 
,
452 
      RDCOUNT(0) =>
453 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
454 
,
455 
      WRCOUNT(12) =>
456 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
457 
,
458 
      WRCOUNT(11) =>
459 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
460 
,
461 
      WRCOUNT(10) =>
462 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
463 
,
464 
      WRCOUNT(9) =>
465 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
466 
,
467 
      WRCOUNT(8) =>
468 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
469 
,
470 
      WRCOUNT(7) =>
471 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
472 
,
473 
      WRCOUNT(6) =>
474 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
475 
,
476 
      WRCOUNT(5) =>
477 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
478 
,
479 
      WRCOUNT(4) =>
480 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
481 
,
482 
      WRCOUNT(3) =>
483 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
484 
,
485 
      WRCOUNT(2) =>
486 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
487 
,
488 
      WRCOUNT(1) =>
489 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
490 
,
491 
      WRCOUNT(0) =>
492 
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
493 
    );
494 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_1 : LUT2
495 
    generic map(
496 
      INIT => X"E"
497 
    )
498 
    port map (
499 
      I0 => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_wr_rst_reg_154,
500 
      I1 => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst(0),
501 
      O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0)
502 
    );
503 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
504 
    generic map(
505 
      INIT => X"2"
506 
    )
507 
    port map (
508 
      I0 => rd_en,
509 
      I1 => NlwRenamedSig_OI_empty,
510 
      O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
511 
    );
512 
  XST_VCC : VCC
513 
    port map (
514 
      P => N2
515 
    );
516 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0 : SRLC16E
517 
    generic map(
518 
      INIT => X"001F"
519 
    )
520 
    port map (
521 
      A0 => N1,
522 
      A1 => N1,
523 
      A2 => N2,
524 
      A3 => N1,
525 
      CE => N2,
526 
      CLK => wr_clk,
527 
      D => N1,
528 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163,
529 
      Q15 => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED
530 
    );
531 
  U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst_0 : FDE
532 
    generic map(
533 
      INIT => '1'
534 
    )
535 
    port map (
536 
      C => wr_clk,
537 
      CE => N2,
538 
      D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_Mshreg_power_on_wr_rst_0_163,
539 
      Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_power_on_wr_rst(0)
540 
    );
541 
 
542 
end STRUCTURE;
543 
 
544 
-- synthesis translate_on

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.