Subversion Repositories pcie_sg_dma

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rem Clean up the results directory

rmdir /S /Q results

mkdir results

rem Synthesize the VHDL Wrapper Files

#Synthesize the Wrapper Files

echo 'Synthesizing example design with XST';

xst -ifn xst.scr

copy v6_sfifo_15x128_top.ngc .\results\

rem Copy the netlist generated by Coregen

echo 'Copying files from the netlist directory to the results directory'

copy ..\..\v6_sfifo_15x128.ngc results\

rem  Copy the constraints files generated by Coregen

echo 'Copying files from constraints directory to results directory'

copy ..\example_design\v6_sfifo_15x128_top.ucf results\

cd results

echo 'Running ngdbuild'

ngdbuild -p xc6vlx240t-ff1156-1 -sd ../../../ v6_sfifo_15x128_top

echo 'Running map'

map v6_sfifo_15x128_top -o mapped.ncd

echo 'Running par'

par mapped.ncd routed.ncd

echo 'Running trce'

trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'

bitgen -w routed

echo 'Running netgen to create gate level VHDL model'

netgen -ofmt vhdl -sim -tm v6_sfifo_15x128_top -pcf mapped.pcf -w routed.ncd routed.vhd