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guanucolui |
#--------------------------------------------------------------------------------
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# Author: Centro Universitario de Desarrollo en Automación y Robótica
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# Universidad Tecnológica Nacional - Facultad Regional Córdoba
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#
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# Project Name: Plataforma de Hardware Reconfigurable - PHR
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#
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# Create Date: 21:08:04 01/27/2015
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#
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# Description:
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# Este archivo UCF contiene las asignaciones de pines
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# de todos los puertos disponibles de la plataforma PHR.
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# Los nombres utilizados (NET "") corresponden
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# al proyecto Demo que se encuentra en el repositorio [1].
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# El archivo "phrboard.ucf" puede agregarse a su diseño,
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# cambiar los nombres de los puertos si es necesario. Y para
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# los puertos no utilizados en su arquitectura, comentar
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# las correspondientes líneas (por ejemplo los puertos GPIO).
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#
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# Dependencies:
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# Archivo UCF válido solo para la plataforma PHR-rev2.
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#
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# Revision:
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# Revision 0.01 - File Created
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# Additional Comments:
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# Los archivos UCF (siglas en inglés de User Constraints File),
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# permiten optimizar el proceso de síntesis para un particular
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# diseño. En los dispositivos Xilinx se identifican dos tipos de
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# "constrain"; los que se implementan en la síntesis y los
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# utilizados en la implementación (proceso posterior a la síntesis).
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# Para mayor información se puede leer el documento "Xilinx Constraints
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# Guide"[2].
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#
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# [1] http://opencores.org/project,phr
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# [2] http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf
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#
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# Entre los constrains utilizados en nuestro archivo UCF, tenemos:
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#
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# NET LOC = ; Permite
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# asignar al puerto definido en la entidad del diseño, a un
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# puerto físico del dispositivo utilizado.
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#
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# NET IOSTANDARD = LVCMOS33; Se define la
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# tecnología que se utilizará para un puerto específico. En este
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# caso, tecnología LVCMOS (3.3V).
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#
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# NET PULLUP; La mayoría de los dispositivos
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# tiene la posibilidad de configurar los puertos de salida con
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# resistencias internas conectadas en modo PULLUP, PULLDOWN, etc.
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# En este caso se utiliza solo para los puertos de entrada del
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# conector GPIO(pines 1,16). No se utiliza este modo para las demás
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# entradas pues ya se dispone de resistores externos.
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#
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# NET SLEW = SLOW; Para los puertos de salida
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# (o bidireccionales) se puede definir la característica de la
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# velocidad de subida. Las opciones son SLOW, FAST y QUIETIO.
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#
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#
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#--------------------------------------------------------------------------------
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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# ---------- Entradas ----------
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# -- Clock principal (50Mhz) --
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NET "clk50M" LOC = P43 | IOSTANDARD = LVCMOS33;
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# -- Clocks externos (desde CD4060) --
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NET "clksel1" LOC = P44 | IOSTANDARD = LVCMOS33;
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NET "clksel2" LOC = P41 | IOSTANDARD = LVCMOS33;
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NET "clksel3" LOC = P40 | IOSTANDARD = LVCMOS33;
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# -- Pulsadores --
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NET "btn[0]" LOC = P68 | IOSTANDARD = LVCMOS33;
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NET "btn[1]" LOC = P78 | IOSTANDARD = LVCMOS33;
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NET "btn[2]" LOC = P82 | IOSTANDARD = LVCMOS33;
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NET "btn[3]" LOC = P83 | IOSTANDARD = LVCMOS33;
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# -- Llaves (Switches) --
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NET "sw[0]" LOC = P85 | IOSTANDARD = LVCMOS33;
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NET "sw[1]" LOC = P88 | IOSTANDARD = LVCMOS33;
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NET "sw[2]" LOC = P90 | IOSTANDARD = LVCMOS33;
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NET "sw[3]" LOC = P94 | IOSTANDARD = LVCMOS33;
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NET "sw[4]" LOC = P97 | IOSTANDARD = LVCMOS33;
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NET "sw[5]" LOC = P4 | IOSTANDARD = LVCMOS33;
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NET "sw[6]" LOC = P6 | IOSTANDARD = LVCMOS33;
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NET "sw[7]" LOC = P7 | IOSTANDARD = LVCMOS33;
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# -- Solo-Entradas del puerto GPIO --
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NET "GPIO_INS[0]" LOC = P39 | PULLUP | IOSTANDARD = LVCMOS33;
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NET "GPIO_INS[1]" LOC = P21 | PULLUP | IOSTANDARD = LVCMOS33;
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# ---------- OUTPUTS ----------
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# -- Leds --
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NET "led[0]" LOC = P84 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[1]" LOC = P86 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[2]" LOC = P89 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[3]" LOC = P93 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[4]" LOC = P98 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[5]" LOC = P3 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[6]" LOC = P5 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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NET "led[7]" LOC = P9 | SLEW = SLOW | IOSTANDARD = LVCMOS33;
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# -- Transistores display 7-seg --
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NET "an[0]" LOC = P59 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "an[1]" LOC = P57 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "an[2]" LOC = P61 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "an[3]" LOC = P60 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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# -- Segmentos del display 4x7seg --
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NET "ssg[0]" LOC = P65 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[1]" LOC = P64 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[2]" LOC = P72 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[3]" LOC = P70 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[4]" LOC = P77 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[5]" LOC = P62 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[6]" LOC = P73 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "ssg[7]" LOC = P71 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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# -- Pines I/O (en modo Salidas) del puerto GPIO --
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NET "GPIO_OUTS[0]" LOC = P50 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[1]" LOC = P37 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[2]" LOC = P49 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[3]" LOC = P36 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[4]" LOC = P46 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[5]" LOC = P35 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[6]" LOC = P34 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[7]" LOC = P33 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[8]" LOC = P32 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[9]" LOC = P31 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[10]" LOC = P30 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[11]" LOC = P29 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[12]" LOC = P28 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[13]" LOC = P27 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[14]" LOC = P20 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[15]" LOC = P19 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[16]" LOC = P16 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[17]" LOC = P15 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[18]" LOC = P13 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[19]" LOC = P12 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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NET "GPIO_OUTS[20]" LOC = P10 | SLEW = FAST | IOSTANDARD = LVCMOS33;
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# -- Pines del puerto serie --
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NET "rxd" LOC = "P52" | IOSTANDARD = LVCMOS33;
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NET "txd" LOC = "P56" | IOSTANDARD = LVCMOS33;
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#PACE: End of Constraints generated by PACE
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