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-- --------------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------------
-- TITLE:       Plasma DATAPATH
-- AUTHOR:      Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
-- COMMENT:     This project is based on Plasma CPU core by Steve Rhoads
--
-- www.ies.tu-darmstadt.de
-- TU Darmstadt
-- Institute for Integrated Systems
-- Merckstr. 25
-- 
-- 64283 Darmstadt - GERMANY
-- --------------------------------------------------------------------------
-- PROJECT:       Plasma CPU core with FPU
-- FILENAME:      plasma_datapath.vhd
-- --------------------------------------------------------------------------
-- COPYRIGHT: 
--  This project is distributed by GPLv2.0
--  Software placed into the public domain by the author.
--  Software 'as is' without warranty.  Author liable for nothing.
-- --------------------------------------------------------------------------
-- DESCRIPTION:
--    datapath of plasma core
--
--    SYNTHESIZABLE
--
----------------------------------------------------------------------------
-- Revision History
-- --------------------------------------------------------------------------
-- Revision   Date    Author     CHANGES
-- 1.0      4/2014    AS         initial
-- 2.0     12/2014    AS         separated into MIPS1 simple architecture
--                               and with FPU included
-- 3.0     05/2015    AS         made generic port, included immediate mux
-- --------------------------------------------------------------------------
library IEEE;
  use IEEE.std_logic_1164.ALL;
 
library PLASMA;
  use PLASMA.mips_instruction_set.ALL;
  use PLASMA.plasma_pack.ALL;
 
 
entity plasma_datapath_MIPSI_FPU is
    generic(
      core_idx                : natural := 0;
      SIM_FLAG                : string  := "ON";
      DEBUG_FLAG              : string  := "OF"
      );
    port(
      control                 : in  t_main_control;
      -- input control mux and registers
      reg_addr                : in  t_reg_addr;
      fpu_reg_addr            : in  t_reg_addr;
      mux_ctrl                : in  t_plasma_mux_ctrl;
      mux_fpu                 : in  t_plasma_mux_fpu;
      stall_src               : in  t_stall_source;
      -- output feedback signals
      comp_out                : out std_logic;
      fpu_cc                  : out std_logic;
      unit_busy               : out t_unit_busy;
      -- operation units control
      unit_ctrl               : in  t_plasma_subunits_ctrl;
      fpu_ctrl                : in  t_fpu_ctrl;
      -- data
      instr_addr              : out t_plasma_word;
      data_addr               : out t_plasma_word;
 
      instr_in                : in  t_plasma_word;
      data_from_mem           : in  t_plasma_word;
      data_to_mem             : out t_plasma_word
    );
end entity plasma_datapath_MIPSI_FPU;
 
 
architecture structure_plasma_datapath_MIPSI_FPU of plasma_datapath_MIPSI_FPU is
 
  -- ___  ____ ____ ____ ____ ____ _  _    ____ ____ _  _ _  _ ___ ____ ____ 
  -- |__] |__/ |  | | __ |__/ |__| |\/|    |    |  | |  | |\ |  |  |___ |__/ 
  -- |    |  \ |__| |__] |  \ |  | |  |    |___ |__| |__| | \|  |  |___ |  \ 
  signal pc_new_value         : t_plasma_word;                            -- next pc value
  signal pc_out_inc           : t_plasma_word;                            -- pc + 4
  signal pc_out_branch        : t_plasma_word;                            -- pc + 4 + (imm16 << 2)
 
  -- ____ ____ ____ _ ____ ___ ____ ____          ___  ____ _  _ _  _ 
  -- |__/ |___ | __ | [__   |  |___ |__/          |__] |__| |\ | |_/  
  -- |  \ |___ |__] | ___]  |  |___ |  \          |__] |  | | \| | \_ 
  signal regular_rd           : t_mips_reg_addr;
  signal reg_bank_a           : t_plasma_word;                            -- rs
  signal reg_bank_b           : t_plasma_word;                            -- rt
 
  -- _ _  _ _  _    _  _ _  _ _  _ 
  -- | |\/| |\/|    |\/| |  |  \/  
  -- | |  | |  |    |  | |__| _/\_ 
  alias i_shamt               : t_mips_shamt    is instr_in(10 downto  6);
  alias i_imm                 : t_mips_imm16    is instr_in(15 downto  0);
  alias i_imm_long            : t_mips_imm26    is instr_in(25 downto  0);
 
  signal i_imm_sign           : t_mips_imm16;
  signal i_imm_branch         : std_logic_vector(31 downto 18);
 
  constant ZERO_SHAMT         : std_logic_vector(31 downto  5) := (others => '0');
  constant ZERO_IMM16         : std_logic_vector(15 downto  0) := (others => '0');
  constant ZERO_IMM26         : std_logic_vector(31 downto 28) := (others => '0');
 
  -- _ _  _ ___  _  _ ___    _  _ _  _ _  _ ____ ____ 
  -- | |\ | |__] |  |  |     |\/| |  |  \/  |___ [__  
  -- | | \| |    |__|  |     |  | |__| _/\_ |___ ___] 
  signal src_a_in             : t_plasma_word;
  signal i_src_b_in           : t_plasma_word;
  signal src_b_in             : t_plasma_word;
  signal imm_in               : t_plasma_word;
  signal mem_data_in          : t_plasma_word;
  signal data_from_fpu        : t_plasma_word;
 
  -- ____ _  _    ____ ___ ____ ____ ____    ____ ____ ____ ____ 
  -- |___  \/     [__   |  |__| | __ |___    |__/ |___ | __ [__  
  -- |___ _/\_    ___]  |  |  | |__] |___    |  \ |___ |__] ___] 
  signal reg_src_a_in         : t_plasma_word;
  signal reg_src_b_in         : t_plasma_word;
  signal reg_imm_in           : t_plasma_word;
  signal reg_mem_data_in      : t_plasma_word;
 
  -- ____ _  _ ___ ___  _  _ ___    _  _ _  _ _  _ 
  -- |  | |  |  |  |__] |  |  |     |\/| |  |  \/  
  -- |__| |__|  |  |    |__|  |     |  | |__| _/\_ 
  signal alu_out              : t_plasma_word;
  signal shift_out            : t_plasma_word;
  signal mult_out             : t_plasma_word;
 
  signal op_data_out          : t_plasma_word;
 
  -- _  _ ____ _  _    ____ ___ ____ ____ ____    ____ ____ ____ 
  -- |\/| |___ |\/|    [__   |  |__| | __ |___    |__/ |___ | __ 
  -- |  | |___ |  |    ___]  |  |  | |__] |___    |  \ |___ |__] 
  signal reg_mem_result       : t_plasma_word;
  signal reg_mem_to_memory    : t_plasma_word;
 
  signal mem_data_out         : t_plasma_word;
 
  -- _ _ _ ___     ____ ___ ____ ____ ____    ____ ____ ____ 
  -- | | | |__]    [__   |  |__| | __ |___    |__/ |___ | __ 
  -- |_|_| |__]    ___]  |  |  | |__] |___    |  \ |___ |__] 
  signal reg_bank_in          : t_plasma_word;
 
begin   ---------- BEGIN -------------------- BEGIN --------------------- BEGIN -------------------
  -- ----------------------------------------------------------------------------------------------
  --  _____  _____   ____   _____ _____            __  __      _____ ____  _    _ _   _ _______ ______ _____  
  -- |  __ \|  __ \ / __ \ / ____|  __ \     /\   |  \/  |    / ____/ __ \| |  | | \ | |__   __|  ____|  __ \ 
  -- | |__) | |__) | |  | | |  __| |__) |   /  \  | \  / |   | |   | |  | | |  | |  \| |  | |  | |__  | |__) |
  -- |  ___/|  _  /| |  | | | |_ |  _  /   / /\ \ | |\/| |   | |   | |  | | |  | | . ` |  | |  |  __| |  _  / 
  -- | |    | | \ \| |__| | |__| | | \ \  / ____ \| |  | |   | |___| |__| | |__| | |\  |  | |  | |____| | \ \ 
  -- |_|    |_|  \_\\____/ \_____|_|  \_\/_/    \_\_|  |_|    \_____\____/ \____/|_| \_|  |_|  |______|_|  \_\
  -- ----------------------------------------------------------------------------------------------                                                                                                         
  --
  -- PC UNIT
  --
  u1_pc: plasma_pc
    PORT MAP(
      control       => control,
      stall         => stall_src.pc,
      pc_imm_in     => reg_imm_in,
      pc_new_value  => pc_new_value,
      pc_out.pc_out_inc     => pc_out_inc,
      pc_out.pc_out_branch  => pc_out_branch,
      pc_out.pc_out         => instr_addr
    );
 
  -- ----------------------------------------------------------------------------------------------
  --  _____  ______ _____ _____  _____ _______ ______ _____      ____          _   _ _  __
  -- |  __ \|  ____/ ____|_   _|/ ____|__   __|  ____|  __ \    |  _ \   /\   | \ | | |/ /
  -- | |__) | |__ | |  __  | | | (___    | |  | |__  | |__) |   | |_) | /  \  |  \| | ' / 
  -- |  _  /|  __|| | |_ | | |  \___ \   | |  |  __| |  _  /    |  _ < / /\ \ | . ` |  <  
  -- | | \ \| |___| |__| |_| |_ ____) |  | |  | |____| | \ \    | |_) / ____ \| |\  | . \ 
  -- |_|  \_\______\_____|_____|_____/   |_|  |______|_|  \_\   |____/_/    \_\_| \_|_|\_\
  -- ----------------------------------------------------------------------------------------------
  --
  -- REGISTER BANK UNIT
  --
  u2_reg_bank: plasma_reg_bank
    GENERIC MAP(
      core_idx        => core_idx,
      DEBUG_FLAG      => DEBUG_FLAG
    )
    PORT MAP(
      control         => control,
      reg_addr        => reg_addr,
      reg_dest_new    => reg_bank_in,
      reg_source_out  => reg_bank_a,
      reg_target_out  => reg_bank_b
    );
 
  -- ----------------------------------------------------------------------------------------------
  -- ----------------------------------------------------------------------------------------------
  -- ######  #######  #####  ####### ######  #######     #####  #######    #     #####  ####### 
  -- #     # #       #     # #     # #     # #          #     #    #      # #   #     # #       
  -- #     # #       #       #     # #     # #          #          #     #   #  #       #       
  -- #     # #####   #       #     # #     # #####       #####     #    #     # #  #### #####   
  -- #     # #       #       #     # #     # #                #    #    ####### #     # #       
  -- #     # #       #     # #     # #     # #          #     #    #    #     # #     # #       
  -- ######  #######  #####  ####### ######  #######     #####     #    #     #  #####  ####### 
  -- ----------------------------------------------------------------------------------------------
 
  -- ----------------------------------------------------------------------------------------------
  --  _____ _   _ _____  _    _ _______     __  __ _    ___   ________  _____ 
  -- |_   _| \ | |  __ \| |  | |__   __|   |  \/  | |  | \ \ / /  ____|/ ____|
  --   | | |  \| | |__) | |  | |  | |      | \  / | |  | |\ V /| |__  | (___  
  --   | | | . ` |  ___/| |  | |  | |      | |\/| | |  | | > < |  __|  \___ \ 
  --  _| |_| |\  | |    | |__| |  | |      | |  | | |__| |/ . \| |____ ____) |
  -- |_____|_| \_|_|     \____/   |_|      |_|  |_|\____//_/ \_\______|_____/ 
  -- ----------------------------------------------------------------------------------------------
  --
  -- IMMEDIATE VALUE MUX
  --
  i_imm_sign        <= (others => i_imm(15));
  i_imm_branch      <= (others => i_imm(15));
 
 
  with mux_ctrl.src_imm select
    imm_in          <=  ZERO_IMM16   & i_imm                when IMM_UNSIGN,
                        i_imm & ZERO_IMM16                  when IMM_HIGH,
                        ZERO_SHAMT   & i_shamt              when IMM_SHAMT,
                        i_imm_branch & i_imm      & b"00"   when IMM_BRANCH,
                        ZERO_IMM26   & i_imm_long & b"00"   when IMM_JUMP,
                        i_imm_sign   & i_imm                when others;
 
  --
  -- SOURCE A MUX
  -- 
  with mux_ctrl.src_a select
    src_a_in        <=  op_data_out       when SRC_OP_OUT,
                        mem_data_out      when SRC_MEM_OUT,
                        reg_bank_in       when SRC_WB_OUT,
                        reg_bank_a        when others;
 
  --
  -- SOURCE B MUX
  --             
  with mux_ctrl.src_b select
    i_src_b_in      <=  op_data_out       when SRC_OP_OUT,
                        mem_data_out      when SRC_MEM_OUT,
                        reg_bank_in       when SRC_WB_OUT,
                        reg_bank_b        when others;
 
  --
  -- IMMEDIATE SWITCH
  --
  with mux_ctrl.src_b_imm select
    src_b_in        <= imm_in             when B_IMM_ON,
                       i_src_b_in         when others;
 
  --
  -- MEMORY INPUT
  --
  with mux_fpu.cop select
    mem_data_in     <=  data_from_fpu     when COP_SELECT_COP1,
                        i_src_b_in        when others;
 
  -- ----------------------------------------------------------------------------------------------
  -- ----------------------------------------------------------------------------------------------
  -- ####### #     # #######  #####  #     # ####### #######     #####  #######    #     #####  ####### 
  -- #        #   #  #       #     # #     #    #    #          #     #    #      # #   #     # #       
  -- #         # #   #       #       #     #    #    #          #          #     #   #  #       #       
  -- #####      #    #####   #       #     #    #    #####       #####     #    #     # #  #### #####   
  -- #         # #   #       #       #     #    #    #                #    #    ####### #     # #       
  -- #        #   #  #       #     # #     #    #    #          #     #    #    #     # #     # #       
  -- ####### #     # #######  #####   #####     #    #######     #####     #    #     #  #####  ####### 
  -- ----------------------------------------------------------------------------------------------
 
  -- ----------------------------------------------------------------------------------------------
  --  ________   __    _____ _______       _____ ______    _____  ______ _____  _____ 
  -- |  ____\ \ / /   / ____|__   __|/\   / ____|  ____|  |  __ \|  ____/ ____|/ ____|
  -- | |__   \ V /   | (___    | |  /  \ | |  __| |__     | |__) | |__ | |  __| (___  
  -- |  __|   > <     \___ \   | | / /\ \| | |_ |  __|    |  _  /|  __|| | |_ |\___ \ 
  -- | |____ / . \    ____) |  | |/ ____ \ |__| | |____   | | \ \| |___| |__| |____) |
  -- |______/_/ \_\  |_____/   |_/_/    \_\_____|______|  |_|  \_\______\_____|_____/ 
  -- ----------------------------------------------------------------------------------------------
ex_stage_registers:
  process( control.clk )
  begin
    if rising_edge( control.clk ) then
      if control.rst = '1' then
        reg_src_a_in      <= PLASMA_ZERO_WORD;
        reg_src_b_in      <= PLASMA_ZERO_WORD;
        reg_imm_in        <= PLASMA_ZERO_WORD;
 
        reg_mem_data_in   <= PLASMA_ZERO_WORD;
      else
        if stall_src.pc = '0' then
          reg_src_a_in    <= src_a_in;
          reg_src_b_in    <= src_b_in;
          reg_imm_in      <= imm_in;
 
          reg_mem_data_in <= mem_data_in;
        end if;
      end if;
    end if;
  end process;
 
  -- ----------------------------------------------------------------------------------------------
  --   ____  _____  ______ _____         _______ _____ ____  _   _     _    _ _   _ _____ _______ _____ 
  --  / __ \|  __ \|  ____|  __ \     /\|__   __|_   _/ __ \| \ | |   | |  | | \ | |_   _|__   __/ ____|
  -- | |  | | |__) | |__  | |__) |   /  \  | |    | || |  | |  \| |   | |  | |  \| | | |    | | | (___  
  -- | |  | |  ___/|  __| |  _  /   / /\ \ | |    | || |  | | . ` |   | |  | | . ` | | |    | |  \___ \ 
  -- | |__| | |    | |____| | \ \  / ____ \| |   _| || |__| | |\  |   | |__| | |\  |_| |_   | |  ____) |
  --  \____/|_|    |______|_|  \_\/_/    \_\_|  |_____\____/|_| \_|    \____/|_| \_|_____|  |_| |_____/ 
  -- ----------------------------------------------------------------------------------------------
  -- ____ _ _  _ _  _ _    ____ ___ _ ____ _  _ 
  -- [__  | |\/| |  | |    |__|  |  | |  | |\ | 
  -- ___] | |  | |__| |___ |  |  |  | |__| | \| 
--synthesis translate_off
  SIM: if SIM_FLAG = "ON" generate
  --
  -- ALU
  --
  u3_alu: entity PLASMA.plasma_alu(sim_alu)
    PORT MAP(
      alu_a_in      => reg_src_a_in,        alu_b_in      => reg_src_b_in,
      alu_func      => unit_ctrl.alu_func,
      alu_out       => alu_out
    );
 
  --
  -- SHIFTER
  --
  u4_shifter: entity PLASMA.plasma_shifter(sim_shifter)
    PORT MAP(
      shift_in      => reg_src_a_in,          shift_amount  => reg_src_b_in(4 downto 0),
      shift_func    => unit_ctrl.shift_func,
      shift_out     => shift_out
    );
 
  --
  -- MULTIPLICATOR
  --
  u5_mult: entity PLASMA.plasma_mult(sim_mult)
    PORT MAP(
      control       => control,
      mult_a_in     => reg_src_a_in,        mult_b_in     => reg_src_b_in,
      mult_func     => unit_ctrl.mult_func, mult_busy     => unit_busy.mult,
      mult_out      => mult_out
    );
 
  --
  -- COMPARATOR
  --
  u6_comp: entity PLASMA.plasma_comparator(structure_comparator)
    PORT MAP(
      comp_a_in     => reg_src_a_in,        comp_b_in     => reg_src_b_in,
      comp_func     => unit_ctrl.comp_func,
      comp_out      => comp_out
    );
  end generate;
 
  --
  -- FPU
  --
  u7_fpu: entity PLASMA.plasma_fpu(behav_plasma_fpu)
    GENERIC MAP( DEBUG_FLAG => DEBUG_FLAG)
    PORT MAP(
      control       => control,
 
      fpu_reg_addr  => fpu_reg_addr,    fpu_ctrl      => fpu_ctrl,
 
      busy          => unit_busy.fpu,   cc_out        => fpu_cc,
 
      fpu_id_sel    => mux_fpu.fpu_id,  fpu_mem_sel   => mux_fpu.fpu_mem,
 
      data_to_fpu     => i_src_b_in,
      data_from_fpu   => data_from_fpu,
      data_to_fpu_mem => data_from_mem
    );
--synthesis translate_on
 
 
  -- ____ ___  ____ ____ 
  -- |___ |__] | __ |__| 
  -- |    |    |__] |  | 
  FPGA: if SIM_FLAG = "OF" generate
  --
  -- ALU
  --
  u3_alu: entity PLASMA.plasma_alu(FPGA_alu)
    PORT MAP(
      alu_a_in      => reg_src_a_in,        alu_b_in      => reg_src_b_in,
      alu_func      => unit_ctrl.alu_func,
      alu_out       => alu_out
    );
 
  --
  -- SHIFTER
  --
  u4_shifter: entity PLASMA.plasma_shifter(FPGA_shifter)
    PORT MAP(
      shift_in      => reg_src_a_in,          shift_amount  => reg_src_b_in(4 downto 0),
      shift_func    => unit_ctrl.shift_func,
      shift_out     => shift_out
    );
 
  --
  -- MULTIPLICATOR
  --  
  u5_mult: entity PLASMA.plasma_mult(FPGA_mult)
    PORT MAP(
      control       => control,
      mult_a_in     => reg_src_a_in,              mult_b_in     => reg_src_b_in,
      mult_func     => unit_ctrl.mult_func,       mult_busy     => unit_busy.mult,
      mult_out      => mult_out
    );
 
  --
  -- COMPARATOR
  --
  u6_comp: entity PLASMA.plasma_comparator(structure_comparator)
    PORT MAP(
      comp_a_in     => reg_src_a_in,        comp_b_in     => reg_src_b_in,
      comp_func     => unit_ctrl.comp_func,
      comp_out      => comp_out
    );
  end generate;
 
 
 
  --   ____  _    _ _______ _____  _    _ _______   __  __ _    ___   __
  --  / __ \| |  | |__   __|  __ \| |  | |__   __| |  \/  | |  | \ \ / /
  -- | |  | | |  | |  | |  | |__) | |  | |  | |    | \  / | |  | |\ V / 
  -- | |  | | |  | |  | |  |  ___/| |  | |  | |    | |\/| | |  | | > <  
  -- | |__| | |__| |  | |  | |    | |__| |  | |    | |  | | |__| |/ . \ 
  --  \____/ \____/   |_|  |_|     \____/   |_|    |_|  |_|\____//_/ \_\
  --
  -- OUTPUT MUX
  --
  with mux_ctrl.src_out select
    op_data_out      <= pc_out_inc        when SRC_OUT_PC,
                        shift_out         when SRC_OUT_SHIFT,
                        mult_out          when SRC_OUT_MULT,
                        reg_mem_data_in   when SRC_OUT_MEM_DATA,
                        alu_out           when others;
 
  --
  -- PC VALUE MUX
  --
  with unit_ctrl.pc_func select
    pc_new_value      <=  reg_imm_in      when PLASMA_PC_IMM,
                          reg_src_a_in    when PLASMA_PC_REG,
                          pc_out_branch   when PLASMA_PC_BRANCH,
                          pc_out_inc      when others;
 
  -- ----------------------------------------------------------------------------------------------
  -- ----------------------------------------------------------------------------------------------
  -- #     # ####### #     # ####### ######  #     #     #####  #######    #     #####  ####### 
  -- ##   ## #       ##   ## #     # #     #  #   #     #     #    #      # #   #     # #       
  -- # # # # #       # # # # #     # #     #   # #      #          #     #   #  #       #       
  -- #  #  # #####   #  #  # #     # ######     #        #####     #    #     # #  #### #####   
  -- #     # #       #     # #     # #   #      #             #    #    ####### #     # #       
  -- #     # #       #     # #     # #    #     #       #     #    #    #     # #     # #       
  -- #     # ####### #     # ####### #     #    #        #####     #    #     #  #####  ####### 
  -- ----------------------------------------------------------------------------------------------
  --
  -- MEMORY STAGE RESTIERS
  --
mem_stage_register:
  process( control.clk )
  begin
    if rising_edge( control.clk ) then
      if control.rst = '1' then
        reg_mem_result      <= PLASMA_ZERO_WORD;
        reg_mem_to_memory   <= PLASMA_ZERO_WORD;
      else
        if (stall_src.data = '0') and
           (stall_src.unit = '0')      then
          reg_mem_result    <= op_data_out;
          reg_mem_to_memory <= reg_mem_data_in;
        end if;
      end if;
    end if;
  end process;
 
  --
  -- MEMORY ACCESS OUTPUT
  --
  data_addr          <= reg_mem_result;                                                -- memory access address
  data_to_mem        <= reg_mem_to_memory;                                             -- memory access data
 
  --
  -- MEMORY STAGE MUX
  --
  with mux_ctrl.wb select
    mem_data_out        <=  data_from_mem   when WB_MEMORY,
                            reg_mem_result  when others;
 
  -- ----------------------------------------------------------------------------------------------
  -- ----------------------------------------------------------------------------------------------
  -- #     # ######  ### ####### #######    ######     #     #####  #    #     #####  #######    #     #####  ####### 
  -- #  #  # #     #  #     #    #          #     #   # #   #     # #   #     #     #    #      # #   #     # #       
  -- #  #  # #     #  #     #    #          #     #  #   #  #       #  #      #          #     #   #  #       #       
  -- #  #  # ######   #     #    #####      ######  #     # #       ###        #####     #    #     # #  #### #####   
  -- #  #  # #   #    #     #    #          #     # ####### #       #  #            #    #    ####### #     # #       
  -- #  #  # #    #   #     #    #          #     # #     # #     # #   #     #     #    #    #     # #     # #       
  --  ## ##  #     # ###    #    #######    ######  #     #  #####  #    #     #####     #    #     #  #####  ####### 
  -- ----------------------------------------------------------------------------------------------
  --
  -- WRITE BACK STAGE REGISTER
  --
wb_stage_register:
  process( control.clk )
  begin
    if rising_edge( control.clk ) then
      if control.rst = '1' then
        reg_bank_in   <= PLASMA_ZERO_WORD;
      else
        if (stall_src.data = '0') then
          reg_bank_in <= mem_data_out;
        end if;
      end if;
    end if;
  end process;
 
end architecture structure_plasma_datapath_MIPSI_FPU;
 

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[/] [plasma_fpu/] [trunk/] [src/] [datapaths/] [plasma_datapath_MIPSI_FPU.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	__alexs__	`-- --------------------------------------------------------------------------`
2			`-- >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<`
3			`-- --------------------------------------------------------------------------`
4			`-- TITLE: Plasma DATAPATH`
5			`-- AUTHOR: Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)`
6			`-- COMMENT: This project is based on Plasma CPU core by Steve Rhoads`
7			`--`
8			`-- www.ies.tu-darmstadt.de`
9			`-- TU Darmstadt`
10			`-- Institute for Integrated Systems`
11			`-- Merckstr. 25`
12			`--`
13			`-- 64283 Darmstadt - GERMANY`
14			`-- --------------------------------------------------------------------------`
15			`-- PROJECT: Plasma CPU core with FPU`
16			`-- FILENAME: plasma_datapath.vhd`
17			`-- --------------------------------------------------------------------------`
18			`-- COPYRIGHT:`
19			`-- This project is distributed by GPLv2.0`
20			`-- Software placed into the public domain by the author.`
21			`-- Software 'as is' without warranty. Author liable for nothing.`
22			`-- --------------------------------------------------------------------------`
23			`-- DESCRIPTION:`
24			`-- datapath of plasma core`
25			`--`
26			`-- SYNTHESIZABLE`
27			`--`
28			`----------------------------------------------------------------------------`
29			`-- Revision History`
30			`-- --------------------------------------------------------------------------`
31			`-- Revision Date Author CHANGES`
32			`-- 1.0 4/2014 AS initial`
33			`-- 2.0 12/2014 AS separated into MIPS1 simple architecture`
34			`-- and with FPU included`
35			`-- 3.0 05/2015 AS made generic port, included immediate mux`
36			`-- --------------------------------------------------------------------------`
37			`library IEEE;`
38			`use IEEE.std_logic_1164.ALL;`
39
40			`library PLASMA;`
41			`use PLASMA.mips_instruction_set.ALL;`
42			`use PLASMA.plasma_pack.ALL;`
43
44
45			`entity plasma_datapath_MIPSI_FPU is`
46			`generic(`
47			`core_idx : natural := 0;`
48			`SIM_FLAG : string := "ON";`
49			`DEBUG_FLAG : string := "OF"`
50			`);`
51			`port(`
52			`control : in t_main_control;`
53			`-- input control mux and registers`
54			`reg_addr : in t_reg_addr;`
55			`fpu_reg_addr : in t_reg_addr;`
56			`mux_ctrl : in t_plasma_mux_ctrl;`
57			`mux_fpu : in t_plasma_mux_fpu;`
58			`stall_src : in t_stall_source;`
59			`-- output feedback signals`
60			`comp_out : out std_logic;`
61			`fpu_cc : out std_logic;`
62			`unit_busy : out t_unit_busy;`
63			`-- operation units control`
64			`unit_ctrl : in t_plasma_subunits_ctrl;`
65			`fpu_ctrl : in t_fpu_ctrl;`
66			`-- data`
67			`instr_addr : out t_plasma_word;`
68			`data_addr : out t_plasma_word;`
69
70			`instr_in : in t_plasma_word;`
71			`data_from_mem : in t_plasma_word;`
72			`data_to_mem : out t_plasma_word`
73			`);`
74			`end entity plasma_datapath_MIPSI_FPU;`
75
76
77			`architecture structure_plasma_datapath_MIPSI_FPU of plasma_datapath_MIPSI_FPU is`
78
79			`-- ___ ____ ____ ____ ____ ____ _ _ ____ ____ _ _ _ _ ___ ____ ____`
80			`-- \|__] \|__/ \| \| \| __ \|__/ \|__\| \|\/\| \| \| \| \| \| \|\ \| \| \|___ \|__/`
81			`-- \| \| \ \|__\| \|__] \| \ \| \| \| \| \|___ \|__\| \|__\| \| \\| \| \|___ \| \`
82			`signal pc_new_value : t_plasma_word; -- next pc value`
83			`signal pc_out_inc : t_plasma_word; -- pc + 4`
84			`signal pc_out_branch : t_plasma_word; -- pc + 4 + (imm16 << 2)`
85
86			`-- ____ ____ ____ _ ____ ___ ____ ____ ___ ____ _ _ _ _`
87			`-- \|__/ \|___ \| __ \| [__ \| \|___ \|__/ \|__] \|__\| \|\ \| \|_/`
88			`-- \| \ \|___ \|__] \| ___] \| \|___ \| \ \|__] \| \| \| \\| \| \_`
89			`signal regular_rd : t_mips_reg_addr;`
90			`signal reg_bank_a : t_plasma_word; -- rs`
91			`signal reg_bank_b : t_plasma_word; -- rt`
92
93			`-- _ _ _ _ _ _ _ _ _ _ _`
94			`-- \| \|\/\| \|\/\| \|\/\| \| \| \/`
95			`-- \| \| \| \| \| \| \| \|__\| _/\_`
96			`alias i_shamt : t_mips_shamt is instr_in(10 downto 6);`
97			`alias i_imm : t_mips_imm16 is instr_in(15 downto 0);`
98			`alias i_imm_long : t_mips_imm26 is instr_in(25 downto 0);`
99
100			`signal i_imm_sign : t_mips_imm16;`
101			`signal i_imm_branch : std_logic_vector(31 downto 18);`
102
103			`constant ZERO_SHAMT : std_logic_vector(31 downto 5) := (others => '0');`
104			`constant ZERO_IMM16 : std_logic_vector(15 downto 0) := (others => '0');`
105			`constant ZERO_IMM26 : std_logic_vector(31 downto 28) := (others => '0');`
106
107			`-- _ _ _ ___ _ _ ___ _ _ _ _ _ _ ____ ____`
108			`-- \| \|\ \| \|__] \| \| \| \|\/\| \| \| \/ \|___ [__`
109			`-- \| \| \\| \| \|__\| \| \| \| \|__\| _/\_ \|___ ___]`
110			`signal src_a_in : t_plasma_word;`
111			`signal i_src_b_in : t_plasma_word;`
112			`signal src_b_in : t_plasma_word;`
113			`signal imm_in : t_plasma_word;`
114			`signal mem_data_in : t_plasma_word;`
115			`signal data_from_fpu : t_plasma_word;`
116
117			`-- ____ _ _ ____ ___ ____ ____ ____ ____ ____ ____ ____`
118			`-- \|___ \/ [__ \| \|__\| \| __ \|___ \|__/ \|___ \| __ [__`
119			`-- \|___ _/\_ ___] \| \| \| \|__] \|___ \| \ \|___ \|__] ___]`
120			`signal reg_src_a_in : t_plasma_word;`
121			`signal reg_src_b_in : t_plasma_word;`
122			`signal reg_imm_in : t_plasma_word;`
123			`signal reg_mem_data_in : t_plasma_word;`
124
125			`-- ____ _ _ ___ ___ _ _ ___ _ _ _ _ _ _`
126			`-- \| \| \| \| \| \|__] \| \| \| \|\/\| \| \| \/`
127			`-- \|__\| \|__\| \| \| \|__\| \| \| \| \|__\| _/\_`
128			`signal alu_out : t_plasma_word;`
129			`signal shift_out : t_plasma_word;`
130			`signal mult_out : t_plasma_word;`
131
132			`signal op_data_out : t_plasma_word;`
133
134			`-- _ _ ____ _ _ ____ ___ ____ ____ ____ ____ ____ ____`
135			`-- \|\/\| \|___ \|\/\| [__ \| \|__\| \| __ \|___ \|__/ \|___ \| __`
136			`-- \| \| \|___ \| \| ___] \| \| \| \|__] \|___ \| \ \|___ \|__]`
137			`signal reg_mem_result : t_plasma_word;`
138			`signal reg_mem_to_memory : t_plasma_word;`
139
140			`signal mem_data_out : t_plasma_word;`
141
142			`-- _ _ _ ___ ____ ___ ____ ____ ____ ____ ____ ____`
143			`-- \| \| \| \|__] [__ \| \|__\| \| __ \|___ \|__/ \|___ \| __`
144			`-- \|_\|_\| \|__] ___] \| \| \| \|__] \|___ \| \ \|___ \|__]`
145			`signal reg_bank_in : t_plasma_word;`
146
147			`begin ---------- BEGIN -------------------- BEGIN --------------------- BEGIN -------------------`
148			`-- ----------------------------------------------------------------------------------------------`
149			`-- _____ _____ ____ _____ _____ __ __ _____ ____ _ _ _ _ _______ ______ _____`
150			`-- \| __ \\| __ \ / __ \ / ____\| __ \ /\ \| \/ \| / ____/ __ \\| \| \| \| \ \| \|__ __\| ____\| __ \`
151			`-- \| \|__) \| \|__) \| \| \| \| \| __\| \|__) \| / \ \| \ / \| \| \| \| \| \| \| \| \| \| \\| \| \| \| \| \|__ \| \|__) \|`
152			-- \| ___/\| _ /\| \| \| \| \| \|_ \| _ / / /\ \ \| \|\/\| \| \| \| \| \| \| \| \| \| \| . ` \| \| \| \| __\| \| _ /
153			`-- \| \| \| \| \ \\| \|__\| \| \|__\| \| \| \ \ / ____ \\| \| \| \| \| \|___\| \|__\| \| \|__\| \| \|\ \| \| \| \| \|____\| \| \ \`
154			`-- \|_\| \|_\| \_\\____/ \_____\|_\| \_\/_/ \_\_\| \|_\| \_____\____/ \____/\|_\| \_\| \|_\| \|______\|_\| \_\`
155			`-- ----------------------------------------------------------------------------------------------`
156			`--`
157			`-- PC UNIT`
158			`--`
159			`u1_pc: plasma_pc`
160			`PORT MAP(`
161			`control => control,`
162			`stall => stall_src.pc,`
163			`pc_imm_in => reg_imm_in,`
164			`pc_new_value => pc_new_value,`
165			`pc_out.pc_out_inc => pc_out_inc,`
166			`pc_out.pc_out_branch => pc_out_branch,`
167			`pc_out.pc_out => instr_addr`
168			`);`
169
170			`-- ----------------------------------------------------------------------------------------------`
171			`-- _____ ______ _____ _____ _____ _______ ______ _____ ____ _ _ _ __`
172			`-- \| __ \\| ____/ ____\|_ _\|/ ____\|__ __\| ____\| __ \ \| _ \ /\ \| \ \| \| \|/ /`
173			`-- \| \|__) \| \|__ \| \| __ \| \| \| (___ \| \| \| \|__ \| \|__) \| \| \|_) \| / \ \| \\| \| ' /`
174			-- \| _ /\| __\|\| \| \|_ \| \| \| \___ \ \| \| \| __\| \| _ / \| _ < / /\ \ \| . ` \| <
175			`-- \| \| \ \\| \|___\| \|__\| \|_\| \|_ ____) \| \| \| \| \|____\| \| \ \ \| \|_) / ____ \\| \|\ \| . \`
176			`-- \|_\| \_\______\_____\|_____\|_____/ \|_\| \|______\|_\| \_\ \|____/_/ \_\_\| \_\|_\|\_\`
177			`-- ----------------------------------------------------------------------------------------------`
178			`--`
179			`-- REGISTER BANK UNIT`
180			`--`
181			`u2_reg_bank: plasma_reg_bank`
182			`GENERIC MAP(`
183			`core_idx => core_idx,`
184			`DEBUG_FLAG => DEBUG_FLAG`
185			`)`
186			`PORT MAP(`
187			`control => control,`
188			`reg_addr => reg_addr,`
189			`reg_dest_new => reg_bank_in,`
190			`reg_source_out => reg_bank_a,`
191			`reg_target_out => reg_bank_b`
192			`);`
193
194			`-- ----------------------------------------------------------------------------------------------`
195			`-- ----------------------------------------------------------------------------------------------`
196			`-- ###### ####### ##### ####### ###### ####### ##### ####### # ##### #######`
197			`-- # # # # # # # # # # # # # # # # # #`
198			`-- # # # # # # # # # # # # # # #`
199			`-- # # ##### # # # # # ##### ##### # # # # #### #####`
200			`-- # # # # # # # # # # # ####### # # #`
201			`-- # # # # # # # # # # # # # # # # # #`
202			`-- ###### ####### ##### ####### ###### ####### ##### # # # ##### #######`
203			`-- ----------------------------------------------------------------------------------------------`
204
205			`-- ----------------------------------------------------------------------------------------------`
206			`-- _____ _ _ _____ _ _ _______ __ __ _ ___ ________ _____`
207			`-- \|_ _\| \ \| \| __ \\| \| \| \|__ __\| \| \/ \| \| \| \ \ / / ____\|/ ____\|`
208			`-- \| \| \| \\| \| \|__) \| \| \| \| \| \| \| \ / \| \| \| \|\ V /\| \|__ \| (___`
209			-- \| \| \| . ` \| ___/\| \| \| \| \| \| \| \|\/\| \| \| \| \| > < \| __\| \___ \
210			`-- _\| \|_\| \|\ \| \| \| \|__\| \| \| \| \| \| \| \| \|__\| \|/ . \\| \|____ ____) \|`
211			`-- \|_____\|_\| \_\|_\| \____/ \|_\| \|_\| \|_\|\____//_/ \_\______\|_____/`
212			`-- ----------------------------------------------------------------------------------------------`
213			`--`
214			`-- IMMEDIATE VALUE MUX`
215			`--`
216			`i_imm_sign <= (others => i_imm(15));`
217			`i_imm_branch <= (others => i_imm(15));`
218
219
220			`with mux_ctrl.src_imm select`
221			`imm_in <= ZERO_IMM16 & i_imm when IMM_UNSIGN,`
222			`i_imm & ZERO_IMM16 when IMM_HIGH,`
223			`ZERO_SHAMT & i_shamt when IMM_SHAMT,`
224			`i_imm_branch & i_imm & b"00" when IMM_BRANCH,`
225			`ZERO_IMM26 & i_imm_long & b"00" when IMM_JUMP,`
226			`i_imm_sign & i_imm when others;`
227
228			`--`
229			`-- SOURCE A MUX`
230			`--`
231			`with mux_ctrl.src_a select`
232			`src_a_in <= op_data_out when SRC_OP_OUT,`
233			`mem_data_out when SRC_MEM_OUT,`
234			`reg_bank_in when SRC_WB_OUT,`
235			`reg_bank_a when others;`
236
237			`--`
238			`-- SOURCE B MUX`
239			`--`
240			`with mux_ctrl.src_b select`
241			`i_src_b_in <= op_data_out when SRC_OP_OUT,`
242			`mem_data_out when SRC_MEM_OUT,`
243			`reg_bank_in when SRC_WB_OUT,`
244			`reg_bank_b when others;`
245
246			`--`
247			`-- IMMEDIATE SWITCH`
248			`--`
249			`with mux_ctrl.src_b_imm select`
250			`src_b_in <= imm_in when B_IMM_ON,`
251			`i_src_b_in when others;`
252
253			`--`
254			`-- MEMORY INPUT`
255			`--`
256			`with mux_fpu.cop select`
257			`mem_data_in <= data_from_fpu when COP_SELECT_COP1,`
258			`i_src_b_in when others;`
259
260			`-- ----------------------------------------------------------------------------------------------`
261			`-- ----------------------------------------------------------------------------------------------`
262			`-- ####### # # ####### ##### # # ####### ####### ##### ####### # ##### #######`
263			`-- # # # # # # # # # # # # # # # # # #`
264			`-- # # # # # # # # # # # # # # #`
265			`-- ##### # ##### # # # # ##### ##### # # # # #### #####`
266			`-- # # # # # # # # # # # ####### # # #`
267			`-- # # # # # # # # # # # # # # # # # #`
268			`-- ####### # # ####### ##### ##### # ####### ##### # # # ##### #######`
269			`-- ----------------------------------------------------------------------------------------------`
270
271			`-- ----------------------------------------------------------------------------------------------`
272			`-- ________ __ _____ _______ _____ ______ _____ ______ _____ _____`
273			`-- \| ____\ \ / / / ____\|__ __\|/\ / ____\| ____\| \| __ \\| ____/ ____\|/ ____\|`
274			`-- \| \|__ \ V / \| (___ \| \| / \ \| \| __\| \|__ \| \|__) \| \|__ \| \| __\| (___`
275			`-- \| __\| > < \___ \ \| \| / /\ \\| \| \|_ \| __\| \| _ /\| __\|\| \| \|_ \|\___ \`
276			`-- \| \|____ / . \ ____) \| \| \|/ ____ \ \|__\| \| \|____ \| \| \ \\| \|___\| \|__\| \|____) \|`
277			`-- \|______/_/ \_\ \|_____/ \|_/_/ \_\_____\|______\| \|_\| \_\______\_____\|_____/`
278			`-- ----------------------------------------------------------------------------------------------`
279			`ex_stage_registers:`
280			`process( control.clk )`
281			`begin`
282			`if rising_edge( control.clk ) then`
283			`if control.rst = '1' then`
284			`reg_src_a_in <= PLASMA_ZERO_WORD;`
285			`reg_src_b_in <= PLASMA_ZERO_WORD;`
286			`reg_imm_in <= PLASMA_ZERO_WORD;`
287
288			`reg_mem_data_in <= PLASMA_ZERO_WORD;`
289			`else`
290			`if stall_src.pc = '0' then`
291			`reg_src_a_in <= src_a_in;`
292			`reg_src_b_in <= src_b_in;`
293			`reg_imm_in <= imm_in;`
294
295			`reg_mem_data_in <= mem_data_in;`
296			`end if;`
297			`end if;`
298			`end if;`
299			`end process;`
300
301			`-- ----------------------------------------------------------------------------------------------`
302			`-- ____ _____ ______ _____ _______ _____ ____ _ _ _ _ _ _ _____ _______ _____`
303			`-- / __ \\| __ \\| ____\| __ \ /\\|__ __\|_ _/ __ \\| \ \| \| \| \| \| \| \ \| \|_ _\|__ __/ ____\|`
304			`-- \| \| \| \| \|__) \| \|__ \| \|__) \| / \ \| \| \| \|\| \| \| \| \\| \| \| \| \| \| \\| \| \| \| \| \| \| (___`
305			-- \| \| \| \| ___/\| __\| \| _ / / /\ \ \| \| \| \|\| \| \| \| . ` \| \| \| \| \| . ` \| \| \| \| \| \___ \
306			`-- \| \|__\| \| \| \| \|____\| \| \ \ / ____ \\| \| _\| \|\| \|__\| \| \|\ \| \| \|__\| \| \|\ \|_\| \|_ \| \| ____) \|`
307			`-- \____/\|_\| \|______\|_\| \_\/_/ \_\_\| \|_____\____/\|_\| \_\| \____/\|_\| \_\|_____\| \|_\| \|_____/`
308			`-- ----------------------------------------------------------------------------------------------`
309			`-- ____ _ _ _ _ _ _ ____ ___ _ ____ _ _`
310			`-- [__ \| \|\/\| \| \| \| \|__\| \| \| \| \| \|\ \|`
311			`-- ___] \| \| \| \|__\| \|___ \| \| \| \| \|__\| \| \\|`
312			`--synthesis translate_off`
313			`SIM: if SIM_FLAG = "ON" generate`
314			`--`
315			`-- ALU`
316			`--`
317			`u3_alu: entity PLASMA.plasma_alu(sim_alu)`
318			`PORT MAP(`
319			`alu_a_in => reg_src_a_in, alu_b_in => reg_src_b_in,`
320			`alu_func => unit_ctrl.alu_func,`
321			`alu_out => alu_out`
322			`);`
323
324			`--`
325			`-- SHIFTER`
326			`--`
327			`u4_shifter: entity PLASMA.plasma_shifter(sim_shifter)`
328			`PORT MAP(`
329			`shift_in => reg_src_a_in, shift_amount => reg_src_b_in(4 downto 0),`
330			`shift_func => unit_ctrl.shift_func,`
331			`shift_out => shift_out`
332			`);`
333
334			`--`
335			`-- MULTIPLICATOR`
336			`--`
337			`u5_mult: entity PLASMA.plasma_mult(sim_mult)`
338			`PORT MAP(`
339			`control => control,`
340			`mult_a_in => reg_src_a_in, mult_b_in => reg_src_b_in,`
341			`mult_func => unit_ctrl.mult_func, mult_busy => unit_busy.mult,`
342			`mult_out => mult_out`
343			`);`
344
345			`--`
346			`-- COMPARATOR`
347			`--`
348			`u6_comp: entity PLASMA.plasma_comparator(structure_comparator)`
349			`PORT MAP(`
350			`comp_a_in => reg_src_a_in, comp_b_in => reg_src_b_in,`
351			`comp_func => unit_ctrl.comp_func,`
352			`comp_out => comp_out`
353			`);`
354			`end generate;`
355
356			`--`
357			`-- FPU`
358			`--`
359			`u7_fpu: entity PLASMA.plasma_fpu(behav_plasma_fpu)`
360			`GENERIC MAP( DEBUG_FLAG => DEBUG_FLAG)`
361			`PORT MAP(`
362			`control => control,`
363
364			`fpu_reg_addr => fpu_reg_addr, fpu_ctrl => fpu_ctrl,`
365
366			`busy => unit_busy.fpu, cc_out => fpu_cc,`
367
368			`fpu_id_sel => mux_fpu.fpu_id, fpu_mem_sel => mux_fpu.fpu_mem,`
369
370			`data_to_fpu => i_src_b_in,`
371			`data_from_fpu => data_from_fpu,`
372			`data_to_fpu_mem => data_from_mem`
373			`);`
374			`--synthesis translate_on`
375
376
377			`-- ____ ___ ____ ____`
378			`-- \|___ \|__] \| __ \|__\|`
379			`-- \| \| \|__] \| \|`
380			`FPGA: if SIM_FLAG = "OF" generate`
381			`--`
382			`-- ALU`
383			`--`
384			`u3_alu: entity PLASMA.plasma_alu(FPGA_alu)`
385			`PORT MAP(`
386			`alu_a_in => reg_src_a_in, alu_b_in => reg_src_b_in,`
387			`alu_func => unit_ctrl.alu_func,`
388			`alu_out => alu_out`
389			`);`
390
391			`--`
392			`-- SHIFTER`
393			`--`
394			`u4_shifter: entity PLASMA.plasma_shifter(FPGA_shifter)`
395			`PORT MAP(`
396			`shift_in => reg_src_a_in, shift_amount => reg_src_b_in(4 downto 0),`
397			`shift_func => unit_ctrl.shift_func,`
398			`shift_out => shift_out`
399			`);`
400
401			`--`
402			`-- MULTIPLICATOR`
403			`--`
404			`u5_mult: entity PLASMA.plasma_mult(FPGA_mult)`
405			`PORT MAP(`
406			`control => control,`
407			`mult_a_in => reg_src_a_in, mult_b_in => reg_src_b_in,`
408			`mult_func => unit_ctrl.mult_func, mult_busy => unit_busy.mult,`
409			`mult_out => mult_out`
410			`);`
411
412			`--`
413			`-- COMPARATOR`
414			`--`
415			`u6_comp: entity PLASMA.plasma_comparator(structure_comparator)`
416			`PORT MAP(`
417			`comp_a_in => reg_src_a_in, comp_b_in => reg_src_b_in,`
418			`comp_func => unit_ctrl.comp_func,`
419			`comp_out => comp_out`
420			`);`
421			`end generate;`
422
423
424
425			`-- ____ _ _ _______ _____ _ _ _______ __ __ _ ___ __`
426			`-- / __ \\| \| \| \|__ __\| __ \\| \| \| \|__ __\| \| \/ \| \| \| \ \ / /`
427			`-- \| \| \| \| \| \| \| \| \| \| \|__) \| \| \| \| \| \| \| \ / \| \| \| \|\ V /`
428			`-- \| \| \| \| \| \| \| \| \| \| ___/\| \| \| \| \| \| \| \|\/\| \| \| \| \| > <`
429			`-- \| \|__\| \| \|__\| \| \| \| \| \| \| \|__\| \| \| \| \| \| \| \| \|__\| \|/ . \`
430			`-- \____/ \____/ \|_\| \|_\| \____/ \|_\| \|_\| \|_\|\____//_/ \_\`
431			`--`
432			`-- OUTPUT MUX`
433			`--`
434			`with mux_ctrl.src_out select`
435			`op_data_out <= pc_out_inc when SRC_OUT_PC,`
436			`shift_out when SRC_OUT_SHIFT,`
437			`mult_out when SRC_OUT_MULT,`
438			`reg_mem_data_in when SRC_OUT_MEM_DATA,`
439			`alu_out when others;`
440
441			`--`
442			`-- PC VALUE MUX`
443			`--`
444			`with unit_ctrl.pc_func select`
445			`pc_new_value <= reg_imm_in when PLASMA_PC_IMM,`
446			`reg_src_a_in when PLASMA_PC_REG,`
447			`pc_out_branch when PLASMA_PC_BRANCH,`
448			`pc_out_inc when others;`
449
450			`-- ----------------------------------------------------------------------------------------------`
451			`-- ----------------------------------------------------------------------------------------------`
452			`-- # # ####### # # ####### ###### # # ##### ####### # ##### #######`
453			`-- ## ## # ## ## # # # # # # # # # # # # # #`
454			`-- # # # # # # # # # # # # # # # # # # # # #`
455			`-- # # # ##### # # # # # ###### # ##### # # # # #### #####`
456			`-- # # # # # # # # # # # # ####### # # #`
457			`-- # # # # # # # # # # # # # # # # # #`
458			`-- # # ####### # # ####### # # # ##### # # # ##### #######`
459			`-- ----------------------------------------------------------------------------------------------`
460			`--`
461			`-- MEMORY STAGE RESTIERS`
462			`--`
463			`mem_stage_register:`
464			`process( control.clk )`
465			`begin`
466			`if rising_edge( control.clk ) then`
467			`if control.rst = '1' then`
468			`reg_mem_result <= PLASMA_ZERO_WORD;`
469			`reg_mem_to_memory <= PLASMA_ZERO_WORD;`
470			`else`
471			`if (stall_src.data = '0') and`
472			`(stall_src.unit = '0') then`
473			`reg_mem_result <= op_data_out;`
474			`reg_mem_to_memory <= reg_mem_data_in;`
475			`end if;`
476			`end if;`
477			`end if;`
478			`end process;`
479
480			`--`
481			`-- MEMORY ACCESS OUTPUT`
482			`--`
483			`data_addr <= reg_mem_result; -- memory access address`
484			`data_to_mem <= reg_mem_to_memory; -- memory access data`
485
486			`--`
487			`-- MEMORY STAGE MUX`
488			`--`
489			`with mux_ctrl.wb select`
490			`mem_data_out <= data_from_mem when WB_MEMORY,`
491			`reg_mem_result when others;`
492
493			`-- ----------------------------------------------------------------------------------------------`
494			`-- ----------------------------------------------------------------------------------------------`
495			`-- # # ###### ### ####### ####### ###### # ##### # # ##### ####### # ##### #######`
496			`-- # # # # # # # # # # # # # # # # # # # # # # # #`
497			`-- # # # # # # # # # # # # # # # # # # # # #`
498			`-- # # # ###### # # ##### ###### # # # ### ##### # # # # #### #####`
499			`-- # # # # # # # # # # ####### # # # # # ####### # # #`
500			`-- # # # # # # # # # # # # # # # # # # # # # # # #`
501			`-- ## ## # # ### # ####### ###### # # ##### # # ##### # # # ##### #######`
502			`-- ----------------------------------------------------------------------------------------------`
503			`--`
504			`-- WRITE BACK STAGE REGISTER`
505			`--`
506			`wb_stage_register:`
507			`process( control.clk )`
508			`begin`
509			`if rising_edge( control.clk ) then`
510			`if control.rst = '1' then`
511			`reg_bank_in <= PLASMA_ZERO_WORD;`
512			`else`
513			`if (stall_src.data = '0') then`
514			`reg_bank_in <= mem_data_out;`
515			`end if;`
516			`end if;`
517			`end if;`
518			`end process;`
519
520			`end architecture structure_plasma_datapath_MIPSI_FPU;`
521