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feddischso |
BEGIN plb2wb_bridge
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION IP_GROUP = Bus and Bridge:MICROBLAZE
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OPTION DESC = Plb-to-wishbone bridge
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## Bus Interfaces
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BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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BUS_INTERFACE BUS = MWB, BUS_STD = WB, BUS_TYPE = MASTER
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PARAMETER SYNCHRONY = true, DT = boolean, VALUES = ( true = synchron, false = asynchron )
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## Parameters for WB
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PARAMETER WB_DAT_W = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
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PARAMETER WB_ADR_W = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
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PARAMETER WB_ADR_OFFSET = 0x00000000, DT = std_logic_vector
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PARAMETER WB_ADR_OFFSET_NEG = 0, DT = std_logic, VALUES = ( 0 = false, 1 = true )
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PARAMETER WB_PIC_INTS = 1, DT = INTEGER, RANGE = (1 : 32),
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PARAMETER WB_PIC_INT_LEVEL = 1, DT = std_logic, VALUES = ( 0 = active_low, 1 = active_high )
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PARAMETER WB_TIMEOUT_CYCLES = 10, DT = integer, RANGE = (2 : 256 )
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PARAMETER WB_SUPPORT_BLOCK = 1, DT = integer, VALUES = ( 1 = supported, 0 = not supported )
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## Parameters for PLB
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PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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PARAMETER C_STATUS_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_STATUS_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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PARAMETER C_STATUS_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_STATUS_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
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PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
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PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
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PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
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PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
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PARAMETER C_SPLB_SUPPORT_BUR_LINE= 1, DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )
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PARAMETER C_SPLB_SUPPORT_ADR_PIPE= 1, DT = INTEGER, BUS = SPLB, VALUES = ( 1 = supported, 0 = not supported )
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## Ports PLB
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PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT PLB2WB_IRQ = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = MEDIUM
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## Ports WB
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PORT wb_clk_i = "", DIR = I, SIGIS = CLK
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PORT wb_rst_i = "", DIR = I, SIGIS = RST
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PORT wb_pic_int_i= "", DIR = I, VEC = [ WB_PIC_INTS-1: 0 ], SIGIS = INTERRUPT
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PORT wb_dat_i = wb_m_dat_o, DIR = IN , VEC = [ WB_DAT_W-1 : 0 ], BUS = MWB
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PORT wb_dat_o = wb_m_dat_i, DIR = OUT, VEC = [ WB_DAT_W-1 : 0 ], BUS = MWB
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PORT wb_adr_o = wb_m_adr_i, DIR = OUT, VEC = [ WB_ADR_W-1 : 0 ], BUS = MWB
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PORT wb_sel_o = wb_m_sel_i, DIR = OUT, VEC = [ WB_DAT_W/8-1 : 0 ], BUS = MWB
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PORT wb_we_o = wb_m_we_i , DIR = OUT, BUS = MWB
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PORT wb_cyc_o = wb_m_cyc_i, DIR = OUT, BUS = MWB
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PORT wb_stb_o = wb_m_stb_i, DIR = OUT, BUS = MWB
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PORT wb_ack_i = wb_m_ack_o, DIR = IN , BUS = MWB
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PORT wb_err_i = wb_m_err_o, DIR = IN , BUS = MWB
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PORT wb_rty_i = wb_m_rty_o, DIR = IN , BUS = MWB
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# note: wb_lock_o is not used, because the arbiter doesn't support it.
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# if u want to use a WB with wb_lock, use the following line --,
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#PORT wb_lock_o = "wb_m_lock_i", DIR = OUT, BUS = MWB <---'
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PORT wb_lock_o = "", DIR = OUT,
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END
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