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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [plb2wb_bridge_v1_00_a/] [hdl/] [vhdl/] [fifo_adr.vhd] - Blame information for rev 2

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----------------------------------------------------------------------
----                                                              ----
----  PLB2WB-Bridge                                               ----
----                                                              ----
----  This file is part of the PLB-to-WB-Bridge project           ----
----  http://opencores.org/project,plb2wbbridge                   ----
----                                                              ----
----  Description                                                 ----
----  Implementation of a PLB-to-WB-Bridge according to           ----
----  PLB-to-WB Bridge specification document.                    ----
----                                                              ----
----  To Do:                                                      ----
----   Nothing                                                    ----
----                                                              ----
----  Author(s):                                                  ----
----      - Christian Haettich                                    ----
----        feddischson@opencores.org                             ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2010 Authors                                   ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE.  See the GNU Lesser General Public License for more ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library plb2wb_bridge_v1_00_a;
 
entity fifo_adr is
   generic
   (
      SYNCHRONY               : boolean := true;  -- true = synchron, false = asynchron
      C_SPLB_MID_WIDTH        : integer := 3
 
   );
   port(
    rd_en   : in  STD_LOGIC      := 'X';
    wr_en   : in  STD_LOGIC      := 'X';
    full    : out STD_LOGIC;
    empty   : out STD_LOGIC;
    wr_clk  : in  STD_LOGIC      := 'X';
    rst     : in  STD_LOGIC      := 'X';
    rd_clk  : in  STD_LOGIC      := 'X';
    dout    : out STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 );
    din     : in  STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 )
 
   );
end entity fifo_adr;
 
 
 
 
architecture IMP of fifo_adr is
 
 
 
   component fifo_adr_cc_1 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )
     );
   end component fifo_adr_cc_1;
 
   component fifo_adr_ic_1 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       wr_clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       rd_clk : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )
     );
   end component fifo_adr_ic_1;
 
   component fifo_adr_cc_2 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )
     );
   end component fifo_adr_cc_2;
 
   component fifo_adr_ic_2 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       wr_clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       rd_clk : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )
     );
   end component fifo_adr_ic_2;
 
   component fifo_adr_cc_3 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )
     );
   end component fifo_adr_cc_3;
 
   component fifo_adr_ic_3 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       wr_clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       rd_clk : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )
     );
   end component fifo_adr_ic_3;
 
   component fifo_adr_cc_4 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )
     );
   end component fifo_adr_cc_4;
 
   component fifo_adr_ic_4 is
     port (
       rd_en : in STD_LOGIC := 'X';
       wr_en : in STD_LOGIC := 'X';
       full : out STD_LOGIC;
       empty : out STD_LOGIC;
       wr_clk : in STD_LOGIC := 'X';
       rst : in STD_LOGIC := 'X';
       rd_clk : in STD_LOGIC := 'X';
       dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );
       din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )
     );
   end component fifo_adr_ic_4;
 
 
begin
 
 
 
 
fifo_cc_1: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 1  ) generate
U_fifo_cc : fifo_adr_cc_1
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      clk      => rd_clk,  --  rd_clk must be the same than wr_clk!
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_cc_1;
 
 
 
fifo_cc_2: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 2 ) generate
U_fifo_cc : fifo_adr_cc_2
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      clk      => rd_clk,  --  rd_clk must be the same than wr_clk!
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_cc_2;
 
 
 
fifo_cc_3: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 3 ) generate
U_fifo_cc : fifo_adr_cc_3
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      clk      => rd_clk,  --  rd_clk must be the same than wr_clk!
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_cc_3;
 
 
 
fifo_cc_4: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 4 ) generate
U_fifo_cc : fifo_adr_cc_4
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      clk      => rd_clk,  --  rd_clk must be the same than wr_clk!
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_cc_4;
 
 
 
fifo_ic_1: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 1 ) generate
U_fifo_ic : fifo_adr_ic_1
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      rd_clk   => rd_clk,
      wr_clk   => wr_clk,
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_ic_1;
 
 
fifo_ic_2: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 2 ) generate
U_fifo_ic : fifo_adr_ic_2
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      rd_clk   => rd_clk,
      wr_clk   => wr_clk,
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_ic_2;
 
 
fifo_ic_3: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 3 ) generate
U_fifo_ic : fifo_adr_ic_3
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      rd_clk   => rd_clk,
      wr_clk   => wr_clk,
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_ic_3;
 
 
fifo_ic_4: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 4 ) generate
U_fifo_ic : fifo_adr_ic_4
   port map(
      rd_en    => rd_en,
      wr_en    => wr_en,
      full     => full,
      empty    => empty,
      rd_clk   => rd_clk,
      wr_clk   => wr_clk,
      rst      => rst,
      dout     => dout,
      din      => din
   );
end generate fifo_ic_4;
 
 
 
 
end architecture IMP;

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [plb2wb_bridge_v1_00_a/] [hdl/] [vhdl/] [fifo_adr.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	feddischso	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- PLB2WB-Bridge ----`
4			`---- ----`
5			`---- This file is part of the PLB-to-WB-Bridge project ----`
6			`---- http://opencores.org/project,plb2wbbridge ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Implementation of a PLB-to-WB-Bridge according to ----`
10			`---- PLB-to-WB Bridge specification document. ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- Nothing ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Christian Haettich ----`
17			`---- feddischson@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2010 Authors ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45
46
47			`library ieee;`
48			`use ieee.std_logic_1164.all;`
49			`use ieee.std_logic_arith.all;`
50			`use ieee.std_logic_unsigned.all;`
51
52			`library plb2wb_bridge_v1_00_a;`
53
54			`entity fifo_adr is`
55			`generic`
56			`(`
57			`SYNCHRONY : boolean := true; -- true = synchron, false = asynchron`
58			`C_SPLB_MID_WIDTH : integer := 3`
59
60			`);`
61			`port(`
62			`rd_en : in STD_LOGIC := 'X';`
63			`wr_en : in STD_LOGIC := 'X';`
64			`full : out STD_LOGIC;`
65			`empty : out STD_LOGIC;`
66			`wr_clk : in STD_LOGIC := 'X';`
67			`rst : in STD_LOGIC := 'X';`
68			`rd_clk : in STD_LOGIC := 'X';`
69			`dout : out STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 );`
70			`din : in STD_LOGIC_VECTOR ( 0 to 41+C_SPLB_MID_WIDTH-1 )`
71
72			`);`
73			`end entity fifo_adr;`
74
75
76
77
78			`architecture IMP of fifo_adr is`
79
80
81
82			`component fifo_adr_cc_1 is`
83			`port (`
84			`rd_en : in STD_LOGIC := 'X';`
85			`wr_en : in STD_LOGIC := 'X';`
86			`full : out STD_LOGIC;`
87			`empty : out STD_LOGIC;`
88			`clk : in STD_LOGIC := 'X';`
89			`rst : in STD_LOGIC := 'X';`
90			`dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );`
91			`din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )`
92			`);`
93			`end component fifo_adr_cc_1;`
94
95			`component fifo_adr_ic_1 is`
96			`port (`
97			`rd_en : in STD_LOGIC := 'X';`
98			`wr_en : in STD_LOGIC := 'X';`
99			`full : out STD_LOGIC;`
100			`empty : out STD_LOGIC;`
101			`wr_clk : in STD_LOGIC := 'X';`
102			`rst : in STD_LOGIC := 'X';`
103			`rd_clk : in STD_LOGIC := 'X';`
104			`dout : out STD_LOGIC_VECTOR ( 42-1 downto 0 );`
105			`din : in STD_LOGIC_VECTOR ( 42-1 downto 0 )`
106			`);`
107			`end component fifo_adr_ic_1;`
108
109			`component fifo_adr_cc_2 is`
110			`port (`
111			`rd_en : in STD_LOGIC := 'X';`
112			`wr_en : in STD_LOGIC := 'X';`
113			`full : out STD_LOGIC;`
114			`empty : out STD_LOGIC;`
115			`clk : in STD_LOGIC := 'X';`
116			`rst : in STD_LOGIC := 'X';`
117			`dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );`
118			`din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )`
119			`);`
120			`end component fifo_adr_cc_2;`
121
122			`component fifo_adr_ic_2 is`
123			`port (`
124			`rd_en : in STD_LOGIC := 'X';`
125			`wr_en : in STD_LOGIC := 'X';`
126			`full : out STD_LOGIC;`
127			`empty : out STD_LOGIC;`
128			`wr_clk : in STD_LOGIC := 'X';`
129			`rst : in STD_LOGIC := 'X';`
130			`rd_clk : in STD_LOGIC := 'X';`
131			`dout : out STD_LOGIC_VECTOR ( 43-1 downto 0 );`
132			`din : in STD_LOGIC_VECTOR ( 43-1 downto 0 )`
133			`);`
134			`end component fifo_adr_ic_2;`
135
136			`component fifo_adr_cc_3 is`
137			`port (`
138			`rd_en : in STD_LOGIC := 'X';`
139			`wr_en : in STD_LOGIC := 'X';`
140			`full : out STD_LOGIC;`
141			`empty : out STD_LOGIC;`
142			`clk : in STD_LOGIC := 'X';`
143			`rst : in STD_LOGIC := 'X';`
144			`dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );`
145			`din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )`
146			`);`
147			`end component fifo_adr_cc_3;`
148
149			`component fifo_adr_ic_3 is`
150			`port (`
151			`rd_en : in STD_LOGIC := 'X';`
152			`wr_en : in STD_LOGIC := 'X';`
153			`full : out STD_LOGIC;`
154			`empty : out STD_LOGIC;`
155			`wr_clk : in STD_LOGIC := 'X';`
156			`rst : in STD_LOGIC := 'X';`
157			`rd_clk : in STD_LOGIC := 'X';`
158			`dout : out STD_LOGIC_VECTOR ( 44-1 downto 0 );`
159			`din : in STD_LOGIC_VECTOR ( 44-1 downto 0 )`
160			`);`
161			`end component fifo_adr_ic_3;`
162
163			`component fifo_adr_cc_4 is`
164			`port (`
165			`rd_en : in STD_LOGIC := 'X';`
166			`wr_en : in STD_LOGIC := 'X';`
167			`full : out STD_LOGIC;`
168			`empty : out STD_LOGIC;`
169			`clk : in STD_LOGIC := 'X';`
170			`rst : in STD_LOGIC := 'X';`
171			`dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );`
172			`din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )`
173			`);`
174			`end component fifo_adr_cc_4;`
175
176			`component fifo_adr_ic_4 is`
177			`port (`
178			`rd_en : in STD_LOGIC := 'X';`
179			`wr_en : in STD_LOGIC := 'X';`
180			`full : out STD_LOGIC;`
181			`empty : out STD_LOGIC;`
182			`wr_clk : in STD_LOGIC := 'X';`
183			`rst : in STD_LOGIC := 'X';`
184			`rd_clk : in STD_LOGIC := 'X';`
185			`dout : out STD_LOGIC_VECTOR ( 45-1 downto 0 );`
186			`din : in STD_LOGIC_VECTOR ( 45-1 downto 0 )`
187			`);`
188			`end component fifo_adr_ic_4;`
189
190
191			`begin`
192
193
194
195
196			`fifo_cc_1: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 1 ) generate`
197			`U_fifo_cc : fifo_adr_cc_1`
198			`port map(`
199			`rd_en => rd_en,`
200			`wr_en => wr_en,`
201			`full => full,`
202			`empty => empty,`
203			`clk => rd_clk, -- rd_clk must be the same than wr_clk!`
204			`rst => rst,`
205			`dout => dout,`
206			`din => din`
207			`);`
208			`end generate fifo_cc_1;`
209
210
211
212			`fifo_cc_2: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 2 ) generate`
213			`U_fifo_cc : fifo_adr_cc_2`
214			`port map(`
215			`rd_en => rd_en,`
216			`wr_en => wr_en,`
217			`full => full,`
218			`empty => empty,`
219			`clk => rd_clk, -- rd_clk must be the same than wr_clk!`
220			`rst => rst,`
221			`dout => dout,`
222			`din => din`
223			`);`
224			`end generate fifo_cc_2;`
225
226
227
228			`fifo_cc_3: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 3 ) generate`
229			`U_fifo_cc : fifo_adr_cc_3`
230			`port map(`
231			`rd_en => rd_en,`
232			`wr_en => wr_en,`
233			`full => full,`
234			`empty => empty,`
235			`clk => rd_clk, -- rd_clk must be the same than wr_clk!`
236			`rst => rst,`
237			`dout => dout,`
238			`din => din`
239			`);`
240			`end generate fifo_cc_3;`
241
242
243
244			`fifo_cc_4: if ( SYNCHRONY = true and C_SPLB_MID_WIDTH = 4 ) generate`
245			`U_fifo_cc : fifo_adr_cc_4`
246			`port map(`
247			`rd_en => rd_en,`
248			`wr_en => wr_en,`
249			`full => full,`
250			`empty => empty,`
251			`clk => rd_clk, -- rd_clk must be the same than wr_clk!`
252			`rst => rst,`
253			`dout => dout,`
254			`din => din`
255			`);`
256			`end generate fifo_cc_4;`
257
258
259
260			`fifo_ic_1: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 1 ) generate`
261			`U_fifo_ic : fifo_adr_ic_1`
262			`port map(`
263			`rd_en => rd_en,`
264			`wr_en => wr_en,`
265			`full => full,`
266			`empty => empty,`
267			`rd_clk => rd_clk,`
268			`wr_clk => wr_clk,`
269			`rst => rst,`
270			`dout => dout,`
271			`din => din`
272			`);`
273			`end generate fifo_ic_1;`
274
275
276			`fifo_ic_2: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 2 ) generate`
277			`U_fifo_ic : fifo_adr_ic_2`
278			`port map(`
279			`rd_en => rd_en,`
280			`wr_en => wr_en,`
281			`full => full,`
282			`empty => empty,`
283			`rd_clk => rd_clk,`
284			`wr_clk => wr_clk,`
285			`rst => rst,`
286			`dout => dout,`
287			`din => din`
288			`);`
289			`end generate fifo_ic_2;`
290
291
292			`fifo_ic_3: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 3 ) generate`
293			`U_fifo_ic : fifo_adr_ic_3`
294			`port map(`
295			`rd_en => rd_en,`
296			`wr_en => wr_en,`
297			`full => full,`
298			`empty => empty,`
299			`rd_clk => rd_clk,`
300			`wr_clk => wr_clk,`
301			`rst => rst,`
302			`dout => dout,`
303			`din => din`
304			`);`
305			`end generate fifo_ic_3;`
306
307
308			`fifo_ic_4: if ( SYNCHRONY = false and C_SPLB_MID_WIDTH = 4 ) generate`
309			`U_fifo_ic : fifo_adr_ic_4`
310			`port map(`
311			`rd_en => rd_en,`
312			`wr_en => wr_en,`
313			`full => full,`
314			`empty => empty,`
315			`rd_clk => rd_clk,`
316			`wr_clk => wr_clk,`
317			`rst => rst,`
318			`dout => dout,`
319			`din => din`
320			`);`
321			`end generate fifo_ic_4;`
322
323
324
325
326			`end architecture IMP;`