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feddischso |
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---- ----
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---- PLB2WB-Bridge ----
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---- ----
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---- This file is part of the PLB-to-WB-Bridge project ----
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---- http://opencores.org/project,plb2wbbridge ----
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---- ----
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---- Description ----
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---- Implementation of a PLB-to-WB-Bridge according to ----
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---- PLB-to-WB Bridge specification document. ----
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---- ----
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---- To Do: ----
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---- Nothing ----
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---- ----
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---- Author(s): ----
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---- - Christian Haettich ----
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---- feddischson@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2010 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library plb2wb_bridge_v1_00_a;
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use plb2wb_bridge_v1_00_a.plb2wb_pkg.all;
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entity fifo_stat2wb is
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generic
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(
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SYNCHRONY : boolean := true -- true = synchron
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);
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port(
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rd_en : in std_logic := 'X';
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wr_en : in std_logic := 'X';
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full : out std_logic;
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empty : out std_logic;
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wr_clk : in std_logic := 'X';
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rst : in std_logic := 'X';
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rd_clk : in std_logic := 'X';
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dout : out std_logic_vector ( 1 -1 downto 0 );
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din : in std_logic_vector ( 1 -1 downto 0 )
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);
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end entity fifo_stat2wb;
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architecture IMP of fifo_stat2wb is
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component fifo_stat2wb_cc is
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port (
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rd_en : in STD_LOGIC := 'X';
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wr_en : in STD_LOGIC := 'X';
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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clk : in STD_LOGIC := 'X';
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rst : in STD_LOGIC := 'X';
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dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
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din : in STD_LOGIC_VECTOR ( 0 downto 0 )
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);
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end component fifo_stat2wb_cc;
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component fifo_stat2wb_ic is
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port (
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rd_en : in STD_LOGIC := 'X';
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wr_en : in STD_LOGIC := 'X';
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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wr_clk : in STD_LOGIC := 'X';
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rst : in STD_LOGIC := 'X';
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rd_clk : in STD_LOGIC := 'X';
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dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
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din : in STD_LOGIC_VECTOR ( 0 downto 0 )
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);
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end component fifo_stat2wb_ic;
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begin
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fifo1: if ( SYNCHRONY = true ) generate
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U_fifo_cc : fifo_stat2wb_cc
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port map(
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rd_en => rd_en,
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wr_en => wr_en,
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full => full,
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empty => empty,
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clk => rd_clk, -- rd_clk must be the same than wr_clk
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rst => rst,
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dout => dout,
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din => din
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);
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end generate fifo1;
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fifo2: if ( SYNCHRONY = false ) generate
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U_fifo_ic : fifo_stat2wb_ic
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port map(
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rd_en => rd_en,
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wr_en => wr_en,
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full => full,
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empty => empty,
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rd_clk => rd_clk,
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wr_clk => wr_clk,
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rst => rst,
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dout => dout,
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din => din
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);
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end generate fifo2;
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end architecture IMP;
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