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feddischso |
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---- ----
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---- PLB2WB-Bridge ----
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---- ----
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---- This file is part of the PLB-to-WB-Bridge project ----
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---- http://opencores.org/project,plb2wbbridge ----
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---- ----
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---- Description ----
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---- Implementation of a PLB-to-WB-Bridge according to ----
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---- PLB-to-WB Bridge specification document. ----
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---- ----
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---- To Do: ----
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---- Nothing ----
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---- ----
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---- Author(s): ----
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---- - Christian Haettich ----
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---- feddischson@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2010 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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library plb2wb_bridge_v1_00_a;
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entity plb2wb_rbuf is
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generic(
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SYNCHRONY : boolean := true;
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WB_DWIDTH : integer := 32
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);
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port(
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wb_clk_i : IN std_logic;
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SPLB_Clk : IN std_logic;
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plb2wb_rst : IN std_logic;
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wb_dat_i : IN std_logic_vector( WB_DWIDTH-1 downto 0 );
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RBF_rBus : out std_logic_vector( WB_DWIDTH-1 downto 0 );
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RBF_empty : out std_logic;
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RBF_almostEmpty : out std_logic;
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RBF_full : out std_logic;
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RBF_rdErrOut : out std_logic;
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RBF_rdErrIn : in std_logic;
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TCU_rbufWEn : in std_logic;
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TCU_rbufREn : in std_logic
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);
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end entity plb2wb_rbuf;
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architecture IMP_32 of plb2wb_rbuf is
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signal rbuf_dout : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
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signal rbuf_din : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
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signal pre_load_reg : std_logic_vector( WB_DWIDTH+1-1 downto 0 );
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signal rd_en : std_logic;
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begin
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rbuf_din <= RBF_rdErrIn & wb_dat_i;
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rd_en <= TCU_rbufREn;
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RBF_rBus <= rbuf_dout( WB_DWIDTH-1 downto 0 );
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RBF_rdErrOut <= rbuf_dout(32);
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rbuf : entity plb2wb_bridge_v1_00_a.fifo_rdat( IMP )
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generic map(
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SYNCHRONY => SYNCHRONY,
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WB_DWIDTH => WB_DWIDTH
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)
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port map(
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rd_en => rd_en,
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wr_en => TCU_rbufWEn,
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full => RBF_full,
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empty => RBF_empty,
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almost_empty => RBF_almostEmpty,
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wr_clk => wb_clk_i,
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rst => plb2wb_rst,
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rd_clk => SPLB_Clk,
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dout => rbuf_dout,
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din => rbuf_din
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);
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end architecture IMP_32;
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