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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [plb2wb_bridge_v1_00_a/] [hdl/] [vhdl/] [plb2wb_short_impulse.vhd] - Blame information for rev 2

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----------------------------------------------------------------------
----                                                              ----
----  PLB2WB-Bridge                                               ----
----                                                              ----
----  This file is part of the PLB-to-WB-Bridge project           ----
----  http://opencores.org/project,plb2wbbridge                   ----
----                                                              ----
----  Description                                                 ----
----  Implementation of a PLB-to-WB-Bridge according to           ----
----  PLB-to-WB Bridge specification document.                    ----
----                                                              ----
----  To Do:                                                      ----
----   Nothing                                                    ----
----                                                              ----
----  Author(s):                                                  ----
----      - Christian Haettich                                    ----
----        feddischson@opencores.org                             ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2010 Authors                                   ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE.  See the GNU Lesser General Public License for more ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity plb2wb_short_impulse is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
           IMPULSE : in  STD_LOGIC;
           SHORT_IMPULSE : out  STD_LOGIC);
end plb2wb_short_impulse;
 
architecture IMP of plb2wb_short_impulse is
 
 
type state is record
   was_down       : std_logic;
   start_of_high  : std_logic;
end record;
 
signal current_state, next_state : state;
 
begin
 
states_state : process( CLK, RESET )
 
   begin
        if CLK'event and CLK='1' then
 
           if RESET = '1' then
 
              current_state <= (   was_down       => '0',
                                   start_of_high  => '0' );
 
           else
               current_state <= next_state;
           end if;
 
        end if;
   end process;
 
 
 
detection : process( current_state, IMPULSE )
   begin
 
      next_state                 <= current_state;
      next_state.start_of_high   <= '0';
      SHORT_IMPULSE              <= '0';
 
      if current_state.was_down = '1' and IMPULSE = '1' then
         next_state.was_down        <= '0';
         next_State.start_of_high   <= '1';
         SHORT_IMPULSE              <= '1';
      end if;
 
      if current_state.was_down = '0' and IMPULSE = '0' then
         next_state.was_down        <= '1';
      end if;
 
   end process;
 
 
 
end IMP;
 

Line No.	Rev	Author	Line
1	2	feddischso	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- PLB2WB-Bridge ----`
4			`---- ----`
5			`---- This file is part of the PLB-to-WB-Bridge project ----`
6			`---- http://opencores.org/project,plb2wbbridge ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Implementation of a PLB-to-WB-Bridge according to ----`
10			`---- PLB-to-WB Bridge specification document. ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- Nothing ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Christian Haettich ----`
17			`---- feddischson@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2010 Authors ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45
46
47			`library IEEE;`
48			`use IEEE.STD_LOGIC_1164.ALL;`
49			`use IEEE.STD_LOGIC_ARITH.ALL;`
50			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
51
52
53			`entity plb2wb_short_impulse is`
54			`Port ( CLK : in STD_LOGIC;`
55			`RESET : in STD_LOGIC;`
56			`IMPULSE : in STD_LOGIC;`
57			`SHORT_IMPULSE : out STD_LOGIC);`
58			`end plb2wb_short_impulse;`
59
60			`architecture IMP of plb2wb_short_impulse is`
61
62
63			`type state is record`
64			`was_down : std_logic;`
65			`start_of_high : std_logic;`
66			`end record;`
67
68			`signal current_state, next_state : state;`
69
70			`begin`
71
72			`states_state : process( CLK, RESET )`
73
74			`begin`
75			`if CLK'event and CLK='1' then`
76
77			`if RESET = '1' then`
78
79			`current_state <= ( was_down => '0',`
80			`start_of_high => '0' );`
81
82			`else`
83			`current_state <= next_state;`
84			`end if;`
85
86			`end if;`
87			`end process;`
88
89
90
91			`detection : process( current_state, IMPULSE )`
92			`begin`
93
94			`next_state <= current_state;`
95			`next_state.start_of_high <= '0';`
96			`SHORT_IMPULSE <= '0';`
97
98			`if current_state.was_down = '1' and IMPULSE = '1' then`
99			`next_state.was_down <= '0';`
100			`next_State.start_of_high <= '1';`
101			`SHORT_IMPULSE <= '1';`
102			`end if;`
103
104			`if current_state.was_down = '0' and IMPULSE = '0' then`
105			`next_state.was_down <= '1';`
106			`end if;`
107
108			`end process;`
109
110
111
112			`end IMP;`
113

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[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [plb2wb_bridge_v1_00_a/] [hdl/] [vhdl/] [plb2wb_short_impulse.vhd] - Blame information for rev 2