| 1 |
2 |
feddischso |
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| 2 |
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CUR_DIR=$(shell pwd)
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| 3 |
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SIM_DIR=$(CUR_DIR)/..
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| 4 |
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XPS_PROJ_DIR=$(CUR_DIR)/../..
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| 5 |
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LIB_DIR=$(CUR_DIR)/../../../EDK_Libs
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| 6 |
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| 7 |
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PLB2WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a
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| 8 |
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OCRAM_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/testram_v1_00_a
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| 9 |
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WB_LIB_DIR=$(LIB_DIR)/WishboneIPLib/pcores/wb_conbus_v1_00_a
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| 10 |
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| 11 |
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# VHDL compile flags
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| 12 |
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VHDL_CFLAGS=-novopt -93 -error -check_synthesis -defercheck -deferSubpgmCheck -rangecheck
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| 14 |
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## Uncomment this, if you are at hochschule pforzheim in a pc-pool.
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| 15 |
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# (Check the paths in common/Makefile ->> vmap entries)
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| 16 |
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#ENVIRONMENT=HSP
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| 18 |
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| 19 |
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ifeq ( $(ENVIRONMENT), "HSP" )
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| 20 |
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VMAP= \
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| 21 |
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vmap -c; \
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| 22 |
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vmap secureip 'c:/Programme/CAEE/ISE_Lib/secureip/'; \
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| 23 |
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vmap simprim 'c:/Programme/CAEE/ISE_Lib/simprim/'; \
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| 24 |
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vmap simprims_ver 'c:/Programme/CAEE/ISE_Lib/simprims_ver/'; \
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| 25 |
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vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/'; \
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| 26 |
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vmap unisims_ver 'c:/Programme/CAEE/ISE_Lib/unisims_ver/'; \
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| 27 |
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vmap xilinxcorelib 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib/'; \
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| 28 |
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vmap xilinxcorelib_ver 'c:/Programme/CAEE/ISE_Lib/XilinxCoreLib_ver/'; \
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| 29 |
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vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/'; \
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| 30 |
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vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/edk/plb_v46_v1_04_a/'; \
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| 31 |
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vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/bfm_synch_v1_00_a/'; \
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| 32 |
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vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/'; \
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| 33 |
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vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/'; \
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vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/'; \
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vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/'; \
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vmap plbv46_slave_single_v1_01_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_single_v1_01_a/';
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| 37 |
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| 38 |
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else
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| 39 |
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VMAP= \
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vmap -c; \
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| 41 |
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vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/'; \
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| 42 |
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vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/'; \
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| 43 |
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vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/'; \
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| 44 |
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vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/'; \
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| 45 |
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vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/'; \
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| 46 |
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vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/'; \
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| 47 |
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vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/'; \
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| 48 |
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vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/'; \
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| 49 |
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vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/'; \
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| 50 |
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vlib work; \
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| 51 |
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vmap work work; \
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| 52 |
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vlib plb2wb_bridge_v1_00_a; \
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| 53 |
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vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
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| 54 |
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endif
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| 55 |
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| 56 |
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| 57 |
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###########
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| 58 |
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ONCHIP_RAM_TARGET=$(CUR_DIR)/testram_*/testram/_primary.dat
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| 59 |
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WB_TARGET=$(CUR_DIR)/wb_conbus_*/wb_conbus_*/_primary.dat
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| 60 |
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WORK_TARGET=$(CUR_DIR)/work/system/_primary.dat
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| 61 |
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PLB2WB_BRIDGE_TARGET=$(CUR_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat
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| 62 |
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###########
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| 63 |
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| 64 |
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| 65 |
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| 66 |
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###########
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| 67 |
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PLB2WB_BRIDGE_SRC=$(PLB2WB_LIB_DIR)/hdl/vhdl/*.vhd \
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| 68 |
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../testbench/plb2wb_amu_tb.vhd
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| 69 |
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| 70 |
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ONCHIP_RAM_SRC=$(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
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| 71 |
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WB_SRC=$(WB_LIB_DIR)/hdl/verilog/*.v
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| 72 |
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###########
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| 73 |
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| 74 |
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| 75 |
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| 76 |
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| 77 |
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| 78 |
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WORK_SRC= $(SIM_DIR)/behavioral/mb_plb_wrapper.vhd \
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| 79 |
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$(SIM_DIR)/behavioral/plb_bfm_master_32_wrapper.vhd \
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| 80 |
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$(SIM_DIR)/behavioral/plb_bfm_monitor_wrapper.vhd \
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| 81 |
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$(SIM_DIR)/behavioral/plb_bfm_slave_wrapper.vhd \
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| 82 |
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$(SIM_DIR)/behavioral/plb_bfm_synch_wrapper.vhd \
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| 83 |
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$(SIM_DIR)/behavioral/system.vhd \
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| 84 |
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$(SIM_DIR)/testbench/system_tb.vhd
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| 85 |
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| 86 |
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VHDL_BRIDGE_SRC=$(SIM_DIR)/behavioral/plb2wb_bridge_0_wrapper.vhd
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| 87 |
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| 88 |
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| 89 |
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#
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| 90 |
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# Generate Simulation HDL Files
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| 91 |
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# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)
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| 92 |
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#
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| 93 |
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$(WORK_SRC): $(XPS_PROJ_DIR)/system.mhs
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| 94 |
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simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \
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| 95 |
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-p virtex5 \
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| 96 |
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-m beh \
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| 97 |
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-od $(XPS_PROJ_DIR)/ \
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| 98 |
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-s mti \
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| 99 |
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-lp $(LIB_DIR)
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| 100 |
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| 101 |
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#
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| 102 |
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#
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| 103 |
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# Generate the modelsim.ini file and working directory
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| 104 |
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# after this, modelsim.ini contains the library mappings
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| 105 |
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#
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| 106 |
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modelsim.ini:
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| 107 |
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$(VMAP)
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| 108 |
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| 109 |
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| 110 |
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| 111 |
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#
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| 112 |
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# Compile the Bus Functional Model script file
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| 113 |
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# transfers.bfl: is written in PLB Bus Functional Language
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| 114 |
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# (see $XILINX_EDK/third_party/doc/PlbToolkit.pdf )
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| 115 |
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# xilbfc: Bus functional compiler (perl script)
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| 116 |
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#
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| 117 |
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|
| 118 |
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transfers.do: transfers.bfl
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| 119 |
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xilbfc transfers.bfl
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| 120 |
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| 121 |
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#
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| 122 |
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# Compile the vhdl-sources with modelsim vhdl compiler
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| 123 |
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#
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| 124 |
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$(WORK_TARGET): $(WORK_SRC)
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| 125 |
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vlib work; \
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| 126 |
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vmap work work; \
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| 127 |
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vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \
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| 128 |
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vcom $(VHDL_CFLAGS) -work work \
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| 129 |
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"../behavioral/onchip_ram_0_wrapper.vhd" \
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| 130 |
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"../behavioral/onchip_ram_1_wrapper.vhd" \
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| 131 |
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"../behavioral/onchip_ram_2_wrapper.vhd" \
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| 132 |
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"../behavioral/onchip_ram_3_wrapper.vhd" \
|
| 133 |
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"../behavioral/mb_plb_wrapper.vhd" \
|
| 134 |
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"../behavioral/plb_bfm_master_32_wrapper.vhd" \
|
| 135 |
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"../behavioral/plb_bfm_master_64_wrapper.vhd" \
|
| 136 |
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"../behavioral/plb_bfm_master_128_wrapper.vhd" \
|
| 137 |
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"../behavioral/plb_bfm_monitor_wrapper.vhd" \
|
| 138 |
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"../behavioral/plb_bfm_slave_wrapper.vhd" \
|
| 139 |
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"../behavioral/plb_bfm_synch_wrapper.vhd" \
|
| 140 |
|
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"../behavioral/plb2wb_bridge_0_wrapper.vhd" \
|
| 141 |
|
|
"../behavioral/system.vhd" \
|
| 142 |
|
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"../testbench/system_tb.vhd"
|
| 143 |
|
|
|
| 144 |
|
|
|
| 145 |
|
|
$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)
|
| 146 |
|
|
vlib plb2wb_bridge_v1_00_a;
|
| 147 |
|
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vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
|
| 148 |
|
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vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a \
|
| 149 |
|
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"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_pkg.vhd" \
|
| 150 |
|
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"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_short_impulse.vhd" \
|
| 151 |
|
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"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_4.vhd" \
|
| 152 |
|
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"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_4.vhd" \
|
| 153 |
|
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"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_3.vhd" \
|
| 154 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_3.vhd" \
|
| 155 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_2.vhd" \
|
| 156 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_2.vhd" \
|
| 157 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_cc_1.vhd" \
|
| 158 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr_ic_1.vhd" \
|
| 159 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_adr.vhd" \
|
| 160 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_cc_32.vhd" \
|
| 161 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat_ic_32.vhd" \
|
| 162 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_rdat.vhd" \
|
| 163 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_cc_32.vhd" \
|
| 164 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat_ic_32.vhd" \
|
| 165 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_wdat.vhd" \
|
| 166 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb.vhd" \
|
| 167 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_4.vhd" \
|
| 168 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_4.vhd" \
|
| 169 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_3.vhd" \
|
| 170 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_3.vhd" \
|
| 171 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_2.vhd" \
|
| 172 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_2.vhd" \
|
| 173 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_ic_1.vhd" \
|
| 174 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2plb_cc_1.vhd" \
|
| 175 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb.vhd" \
|
| 176 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_ic.vhd" \
|
| 177 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/fifo_stat2wb_cc.vhd" \
|
| 178 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_fifo.vhd" \
|
| 179 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_stu.vhd" \
|
| 180 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_tcu.vhd" \
|
| 181 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_amu.vhd" \
|
| 182 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_rbuf.vhd" \
|
| 183 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_wbuf.vhd" \
|
| 184 |
|
|
"$(PLB2WB_LIB_DIR)/hdl/vhdl/plb2wb_bridge.vhd"
|
| 185 |
|
|
|
| 186 |
|
|
|
| 187 |
|
|
|
| 188 |
|
|
$(ONCHIP_RAM_TARGET): $(ONCHIP_RAM_SRC)
|
| 189 |
|
|
vlib testram_v1_00_a;
|
| 190 |
|
|
vmap testram_v1_00_a testram_v1_00_a;
|
| 191 |
|
|
vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(OCRAM_LIB_DIR)/hdl/vhdl/testram.vhd
|
| 192 |
|
|
|
| 193 |
|
|
|
| 194 |
|
|
$(WB_TARGET): $(WB_SRC)
|
| 195 |
|
|
vlib wb_conbus_v1_00_a;
|
| 196 |
|
|
vmap wb_conbus_v1_00_a wb_conbus_v1_00_a;
|
| 197 |
|
|
vlog -novopt -93 -work wb_conbus_v1_00_a "$(WB_LIB_DIR)/hdl/verilog/wb_conbus_arb.v" \
|
| 198 |
|
|
"$(WB_LIB_DIR)/hdl/verilog/wb_conbus_top.v" \
|
| 199 |
|
|
"$(WB_LIB_DIR)/hdl/verilog/wb_conbus_wrapper.v"
|
| 200 |
|
|
|
| 201 |
|
|
|
| 202 |
|
|
|
| 203 |
|
|
compile: modelsim.ini $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
|
| 204 |
|
|
|
| 205 |
|
|
sim: modelsim.ini transfers.do $(ONCHIP_RAM_TARGET) $(WORK_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET)
|
| 206 |
|
|
vsim -quiet -l simulation.log -do sim.do
|
| 207 |
|
|
|
| 208 |
|
|
|
| 209 |
|
|
sim_fifo: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
| 210 |
|
|
vsim -quiet -do sim_fifo.do
|
| 211 |
|
|
|
| 212 |
|
|
sim_amu : ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
| 213 |
|
|
vsim -quiet -do sim_amu.do
|
| 214 |
|
|
|
| 215 |
|
|
sim_clk_trans: ./plb2wb_bridge_*/plb2wb_bridge/_primary.dat
|
| 216 |
|
|
vsim -quiet -do sim_clk_trans.do
|
| 217 |
|
|
|
| 218 |
|
|
clean:
|
| 219 |
|
|
rm -rf work \
|
| 220 |
|
|
simgen.log \
|
| 221 |
|
|
simgen.opt \
|
| 222 |
|
|
transcript \
|
| 223 |
|
|
vsim.wlf \
|
| 224 |
|
|
modelsim.ini \
|
| 225 |
|
|
../behavioral \
|
| 226 |
|
|
xilbfc.log \
|
| 227 |
|
|
plb2wb_bridge_v1_00_a \
|
| 228 |
|
|
wb_conbus_v1_00_a \
|
| 229 |
|
|
testram_v1_00_a \
|
| 230 |
|
|
wb_conbus_v1_00_a \
|
| 231 |
|
|
bfm_synch_v1_00_a \
|
| 232 |
|
|
plb_v46_v1_04_a \
|
| 233 |
|
|
plbv46_bfm \
|
| 234 |
|
|
plbv46_master_bfm_v1_00_a \
|
| 235 |
|
|
plbv46_monitor_bfm_v1_00_a \
|
| 236 |
|
|
plbv46_slave_bfm_v1_00_a \
|
| 237 |
|
|
plbv46_slave_single_v1_01_a \
|
| 238 |
|
|
proc_common_v3_00_a \
|
| 239 |
|
|
modelsim_proj.cr.mti \
|
| 240 |
|
|
transfers.do
|
