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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [Makefile] - Blame information for rev 2

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Line No. Rev Author Line
1 2 feddischso 
CUR_DIR=$(shell pwd)
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# IP-Library
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LIB_DIR=$(CUR_DIR)/../EDK_Libs
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# Wishbone Library
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WISHBONE_LIB_DIR=$(LIB_DIR)/WishboneIPLib
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# VHDL compile flags
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VHDL_CFLAGS="-novopt -93 -error -check_synthesis -defercheck -deferSubpgmCheck -rangecheck "
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# not used at the moment
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#PLB_BFM_LIB_DIR=/opt/Xilinx/11.1/EDK/hw/XilinxBFMinterface
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## Uncomment this, if you are using cygwin in a windows environment
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#  (Check the paths in common/Makefile  ->> vmap entries)
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#ENVIRONMENT="cygwin"
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all: sim assert.log simulation.log error.log
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.PHONY: sim assert.log simulation.log error.log
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newsim: cleansim sim
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sim: t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
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TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write"
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TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw"
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TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw"
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TEST_CASES+="32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write"
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TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write"
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TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw"
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TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw"
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TEST_CASES+="32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write"
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TEST_CASES+="wb_retries/simulation/test_cases/simple_retries"
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TEST_CASES+="wb_err_and_rst/simulation/test_cases/errors_and_rst"
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TEST_CASES+="wb_err_and_rst/simulation/test_cases/timeouts"
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TEST_CASES+="wb_irqs/simulation/test_cases/irq_tests"
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TEST_CASES+="simple/simulation/test_cases/stressful_read_write"
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t1:
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        $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t2:
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        $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_line_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t3:
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        $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/simple_burst_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t4:
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        $(MAKE) -C "32bit_on_128bitPLB_syn/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t5:
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        $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t6:
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        $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_line_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t7:
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        $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/simple_burst_rw" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t8:
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        $(MAKE) -C "32bit_on_128bitPLB_asyn/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t9:
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        $(MAKE) -C "wb_retries/simulation/test_cases/simple_retries" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t10:
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        $(MAKE) -C "wb_err_and_rst/simulation/test_cases/errors_and_rst" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t11:
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        $(MAKE) -C "wb_err_and_rst/simulation/test_cases/timeouts" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t12:
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        $(MAKE) -C "wb_irqs/simulation/test_cases/irq_tests" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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t13:
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        $(MAKE) -C "simple/simulation/test_cases/stressful_read_write" sim LIB_DIR=$(LIB_DIR) WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) PLB_BFM_LIB_DIR=$(PLB_BFM_LIB_DIR) VHDL_CFLAGS=$(VHDL_CFLAGS);
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compile:
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        $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_syn/simulation compile LIB_DIR=$(LIB_DIR)   WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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        $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_asyn/simulation compile LIB_DIR=$(LIB_DIR)  WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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        $(MAKE) -C $(CUR_DIR)/wb_retries/simulation compile LIB_DIR=$(LIB_DIR)  WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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        $(MAKE) -C $(CUR_DIR)/wb_err_and_rst/simulation compile LIB_DIR=$(LIB_DIR)  WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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        $(MAKE) -C $(CUR_DIR)/wb_irqs/simulation compile LIB_DIR=$(LIB_DIR)  WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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        $(MAKE) -C $(CUR_DIR)/simple/simulation compile LIB_DIR=$(LIB_DIR)  WISHBONE_LIB_DIR=$(WISHBONE_LIB_DIR) ENVIRONMENT=$(ENVIRONMENT) VHDL_CFLAGS=$(VHDL_CFLAGS);
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clean:
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        $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_syn/simulation         clean
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        $(MAKE) -C $(CUR_DIR)/32bit_on_128bitPLB_asyn/simulation        clean
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        $(MAKE) -C $(CUR_DIR)/wb_retries/simulation                                     clean
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        $(MAKE) -C $(CUR_DIR)/wb_err_and_rst/simulation                         clean
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        $(MAKE) -C $(CUR_DIR)/wb_irqs/simulation                                                clean
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        $(MAKE) -C $(CUR_DIR)/simple/simulation                                         clean
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        @for i in $(TEST_CASES); do \
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                $(MAKE) -C $$i clean;   \
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        done;
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cleansim:
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        @for i in $(TEST_CASES); do \
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                $(MAKE) -C $$i clean;   \
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        done;
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        rm -rf error.log assert.log simulation.log
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simulation.log: sim
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        @rm -rf simulation.log
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        @for i in $(TEST_CASES); do \
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        echo "------------------------------------------------------" >> simulation.log; \
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        echo "----  $$i  ----" >> simulation.log; \
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        echo "------------------------------------------------------" >> simulation.log; \
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        cat $$i/result/simulation.log >> simulation.log;        \
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        done;
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error.log: sim
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        @rm -rf error.log
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        @for i in $(TEST_CASES); do \
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        echo "------------------------------------------------------" >> error.log; \
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        echo "----  $$i  ----" >> error.log; \
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        echo "------------------------------------------------------" >> error.log; \
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        cat $$i/result/error.log >> error.log;  \
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        done;
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assert.log: sim
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        @rm -rf assert.log
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        @for i in $(TEST_CASES); do \
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        echo "------------------------------------------------------" >> assert.log; \
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        echo "----  $$i  ----" >> assert.log; \
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        echo "------------------------------------------------------" >> assert.log; \
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        cat $$i/result/assert.log >> assert.log;        \
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        done;
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