URL https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [common/] [Makefile] - Blame information for rev 2

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WB_SRC=$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/*.v
TESTRAM_SRC=$(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd
PLB2WB_BRIDGE_SRC=$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/*.vhd
 
 
PLB2WB_BRIDGE_TARGET=$(SIM_BIN_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat
TESTRAM_TARGET=$(SIM_BIN_DIR)/testram_*/testram/_primary.dat
WB_TARGET=$(SIM_BIN_DIR)/wb_conbus_*/wb_conbus_*/_primary.dat
 
 
 
 
VMAP_WIN=                                                                                                                                                                                                                                               \
        vmap -c;                                                                                                                                                                                                                                        \
        vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/';                                                                                                                        \
        vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/bfm_synch_v1_00_a/';                                                  \
        vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/plb_v46_v1_00_a/';                                                              \
        vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/';                                                                                    \
        vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/';      \
        vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/';    \
        vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/';                \
        vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/';                                  \
        vlib work;                                                                                                                                                                                                                              \
        vmap work work;                                                                                                                                                                                                         \
        vlib plb2wb_bridge_v1_00_a;                                                                                                                                                                             \
        vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
 
VMAP=                                                                                                                                                                                                                                           \
        vmap -c;                                                                                                                                                                                                                                        \
        vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/';                                                                                                                      \
        vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/';                                                                                                                        \
        vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/';                                                      \
        vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/';                                                          \
        vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/';                                                                                    \
        vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/';      \
        vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/';    \
        vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/';                \
        vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/';                                  \
        vlib work;                                                                                                                                                                                                                              \
        vmap work work;                                                                                                                                                                                                         \
        vlib plb2wb_bridge_v1_00_a;                                                                                                                                                                             \
        vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;
 
 
 
 
 
###
#
#       Generate the modelsim.ini file and working directory
#               after this, modelsim.ini contains the library mappings
#
$(SIM_BIN_DIR)/modelsim.ini:
        @mkdir -p $(SIM_BIN_DIR)
        @echo " "
        @if [ "$(ENVIRONMENT)" = "cygwin" ]; then       \
                cd $(SIM_BIN_DIR); $(VMAP_WIN)                  \
        else                                                                                                    \
                cd $(SIM_BIN_DIR); $(VMAP)                                      \
        fi
        @echo " "
        @echo " "
 
 
 
 
 
 
###
#
# Compile testram
#
$(TESTRAM_TARGET):  $(TESTRAM_SRC)
        cd $(SIM_BIN_DIR);      \
        vlib testram_v1_00_a; \
        vmap testram_v1_00_a testram_v1_00_a; \
        vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd
 
 
###
#
# Compile Wishbone-BUS
#
$(WB_TARGET): $(WB_SRC)
        cd $(SIM_BIN_DIR);      \
        vlib wb_conbus_v1_00_a; \
        vmap wb_conbus_v1_00_a wb_conbus_v1_00_a; \
        vlog -novopt -93 -work wb_conbus_v1_00_a "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v"       \
                                              "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v"       \
                                           "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v"
 
 
 
###
#
# Compile PLB2WB-Bridge
#
$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)
        echo "VHDL-Flags: $(VHDL_CFLAGS)"
        cd $(SIM_BIN_DIR); \
        vlib plb2wb_bridge_v1_00_a;     \
        vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;\
        vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a                                                                                                                 \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd"                              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd"                            \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_4.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_4.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_3.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_3.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_2.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_2.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_1.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_1.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd"                                \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_cc_32.vhd"                         \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_ic_32.vhd"                         \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd"                               \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_cc_32.vhd"                         \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_ic_32.vhd"                         \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd"                               \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd"                           \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_4.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_4.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_3.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_3.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_2.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_2.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_1.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_1.vhd"              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd"                            \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_ic.vhd"                 \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_cc.vhd"                 \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd"                             \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd"                              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd"                              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd"                              \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd"                             \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd"                             \
        "$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd"
 
 
 
 

Line No.	Rev	Author	Line
1	2	feddischso	`WB_SRC=$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/*.v`
2			`TESTRAM_SRC=$(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd`
3			`PLB2WB_BRIDGE_SRC=$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/*.vhd`
4
5
6			`PLB2WB_BRIDGE_TARGET=$(SIM_BIN_DIR)/plb2wb_bridge_*/plb2wb_bridge/_primary.dat`
7			`TESTRAM_TARGET=$(SIM_BIN_DIR)/testram_*/testram/_primary.dat`
8			`WB_TARGET=$(SIM_BIN_DIR)/wb_conbus_/wb_conbus_/_primary.dat`
9
10
11
12
13			`VMAP_WIN= \`
14			`vmap -c; \`
15			`vmap unisim 'c:/Programme/CAEE/ISE_Lib/unisim/'; \`
16			`vmap bfm_synch_v1_00_a 'c:/Programme/CAEE/EDK_Lib/bfm_synch_v1_00_a/'; \`
17			`vmap plb_v46_v1_04_a 'c:/Programme/CAEE/EDK_Lib/plb_v46_v1_00_a/'; \`
18			`vmap plbv46_bfm 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_bfm/'; \`
19			`vmap plbv46_master_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_master_bfm_v1_00_a/'; \`
20			`vmap plbv46_monitor_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_monitor_bfm_v1_00_a/'; \`
21			`vmap plbv46_slave_bfm_v1_00_a 'c:/Programme/CAEE/EDK_Lib/edk/plbv46_slave_bfm_v1_00_a/'; \`
22			`vmap proc_common_v3_00_a 'c:/Programme/CAEE/EDK_Lib/edk/proc_common_v3_00_a/'; \`
23			`vlib work; \`
24			`vmap work work; \`
25			`vlib plb2wb_bridge_v1_00_a; \`
26			`vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;`
27
28			`VMAP= \`
29			`vmap -c; \`
30			`vmap unisims_ver '/opt/Xilinx/11.1/compxlib/unisims_ver/'; \`
31			`vmap unisim '/opt/Xilinx/11.1/compxlib/unisim/'; \`
32			`vmap bfm_synch_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/bfm_synch_v1_00_a/'; \`
33			`vmap plb_v46_v1_04_a '/opt/Xilinx/11.1/compxlib/edk/plb_v46_v1_04_a/'; \`
34			`vmap plbv46_bfm '/opt/Xilinx/11.1/compxlib/edk/plbv46_bfm/'; \`
35			`vmap plbv46_master_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_master_bfm_v1_00_a/'; \`
36			`vmap plbv46_monitor_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_monitor_bfm_v1_00_a/'; \`
37			`vmap plbv46_slave_bfm_v1_00_a '/opt/Xilinx/11.1/compxlib/edk/plbv46_slave_bfm_v1_00_a/'; \`
38			`vmap proc_common_v3_00_a '/opt/Xilinx/11.1/compxlib/edk/proc_common_v3_00_a/'; \`
39			`vlib work; \`
40			`vmap work work; \`
41			`vlib plb2wb_bridge_v1_00_a; \`
42			`vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;`
43
44
45
46
47
48			`###`
49			`#`
50			`# Generate the modelsim.ini file and working directory`
51			`# after this, modelsim.ini contains the library mappings`
52			`#`
53			`$(SIM_BIN_DIR)/modelsim.ini:`
54			`@mkdir -p $(SIM_BIN_DIR)`
55			`@echo " "`
56			`@if [ "$(ENVIRONMENT)" = "cygwin" ]; then \`
57			`cd $(SIM_BIN_DIR); $(VMAP_WIN) \`
58			`else \`
59			`cd $(SIM_BIN_DIR); $(VMAP) \`
60			`fi`
61			`@echo " "`
62			`@echo " "`
63
64
65
66
67
68
69			`###`
70			`#`
71			`# Compile testram`
72			`#`
73			`$(TESTRAM_TARGET): $(TESTRAM_SRC)`
74			`cd $(SIM_BIN_DIR); \`
75			`vlib testram_v1_00_a; \`
76			`vmap testram_v1_00_a testram_v1_00_a; \`
77			`vcom $(VHDL_CFLAGS) -work testram_v1_00_a $(WISHBONE_LIB_DIR)/pcores/testram_v1_00_a/hdl/vhdl/testram.vhd`
78
79
80			`###`
81			`#`
82			`# Compile Wishbone-BUS`
83			`#`
84			`$(WB_TARGET): $(WB_SRC)`
85			`cd $(SIM_BIN_DIR); \`
86			`vlib wb_conbus_v1_00_a; \`
87			`vmap wb_conbus_v1_00_a wb_conbus_v1_00_a; \`
88			`vlog -novopt -93 -work wb_conbus_v1_00_a "$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_arb.v" \`
89			`"$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_top.v" \`
90			`"$(WISHBONE_LIB_DIR)/pcores/wb_conbus_v1_00_a/hdl/verilog/wb_conbus_wrapper.v"`
91
92
93
94			`###`
95			`#`
96			`# Compile PLB2WB-Bridge`
97			`#`
98			`$(PLB2WB_BRIDGE_TARGET): $(PLB2WB_BRIDGE_SRC)`
99			`echo "VHDL-Flags: $(VHDL_CFLAGS)"`
100			`cd $(SIM_BIN_DIR); \`
101			`vlib plb2wb_bridge_v1_00_a; \`
102			`vmap plb2wb_bridge_v1_00_a plb2wb_bridge_v1_00_a;\`
103			`vcom $(VHDL_CFLAGS) -work plb2wb_bridge_v1_00_a \`
104			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_pkg.vhd" \`
105			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_short_impulse.vhd" \`
106			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_4.vhd" \`
107			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_4.vhd" \`
108			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_3.vhd" \`
109			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_3.vhd" \`
110			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_2.vhd" \`
111			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_2.vhd" \`
112			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_cc_1.vhd" \`
113			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr_ic_1.vhd" \`
114			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_adr.vhd" \`
115			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_cc_32.vhd" \`
116			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat_ic_32.vhd" \`
117			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_rdat.vhd" \`
118			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_cc_32.vhd" \`
119			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat_ic_32.vhd" \`
120			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_wdat.vhd" \`
121			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb.vhd" \`
122			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_4.vhd" \`
123			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_4.vhd" \`
124			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_3.vhd" \`
125			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_3.vhd" \`
126			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_2.vhd" \`
127			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_2.vhd" \`
128			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_ic_1.vhd" \`
129			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2plb_cc_1.vhd" \`
130			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb.vhd" \`
131			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_ic.vhd" \`
132			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/fifo_stat2wb_cc.vhd" \`
133			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_fifo.vhd" \`
134			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_stu.vhd" \`
135			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_tcu.vhd" \`
136			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_amu.vhd" \`
137			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_rbuf.vhd" \`
138			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_wbuf.vhd" \`
139			`"$(WISHBONE_LIB_DIR)/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/plb2wb_bridge.vhd"`
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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [common/] [Makefile] - Blame information for rev 2