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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_err_and_rst/] [simulation/] [test_cases/] [errors_and_rst/] [transfers.bfl] - Blame information for rev 2

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 set_alias(PART         = 1)
 set_alias(SUBPART      = 2)
 set_alias(SUBSUBPART   = 3)
 
 
 ---------------------------------
 --  32-Bit Master              --
 
 set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
 configure(msize=00)
 mem_update(addr=00010000,data=00000000_00000000_00000000_00000000)
 mem_update(addr=00010010,data=00000000_00000000_00000000_00000000)
 
 
 mem_update(addr=f0000000,data=11000001_11000002_11000003_11000004)
 mem_update(addr=f0000010,data=11111111_11111112_11111113_11111114)
 mem_update(addr=f0000020,data=11222221_11222222_11222223_11222224)
 mem_update(addr=f0000030,data=11333331_11333332_11333333_11333334)
 
 mem_update(addr=f1000000,data=22000001_22000002_22000003_22000004)
 mem_update(addr=f1000010,data=22111111_22111112_22111113_22111114)
 mem_update(addr=f1000020,data=22222221_22222222_22222223_22222224)
 mem_update(addr=f1000030,data=22333331_22333332_22333333_22333334)
 
 mem_update(addr=f2000000,data=33000001_33000002_33000003_33000004)
 mem_update(addr=f2000010,data=33111111_33111112_33111113_33111114)
 mem_update(addr=f2000020,data=33222221_33222222_33222223_33222224)
 mem_update(addr=f2000030,data=33333331_33333332_33333333_33333334)
 
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 
 
 write   ( addr=f0000000, size=0000, be=1111 )
 write   ( addr=f0000004, size=0000, be=1111 )
 -- we will get an error on wb-side after two successful writes
 write   ( addr=f0000008, size=0000, be=1111 )
 
 
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 -- we're now checking the status registers:
 mem_update( addr=00010000, data=20000000 )
 mem_update( addr=00010004, data=11000003 )
 mem_update( addr=00010008, data=f0000008 )
 read  ( addr=00010000, size=0001, be=1111 )
 read  ( addr=00010004, size=0000, be=1111 )
 read  ( addr=00010008, size=0000, be=1111 )
 
 -- we have to clear the exception
 mem_update( addr=00010000, data=00000000 )
 write   ( addr=00010000, size=0000, be=1111 )
 
 -- we abort the transfer
 write   ( addr=00010008, size=0000, be=1111 )
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 
 
 ------------------
 
 write   ( addr=f0000000, size=0001, be=1111 )
 -- we wait (this simulates the interrupt-latency)
 -- and continue the transfer
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
 write   ( addr=00010000, size=0000, be=1111 )
 
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 
 
 --------------------
 
 
 write   ( addr=f1000000, size=0001, be=1111 )
 -- we wait (this simulates the interrupt-latency)
 -- and continue the transfer
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
 write   ( addr=00010000, size=0000, be=1111 )
 
 
 
 wait( level=SUBSUBPART )
 wait( level=SUBSUBPART )
 
 
 --------------------
 
 
  write   ( addr=f2000000, size=0010, be=1111 )
  -- we wait (this simulates the interrupt-latency)
  -- and continue the transfer
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  wait( level=SUBSUBPART )
  write   ( addr=00010004, size=0000, be=1111 )
 -- we have to clear the exception
  write   ( addr=00010000, size=0000, be=1111 )
 
 
 
 
 -- this causes several address-pipelining situations
 read    ( addr=f1000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=0001, be=1111 )
 read    ( addr=f1000000, size=0000, be=1111 )
 read    ( addr=f1000000, size=1010, be=0011 )
 read    ( addr=f2000000, size=1010, be=0011 )
 read    ( addr=f2000000, size=0001, be=1111 )
 read    ( addr=f1000000, size=1010, be=0010 )
 read    ( addr=f2000000, size=0000, be=1111 )
 read    ( addr=f2000000, size=1010, be=0001 )
 
 
 wait( level=SUBPART )
 wait( level=SUBPART )
 
 -- we're now checking the status registers:
 mem_update( addr=00010000, data=40000000 )
 read  ( addr=00010000, size=0000, be=1111 )
 mem_update( addr=00010000, data=00000000 )
 
 -- clear the interrupt
 write   ( addr=00010000, size=0000, be=1111 )
 

Line No.	Rev	Author	Line
1	2	feddischso
2			`set_alias(PART = 1)`
3			`set_alias(SUBPART = 2)`
4			`set_alias(SUBSUBPART = 3)`
5
6
7			`---------------------------------`
8			`-- 32-Bit Master --`
9
10			`set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)`
11			`configure(msize=00)`
12			`mem_update(addr=00010000,data=00000000_00000000_00000000_00000000)`
13			`mem_update(addr=00010010,data=00000000_00000000_00000000_00000000)`
14
15
16			`mem_update(addr=f0000000,data=11000001_11000002_11000003_11000004)`
17			`mem_update(addr=f0000010,data=11111111_11111112_11111113_11111114)`
18			`mem_update(addr=f0000020,data=11222221_11222222_11222223_11222224)`
19			`mem_update(addr=f0000030,data=11333331_11333332_11333333_11333334)`
20
21			`mem_update(addr=f1000000,data=22000001_22000002_22000003_22000004)`
22			`mem_update(addr=f1000010,data=22111111_22111112_22111113_22111114)`
23			`mem_update(addr=f1000020,data=22222221_22222222_22222223_22222224)`
24			`mem_update(addr=f1000030,data=22333331_22333332_22333333_22333334)`
25
26			`mem_update(addr=f2000000,data=33000001_33000002_33000003_33000004)`
27			`mem_update(addr=f2000010,data=33111111_33111112_33111113_33111114)`
28			`mem_update(addr=f2000020,data=33222221_33222222_33222223_33222224)`
29			`mem_update(addr=f2000030,data=33333331_33333332_33333333_33333334)`
30
31
32			`wait( level=SUBSUBPART )`
33			`wait( level=SUBSUBPART )`
34
35
36			`write ( addr=f0000000, size=0000, be=1111 )`
37			`write ( addr=f0000004, size=0000, be=1111 )`
38			`-- we will get an error on wb-side after two successful writes`
39			`write ( addr=f0000008, size=0000, be=1111 )`
40
41
42
43			`wait( level=SUBSUBPART )`
44			`wait( level=SUBSUBPART )`
45			`-- we're now checking the status registers:`
46			`mem_update( addr=00010000, data=20000000 )`
47			`mem_update( addr=00010004, data=11000003 )`
48			`mem_update( addr=00010008, data=f0000008 )`
49			`read ( addr=00010000, size=0001, be=1111 )`
50			`read ( addr=00010004, size=0000, be=1111 )`
51			`read ( addr=00010008, size=0000, be=1111 )`
52
53			`-- we have to clear the exception`
54			`mem_update( addr=00010000, data=00000000 )`
55			`write ( addr=00010000, size=0000, be=1111 )`
56
57			`-- we abort the transfer`
58			`write ( addr=00010008, size=0000, be=1111 )`
59
60			`wait( level=SUBSUBPART )`
61			`wait( level=SUBSUBPART )`
62
63
64			`------------------`
65
66			`write ( addr=f0000000, size=0001, be=1111 )`
67			`-- we wait (this simulates the interrupt-latency)`
68			`-- and continue the transfer`
69			`wait( level=SUBSUBPART )`
70			`wait( level=SUBSUBPART )`
71			`write ( addr=00010004, size=0000, be=1111 )`
72			`-- we have to clear the exception`
73			`write ( addr=00010000, size=0000, be=1111 )`
74
75
76			`wait( level=SUBSUBPART )`
77			`wait( level=SUBSUBPART )`
78
79
80			`--------------------`
81
82
83			`write ( addr=f1000000, size=0001, be=1111 )`
84			`-- we wait (this simulates the interrupt-latency)`
85			`-- and continue the transfer`
86			`wait( level=SUBSUBPART )`
87			`wait( level=SUBSUBPART )`
88			`wait( level=SUBSUBPART )`
89			`write ( addr=00010004, size=0000, be=1111 )`
90			`-- we have to clear the exception`
91			`write ( addr=00010000, size=0000, be=1111 )`
92
93
94
95			`wait( level=SUBSUBPART )`
96			`wait( level=SUBSUBPART )`
97
98
99			`--------------------`
100
101
102			`write ( addr=f2000000, size=0010, be=1111 )`
103			`-- we wait (this simulates the interrupt-latency)`
104			`-- and continue the transfer`
105			`wait( level=SUBSUBPART )`
106			`wait( level=SUBSUBPART )`
107			`wait( level=SUBSUBPART )`
108			`wait( level=SUBSUBPART )`
109			`write ( addr=00010004, size=0000, be=1111 )`
110			`-- we have to clear the exception`
111			`write ( addr=00010000, size=0000, be=1111 )`
112
113
114
115
116			`-- this causes several address-pipelining situations`
117			`read ( addr=f1000000, size=0000, be=1111 )`
118			`read ( addr=f2000000, size=0000, be=1111 )`
119			`read ( addr=f2000000, size=0001, be=1111 )`
120			`read ( addr=f1000000, size=0000, be=1111 )`
121			`read ( addr=f1000000, size=1010, be=0011 )`
122			`read ( addr=f2000000, size=1010, be=0011 )`
123			`read ( addr=f2000000, size=0001, be=1111 )`
124			`read ( addr=f1000000, size=1010, be=0010 )`
125			`read ( addr=f2000000, size=0000, be=1111 )`
126			`read ( addr=f2000000, size=1010, be=0001 )`
127
128
129			`wait( level=SUBPART )`
130			`wait( level=SUBPART )`
131
132			`-- we're now checking the status registers:`
133			`mem_update( addr=00010000, data=40000000 )`
134			`read ( addr=00010000, size=0000, be=1111 )`
135			`mem_update( addr=00010000, data=00000000 )`
136
137			`-- clear the interrupt`
138			`write ( addr=00010000, size=0000, be=1111 )`
139

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_err_and_rst/] [simulation/] [test_cases/] [errors_and_rst/] [transfers.bfl] - Blame information for rev 2